Re: qemu/powernv: coreboot support?

On Sat, Oct 19, 2019 at 10:15:19PM +1100, David Gibson wrote: > On Fri, Oct 18, 2019 at 12:28:29PM -0500, Marty E. Plummer wrote: > > Hello, > > > > First off, thank you for the work you've done on the ppc64 support, it > > has been very useful. I'm currently working on a coreboot port for the >

[PATCH 0/1] Update Bulgarian translation

From: Alexander Shopov This is the updated Bulgarian translation of Qemu It has 1 new message translated and corresponds to v 4.1.0 and up I am sending to the devel list, the trivial patch list and all people listes as CC, Tested-By, Approved-By in the po dir Please ping if that is too wide an

[PATCH 1/1] Updated Bulgarian translation (19) - 4.1.0

From: Alexander Shopov Signed-off-by: Alexander Shopov --- po/bg.po | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/po/bg.po b/po/bg.po index 3d8c353372..98c57e5b22 100644 --- a/po/bg.po +++ b/po/bg.po @@ -1,14 +1,14 @@ # Bulgarian translation of qemu po-file.

Re: qemu/powernv: coreboot support?

On 18/10/2019 19:28, Marty E. Plummer wrote: > Hello, > > First off, thank you for the work you've done on the ppc64 support, it > has been very useful. I'm currently working on a coreboot port for the > talos ii line of systems (which means more ppc64 support, support > specifically for the

[PATCH 1/1] Updated Bulgarian translation (19) - 4.1.0

Signed-off-by: Alexander Shopov --- po/bg.po | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/po/bg.po b/po/bg.po index 3d8c353372..98c57e5b22 100644 --- a/po/bg.po +++ b/po/bg.po @@ -1,14 +1,14 @@ # Bulgarian translation of qemu po-file. -# Copyright (C) 2016

[PATCH 0/1] Update Bulgarian translation

This is the updated Bulgarian translation of Qemu It has 1 new message translated and corresponds to v 4.1.0 and up I am sending to the devel list, the trivial patch list and all people listes as CC, Tested-By, Approved-By in the po dir Please ping if that is too wide an audience and point me to

Re: [PATCH v2] Do not use %m in common code to print error messages

On Fri, Oct 18, 2019 at 06:01:22PM +0200, Thomas Huth wrote: > On 18/10/2019 15.49, Kamil Rytarowski wrote: > > On 18.10.2019 15:42, Stefano Garzarella wrote: > >> On Fri, Oct 18, 2019 at 03:07:16PM +0200, Thomas Huth wrote: > >>> The %m format specifier is an extension from glibc - and when

Re: [PATCH v5 1/3] tests/vm: netbsd autoinstall, using serial console

On 18/10/2019 20.17, Eduardo Habkost wrote: > From: Gerd Hoffmann > > Instead of fetching the prebuilt image from patchew download the install > iso and prepare the image locally. Install to disk, using the serial > console. Create qemu user, configure ssh login. Install packages > needed for

Re: [PATCH v2 2/2] migration: savevm_state_handler_insert: constant-time element insertion

On Fri, Oct 18, 2019 at 10:43:52AM +0100, Dr. David Alan Gilbert wrote: > * Laurent Vivier (lviv...@redhat.com) wrote: > > On 18/10/2019 10:16, Dr. David Alan Gilbert wrote: > > > * Scott Cheloha (chel...@linux.vnet.ibm.com) wrote: > > >> savevm_state's SaveStateEntry TAILQ is a priority queue.

Re: [PATCH v2 00/20] hw/i386/pc: Split PIIX3 southbridge from i440FX northbridge

Patchew URL: https://patchew.org/QEMU/20191018134754.16362-1-phi...@redhat.com/ Hi, This series seems to have some coding style problems. See output below for more information: Subject: [PATCH v2 00/20] hw/i386/pc: Split PIIX3 southbridge from i440FX northbridge Type: series Message-id:

Re: [PATCH 7/8] hw/m68k/mcf5206.c: Switch to transaction-based ptimer API

Am Sat, 19 Oct 2019 12:48:59 +0200 schrieb Thomas Huth : > Am Thu, 17 Oct 2019 14:29:04 +0100 > schrieb Peter Maydell : > > > Switch the mcf5206 code away from bottom-half based ptimers to > > the new transaction-based ptimer API. This just requires adding > > begin/commit calls around the

Re: [PATCH 7/8] hw/m68k/mcf5206.c: Switch to transaction-based ptimer API

Am Sat, 19 Oct 2019 13:10:27 +0200 schrieb Thomas Huth : > Am Sat, 19 Oct 2019 12:48:59 +0200 > schrieb Thomas Huth : > > > Am Thu, 17 Oct 2019 14:29:04 +0100 > > schrieb Peter Maydell : > > > > > Switch the mcf5206 code away from bottom-half based ptimers to > > > the new transaction-based

Re: [PATCH v5 00/13] Multi-phase reset mechanism

Patchew URL: https://patchew.org/QEMU/20191018150630.31099-1-damien.he...@greensocs.com/ Hi, This series failed the docker-mingw@fedora build test. Please find the testing commands and their output below. If you have Docker installed, you can probably reproduce it locally. === TEST SCRIPT

Re: [PATCH 8/8] hw/m68k/mcf5208.c: Switch to transaction-based ptimer API

Am Thu, 17 Oct 2019 14:29:05 +0100 schrieb Peter Maydell : > Switch the mcf5208 code away from bottom-half based ptimers to > the new transaction-based ptimer API. This just requires adding > begin/commit calls around the various places that modify the ptimer > state, and using the new

Re: [PATCH 7/8] hw/m68k/mcf5206.c: Switch to transaction-based ptimer API

Am Thu, 17 Oct 2019 14:29:04 +0100 schrieb Peter Maydell : > Switch the mcf5206 code away from bottom-half based ptimers to > the new transaction-based ptimer API. This just requires adding > begin/commit calls around the various places that modify the ptimer > state, and using the new

Re: qemu/powernv: coreboot support?

On Fri, Oct 18, 2019 at 12:28:29PM -0500, Marty E. Plummer wrote: > Hello, > > First off, thank you for the work you've done on the ppc64 support, it > has been very useful. I'm currently working on a coreboot port for the > talos ii line of systems (which means more ppc64 support, support >

Re: [PATCH v2 10/11] tests/ssh_linux_malta: Refactor how to get image/kernel info

On Saturday, October 19, 2019, Philippe Mathieu-Daudé wrote: > The qcow and kernel images use a similar pattern regarding they > are for big/little endianess, or 32/64 bit. > Refactor using more dictionary keys. > > Signed-off-by: Philippe Mathieu-Daudé > --- >

Re: qemu/powernv: coreboot support?

On 19/10/2019 17:31, Marty E. Plummer wrote: > On Sat, Oct 19, 2019 at 03:46:59PM +0200, Cédric Le Goater wrote: >> On 18/10/2019 19:28, Marty E. Plummer wrote: >>> Hello, >>> >>> First off, thank you for the work you've done on the ppc64 support, it >>> has been very useful. I'm currently working

Re: [PATCH 1/1] Updated Bulgarian translation (19) - 4.1.0

On Saturday, October 19, 2019, Alexander Shopov wrote: > Signed-off-by: Alexander Shopov > --- > po/bg.po | 10 +- > 1 file changed, 5 insertions(+), 5 deletions(-) > > Reviewed-by: Aleksandar Markovic diff --git a/po/bg.po b/po/bg.po > index 3d8c353372..98c57e5b22 100644 > ---

Re: qemu/powernv: coreboot support?

On Sat, Oct 19, 2019 at 05:53:12PM +0200, Cédric Le Goater wrote: > On 19/10/2019 17:31, Marty E. Plummer wrote: > > On Sat, Oct 19, 2019 at 03:46:59PM +0200, Cédric Le Goater wrote: > >> On 18/10/2019 19:28, Marty E. Plummer wrote: > >>> Hello, > >>> > >>> First off, thank you for the work you've

Re: [PATCH v2 06/10] hw/arm/bcm2836: Create VideoCore address space in the SoC

On 10/17/19 3:57 PM, Philippe Mathieu-Daudé wrote: > +static const char *alias_name[] = { > +NULL, "cached-coherent", "cached", "uncached" > +}; While respinning, static const char * const alias_name[] r~

Re: [PATCH v5 01/13] add device_legacy_reset function to prepare for reset api change

On 10/18/19 8:06 AM, Damien Hedde wrote: > Provide a temporary device_legacy_reset function doing what > device_reset does to prepare for the transition with Resettable > API. > > All occurrence of device_reset in the code tree are also replaced > by device_legacy_reset. > > The new resettable

[PATCH] net: add tulip (dec21143) driver

This adds the basic functionality to emulate a Tulip NIC. Implemented are: - RX and TX functionality - Perfect Frame Filtering - Big/Little Endian descriptor support - 93C46 EEPROM support - LXT970 PHY Not implemented, mostly because i had no OS using these functions: - Imperfect frame

Re: [PATCH v5 02/13] hw/core/qdev: add trace events to help with resettable transition

On 10/18/19 8:06 AM, Damien Hedde wrote: > Adds trace events to reset procedure and when updating the parent > bus of a device. > > Signed-off-by: Damien Hedde > --- > hw/core/qdev.c | 27 --- > hw/core/trace-events | 9 + > 2 files changed, 33

Re: [PATCH v5 04/13] hw/core: add Resettable support to BusClass and DeviceClass

On 10/18/19 8:06 AM, Damien Hedde wrote: > This commit adds support of Resettable interface to buses and devices: > + ResettableState structure is added in the Bus/Device state > + Resettable methods are implemented. > + device/bus_is_in_reset function defined > > This commit allows to transition

Re: [PATCH v7 1/3] target/ppc: Optimize emulation of vclzh and vclzb instructions

On Thursday, October 17, 2019, Stefan Brankovic wrote: > Optimize Altivec instruction vclzh (Vector Count Leading Zeros Halfword). > This instruction counts the number of leading zeros of each halfword > element > in source register and places result in the appropriate halfword element of >

[PATCH v3 03/16] hw/timer/bcm2835: Add the BCM2835 SYS_timer

Add the 64-bit free running timer. Do not model the COMPARE register (no IRQ generated). This timer is used by Linux kernel and recently U-Boot: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/clocksource/bcm2835_timer.c?h=v3.7

[PATCH v3 00/16] hw/arm/raspi: Add thermal/timer, improve address space, run U-boot

Since v2: - fixed issue in videocore address space - allow to start with some cores OFF (to boot firmwares) - add proof-of-concept test for '-smp cores=1' and U-boot - fixed my email setup Previous cover: Hi, Some patches from v1 are already merged. This v2 addresses the review comment from v1,

[PATCH v3 01/16] hw/misc/bcm2835_thermal: Add a dummy BCM2835 thermal sensor

We will soon implement the SYS_timer. This timer is used by Linux in the thermal subsystem, so once available, the subsystem will be enabled and poll the temperature sensors. We need to provide the minimum required to keep Linux booting. Add a dummy thermal sensor returning ~25°C based on:

Re: qemu/powernv: coreboot support?

On Sat, Oct 19, 2019 at 05:53:12PM +0200, Cédric Le Goater wrote: > On 19/10/2019 17:31, Marty E. Plummer wrote: > > On Sat, Oct 19, 2019 at 03:46:59PM +0200, Cédric Le Goater wrote: > >> On 18/10/2019 19:28, Marty E. Plummer wrote: > >>> Hello, > >>> > >>> First off, thank you for the work you've

Re: qemu/powernv: coreboot support?

On Sat, Oct 19, 2019 at 05:53:12PM +0200, Cédric Le Goater wrote: > On 19/10/2019 17:31, Marty E. Plummer wrote: > > On Sat, Oct 19, 2019 at 03:46:59PM +0200, Cédric Le Goater wrote: > >> On 18/10/2019 19:28, Marty E. Plummer wrote: > >>> Hello, > >>> > >>> First off, thank you for the work you've

Re: [PATCH v32 04/13] target/avr: Add instruction translation - Registers definition

On Fri, Oct 18, 2019 at 9:08 PM Aleksandar Markovic wrote: > > > > On Friday, October 18, 2019, Aleksandar Markovic > wrote: >> >> >> >> On Friday, October 18, 2019, Michael Rolnik wrote: >>> >>> On Fri, Oct 18, 2019 at 4:23 PM Aleksandar Markovic >>> wrote: >>> > >>> > >>> > >>> > On Friday,

[PATCH v3 12/16] hw/arm/bcm2836: Rename enabled_cpus -> enabled_cores

We now use -smp cores= to limit the number of cores powered on reset. Rename the 'enabled_cpus' variable as 'enabled_cores' to better match the new use. No functional changes. Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/bcm2836.c | 4 ++-- hw/arm/raspi.c | 2 +-

[PATCH v3 10/16] hw/arm/raspi: Use AddressSpace when using arm_boot::write_secondary_boot

write_secondary_boot() is used in SMP configurations where the CPU address space might not be the main System Bus. The rom_add_blob_fixed_as() function allow us to specify an address space. Use it to write each boot blob in the corresponding CPU address space. Signed-off-by: Philippe

[PATCH NOTFORMERGE v3 16/16] tests/acceptance: Test U-boot on the Raspberry Pi 3

This is a proof-of-concept for the '-smp cores=1' feature which restricts the cores brought online on reset. The u-boot binary is old and from an untrusted source, but I don't want to add the build machinery in QEMU, so it is enough to demonstrate the feature works reliably. By default this test

[PATCH v3 13/16] hw/arm/raspi: Make the board code modular

Our code currently create the raspi2 (based on the BCM2836) and the raspi3 (on the BCM2837). Similarly, the raspi4 is based on the BCM2838. To be able to add the new board, make the current code more modular: - Dynamically fills the 'board-rev' value - Allow DRAM sizes different than 1 GiB

Re: [PATCH v7 3/3] target/ppc: Optimize emulation of vupkhpx and vupklpx instructions

On Thursday, October 17, 2019, Stefan Brankovic wrote: > 'trans_vupkpx' function implements both vupkhpx and vupklpx instructions > with > argument 'high' determine which instruction is processed. Instructions are > implemented in two 'for' loops. Outer 'for' loop repeats unpacking two > times,

Re: [PATCH v7 3/3] target/ppc: Optimize emulation of vupkhpx and vupklpx instructions

On Thursday, October 17, 2019, Stefan Brankovic wrote: > 'trans_vupkpx' function implements both vupkhpx and vupklpx instructions > with > argument 'high' determine which instruction is processed. Instructions are > implemented in two 'for' loops. Outer 'for' loop repeats unpacking two > times,

Fwd: IGD assignment / Legacy Mode Question

Hello, We are using IGD legacy assignment to start our Vm on Intel nuc platform ( generation 7, 8 ) with succes. However, in some cases, we must set rombar to off and sometime rombar set to on in order to start the Vm. We are using Windows 10 : according to the hardware ( intel nuc 6,7,8

[PATCH v3 04/16] hw/arm/bcm2835_peripherals: Use the SYS_timer

Connect the recently added SYS_timer. Now U-Boot does not hang anymore polling a free running counter stuck at 0. This timer is also used by the Linux kernel thermal subsystem. Reviewed-by: Alistair Francis Signed-off-by: Philippe Mathieu-Daudé --- v2: Remove spurious error check (Alex) ---

[PATCH v3 06/16] hw/arm/bcm2836: Rename cpus[] as cpu[].core

As we are going to add more core-specific fields, add a 'cpu' structure and move the ARMCPU field there as 'core'. Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/bcm2836.c | 26 ++ include/hw/arm/bcm2836.h | 4 +++- 2 files changed, 17 insertions(+), 13

[PATCH v3 11/16] hw/arm/raspi: Use -smp cores= option to restrict enabled cores

The abstract TYPE_BCM283X device provides a 'enabled-cpus' property to restrict the number of cores powered on reset. This because on real hardware the GPU is responsible of starting the cores and keep them spinning until the Linux kernel is ready to use them. When using the -kernel paramenter,

[PATCH v3 02/16] hw/arm/bcm2835_peripherals: Use the thermal sensor block

Map the thermal sensor in the BCM2835 block. Reviewed-by: Alistair Francis Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/bcm2835_peripherals.c | 13 + include/hw/arm/bcm2835_peripherals.h | 2 ++ include/hw/arm/raspi_platform.h | 1 + 3 files changed, 16

[PATCH v3 05/16] hw/arm/bcm2836: Make the SoC code modular

This file creates the BCM2836/BCM2837 blocks. The biggest differences with the BCM2838 we are going to add, are the base addresses of the interrupt controller and the peripherals. Add these addresses in the BCM283XInfo structure to make this block more modular. Remove the MCORE_OFFSET offset as it

Re: [PATCH v7 3/3] target/ppc: Optimize emulation of vupkhpx and vupklpx instructions

On Thursday, October 17, 2019, Stefan Brankovic wrote: > 'trans_vupkpx' function implements both vupkhpx and vupklpx instructions > with implements both -> implements emulation of both with -> , while its argument 'high' determine which determine -> determines > instruction is processed.

Re: [PATCH v7 2/3] target/ppc: Optimize emulation of vpkpx instruction

On Thursday, October 17, 2019, Stefan Brankovic wrote: > Optimize altivec instruction vpkpx (Vector Pack Pixel). > Rearranges 8 pixels coded in 6-5-5 pattern (4 from each source register) > into contigous array of bits in the destination register. > > In each iteration of outer loop, the

Re: [PATCH v7 0/3] target/ppc: Optimize emulation of some Altivec instructions

On Thursday, October 17, 2019, Stefan Brankovic wrote: > Optimize emulation of ten Altivec instructions: lvsl, lvsr, vsl, vsr, > vpkpx, > vgbbd, vclzb, vclzh, vclzw, vclzd, vupkhpx and vupklpx. > > ten -> twelve > This series buils up on and complements > buils -> builds > recent work of

Re: [PATCH 0/1] Update Bulgarian translation

Patchew URL: https://patchew.org/QEMU/20191019120534.27479-1-...@kambanaria.org/ Hi, This series failed the docker-quick@centos7 build test. Please find the testing commands and their output below. If you have Docker installed, you can probably reproduce it locally. === TEST SCRIPT BEGIN ===

[PATCH v3 07/16] hw/arm/bcm2836: Use per CPU address spaces

Currently all CPUs access the main system bus. Let each CPU have his own address space. Before: (qemu) info mtree address-space: memory - (prio 0, i/o): system -3fff (prio 0, ram): ram

[PATCH v3 08/16] hw/arm/bcm2835_peripherals: Add const link property in realize()

The VideoCore GPU is indenpendant from the Peripheral block. In the next commit, we will move its instantiation to the SoC block. The "gpu-bus" object will not be accessible in init() but later in realize(). As a preliminary step to keep the diff clearer, move the const link property creation from

[PATCH v3 09/16] hw/arm/bcm2836: Create VideoCore address space in the SoC

Currently the VideoCore is created in the Peripheral container as the 'GPU bus'. It is created there because the peripherals using DMA use physical addresses from the VideoCore bus. However the VideoCore is a GPU core placed at the same hierarchical level than the ARM cores. To match the

[PATCH v3 14/16] hw/arm/highbank: Use AddressSpace when using write_secondary_boot()

write_secondary_boot() is used in SMP configurations where the CPU address space might not be the main System Bus. The rom_add_blob_fixed_as() function allow us to specify an address space. Use it to write each boot blob in the corresponding CPU address space. Signed-off-by: Philippe

[PATCH v3 15/16] python/qemu/machine: Allow to use other serial consoles than default

Currently the QEMU Python module limits the QEMUMachine class to use the first serial console. Some machines/guest might use another console than the first one as the 'boot console'. For example the Raspberry Pi uses the second (AUX) console. To be able to use the Nth console as default, we

[Bug 1848901] [NEW] kvm_mem_ioeventfd_add: error adding ioeventfd: No space left on device (28)

Public bug reported: => QEMU process has stopped, return code: -6 Start QEMU with /usr/bin/qemu-system-x86_64 -name CiscoASAv9.8.1-1 -m 2048M -smp cpus=1 -enable-kvm -machine smm=off -boot order=c -drive 'file=/home/deemon/GNS3/projects/ASAv my ass/project-files/qemu /7725cdea-5e66-4777-b4dd-

[Bug 1848901] Re: kvm_mem_ioeventfd_add: error adding ioeventfd: No space left on device (28)

QEMU 4.1.0 btw. -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1848901 Title: kvm_mem_ioeventfd_add: error adding ioeventfd: No space left on device (28) Status in QEMU: New Bug description:

[Bug 1848901] Re: kvm_mem_ioeventfd_add: error adding ioeventfd: No space left on device (28)

correct hash from GNS3 webpage then* -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1848901 Title: kvm_mem_ioeventfd_add: error adding ioeventfd: No space left on device (28) Status in QEMU:

[Bug 1848901] Re: kvm_mem_ioeventfd_add: error adding ioeventfd: No space left on device (28)

Was trying to start Cisco ASAv 9.8.1 (with the correct hash from your own webpage) through GNS3 on Manjaro when this happened. -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1848901 Title:

Re: [PATCH v3 1/2] hw: timer: Add Goldfish RTC device

On Saturday, October 19, 2019, Anup Patel wrote: > Hi, > > From: Aleksandar Markovic > Sent: Saturday, October 19, 2019 2:45 AM > To: Anup Patel > Cc: Peter Maydell ; Palmer Dabbelt < > pal...@sifive.com>; Alistair Francis ; Sagar > Karandikar ; Bastian Koppelmann < >

[PATCH v3 08/16] libqos: implement VIRTIO 1.0 FEATURES_OK step

Device initialization has an extra step in VIRTIO 1.0. The FEATURES_OK status bit is set to indicate that feature negotiation has completed. The driver then reads the status register again to check that the device agrees with the final features. Implement this step as part of

[PATCH v3 07/16] libqos: enforce Device Initialization order

According to VIRTIO 1.1 "3.1.1 Driver Requirements: Device Initialization", configuration space and virtqueues cannot be accessed before features have been negotiated. Enforce this requirement. Signed-off-by: Stefan Hajnoczi --- tests/libqos/virtio.c | 11 +++ 1 file changed, 11

[PATCH v3 11/16] libqos: pass full QVirtQueue to set_queue_address()

Instead of just passing the vring page frame number, pass the full QVirtQueue. This will allow the VIRTIO 1.0 transport to program the fine-grained vring address registers in the future. Signed-off-by: Stefan Hajnoczi Reviewed-by: Sergio Lopez Reviewed-by: Thomas Huth ---

[PATCH v3 14/16] libqos: make the virtio-pci BAR index configurable

The Legacy virtio-pci interface always uses BAR 0. VIRTIO 1.0 may need to use a different BAR index, so make it configurable. Signed-off-by: Stefan Hajnoczi --- v3: * Change uint8_t bar_idx to int [Thomas] --- tests/libqos/virtio-pci.h | 2 ++ tests/libqos/virtio-pci.c | 3 ++- 2 files

Re: [PATCH v2 2/2] spapr/xive: Set the OS CAM line at reset

On Fri, 18 Oct 2019 19:22:19 +0200 Cédric Le Goater wrote: > When a Virtual Processor is scheduled to run on a HW thread, the > hypervisor pushes its identifier in the OS CAM line. When running with > kernel_irqchip=off, QEMU needs to emulate the same behavior. > > Set the OS CAM line when the

[PATCH v3 04/16] virtio-scsi-test: add missing feature negotiation

VIRTIO Device Initialization requires feature negotiation. Currently virtio-scsi-test.c is non-compliant. Signed-off-by: Stefan Hajnoczi --- tests/virtio-scsi-test.c | 8 1 file changed, 8 insertions(+) diff --git a/tests/virtio-scsi-test.c b/tests/virtio-scsi-test.c index

[PATCH v3 03/16] libqos: extend feature bits to 64-bit

In VIRTIO 1.0 feature bits changed from 32-bit to 64-bit. (In fact, the transports allow even more feature bits but nothing uses more than 64 bits today.) Add 64-bit feature bit support to virtio-mmio and virtio-pci. This will be necessary for VIRTIO 1.0 support. Signed-off-by: Stefan Hajnoczi

[PATCH v3 00/16] libqos: add VIRTIO PCI 1.0 support

v3: * Now implements VIRTIO 1.0 fully (vring, device initialization). This required several new patches to address the following issues: 1. Tests that do not negotiate features (non-compliant!) 2. Tests that access configuration space before feature negotiation (non-compliant!)

[PATCH v3 02/16] libqos: read QVIRTIO_MMIO_VERSION register

There was no real virtio-mmio ABI change between Legacy and VIRTIO 1.0 except that the Version field was incremented from 1 to 2. However, QEMU does not allow Legacy drivers to perform VIRTIO 1.0 operations like accessing 64-bit feature bits. Since we will introduce 64-bit feature bit support we

[PATCH v3 09/16] libqos: access VIRTIO 1.0 vring in little-endian

VIRTIO 1.0 uses little-endian for the vring. Legacy VIRTIO uses guest endianness. Adjust the code to handle both. Note that qvirtio_readq() is not defined because it has no users. All the other accessors are really needed. Signed-off-by: Stefan Hajnoczi --- tests/libqos/virtio.h | 4

[PATCH v3 10/16] libqos: add iteration support to qpci_find_capability()

VIRTIO 1.0 PCI devices have multiple PCI_CAP_ID_VNDR capabilities so we need a way to iterate over them. Extend qpci_find_capability() to take the last address. Signed-off-by: Stefan Hajnoczi -- v3: * Document qpci_find_capability() --- tests/libqos/pci.h | 2 +- tests/libqos/pci.c | 30

[PATCH v3 13/16] libqos: expose common virtqueue setup/cleanup functions

The VIRTIO 1.0 code will need to perform additional steps but it will reuse the common virtqueue setup/cleanup code. Make these functions public. Make sure to invoke callbacks via QVirtioBus instead of directly calling the virtio-pci Legacy versions of these functions. Signed-off-by: Stefan

Re: [PATCH v2 1/2] spapr: Introduce a interrupt presenter reset handler

On Fri, 18 Oct 2019 19:22:18 +0200 Cédric Le Goater wrote: > The interrupt presenters are created by a machine handler at the core > level and are reseted independently. This is not consistent and it > raises some issues when it comes to handle hot-plugged CPUs. These are > reseted from the

Re: Using virtual IOMMU in guest hypervisors other than KVM and Xen?

On Fri, Oct 18, 2019 at 8:37 PM Peter Xu wrote: > > On Wed, Oct 16, 2019 at 03:01:22PM -0700, Jintack Lim wrote: > > On Mon, Oct 14, 2019 at 7:50 PM Peter Xu wrote: > > > > > > On Mon, Oct 14, 2019 at 01:28:49PM -0700, Jintack Lim wrote: > > > > Hi, > > > > > > Hello, Jintack, > > > > > Hi

[PATCH v3 05/16] tests/virtio-blk-test: set up virtqueue after feature negotiation

VIRTIO Device Initialization requires that feature negotiation has completed before virtqueues are set up. This makes sense because the driver must know whether it is operating in Legacy or VIRTIO 1.0 mode before it can access vring fields with the correct endianness. Signed-off-by: Stefan

[PATCH v3 06/16] libqos: add missing virtio-9p feature negotiation

VIRTIO Device Initialization requires feature negotiation. The libqos virtio-9p driver lacks feature negotiation and is therefore non-compliant. Signed-off-by: Stefan Hajnoczi --- tests/libqos/virtio-9p.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/tests/libqos/virtio-9p.c

[PATCH v3 01/16] tests/virtio-blk-test: read config space after feature negotiation

The VIRTIO Configuration Space cannot be accessed before device feature bits have been read because a driver doesn't know the endianness until it has checked VIRTIO_F_VERSION_1. Fix this problem in preparation for VIRTIO 1.0 support. Signed-off-by: Stefan Hajnoczi --- tests/virtio-blk-test.c |

[PATCH v3 16/16] libqos: add VIRTIO PCI 1.0 support

Implement the VIRTIO 1.0 virtio-pci interface. The main change here is that the register layout is no longer a fixed layout in BAR 0. Instead we have to iterate of PCI Capabilities to find descriptions of where various registers are located. The vring registers are also more fine-grained,

[PATCH v3 12/16] libqos: add MSI-X callbacks to QVirtioPCIDevice

The MSI-X vectors are programmed differently in the VIRTIO 1.0 and Legacy interfaces. Introduce callbacks so different implementations can be used depending on the interface version. Signed-off-by: Stefan Hajnoczi Reviewed-by: Sergio Lopez Reviewed-by: Thomas Huth ---

[PATCH v3 15/16] libqos: extract Legacy virtio-pci.c code

The current libqos virtio-pci.c code implements the VIRTIO Legacy interface. Extract existing code in preparation for VIRTIO 1.0 support. Signed-off-by: Stefan Hajnoczi Reviewed-by: Sergio Lopez Reviewed-by: Thomas Huth --- tests/libqos/virtio-pci.h | 2 -- tests/libqos/virtio-pci.c | 29

[PATCH 06/11] tests/boot_linux_console: Run BusyBox on 5KEc 64-bit cpu

This tests boots a Linux kernel on a Malta machine up to a busybox shell on the serial console. Few commands are executed before halting the machine (via reboot). We use the Fedora 24 kernel extracted from the image at: https://fedoraproject.org/wiki/Architectures/MIPS and the initrd cpio image

[PATCH 02/11] tests/acceptance: Fixe wait_for_console_pattern() hangs

From: Philippe Mathieu-Daudé Because of a possible deadlock (QEMU waiting for the socket to become writable) let's close the console socket as soon as we stop to use it. Suggested-by: Cleber Rosa Signed-off-by: Philippe Mathieu-Daudé --- tests/acceptance/avocado_qemu/__init__.py | 1 + 1

[PATCH 03/11] tests/acceptance: Send on serial lines

Some firmwares don't parse the control character and expect a . Signed-off-by: Philippe Mathieu-Daudé --- tests/acceptance/boot_linux_console.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py

[PATCH 00/11] tests/acceptance: Fix 64-bit MIPS target tests

From: PhilMD Commit 9090d3332cdcc introduced a regression which makes the 64-bit target tests to fail. This series fix it (by previously refactoring the linux_ssh_malta test), and also add another test for the 5KEc CPU. I had to include Avocado-related patches not yet merged again to avoid

[PATCH 01/11] Acceptance tests: refactor wait_for_console_pattern

From: Cleber Rosa The same utility method is already present in two different test files, so let's consolidate it into a single utility function. Signed-off-by: Cleber Rosa Message-Id: <20190916164011.7653-1-cr...@redhat.com> Reviewed-by: Philippe Mathieu-Daudé [PMD: failure_message is

[PATCH 07/11] tests/ssh_linux_malta: Run tests using a snapshot image

If a test fails, it can corrupt the underlying QCow2 image, making further tests failing. Fix this by running each test with a snapshot. Signed-off-by: Philippe Mathieu-Daudé --- tests/acceptance/linux_ssh_mips_malta.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git

[PATCH 05/11] tests/boot_linux_console: Use Avocado archive::gzip_uncompress()

Avocado 67.0 [*] introduced the avocado.utils.archive module which provides handling of gzip files. Use the gzip_uncompress() method. [*] https://avocado-framework.readthedocs.io/en/67.0/api/utils/avocado.utils.html#avocado.utils.archive.gzip_uncompress Suggested-by: Cleber Rosa Signed-off-by:

[PATCH 08/11] tests/ssh_linux_malta: Remove duplicated test

Remove duplicated test (probably copy/paste error in commit 9090d3332cdcc). Signed-off-by: Philippe Mathieu-Daudé --- tests/acceptance/linux_ssh_mips_malta.py | 3 --- 1 file changed, 3 deletions(-) diff --git a/tests/acceptance/linux_ssh_mips_malta.py

Re: [PATCH v2 00/20] hw/i386/pc: Split PIIX3 southbridge from i440FX northbridge

On Friday, October 18, 2019, Philippe Mathieu-Daudé wrote: > Changes since v1 [0]: > - Removed patch reintroducing DO_UPCAST() use (thuth) > - Took various patches out to reduce series (thuth) > - Added review tags (thanks all for reviewing!) > > As far as I can tell, a handful of checkpatch

[PATCH 04/11] tests/acceptance: Refactor exec_command_and_wait_for_pattern()

From: Philippe Mathieu-Daudé The same utility method is already present in two different test files, so let's consolidate it into a single utility function. Signed-off-by: Philippe Mathieu-Daudé --- v2: fix self -> test, failure_message is optional, added doc ---

[PATCH 10/11] tests/ssh_linux_malta: Refactor how to get image/kernel info

The qcow and kernel images use a similar pattern regarding they are for big/little endianess, or 32/64 bit. Refactor using more dictionary keys. Signed-off-by: Philippe Mathieu-Daudé --- tests/acceptance/linux_ssh_mips_malta.py | 75 ++-- 1 file changed, 44 insertions(+), 31

[PATCH 09/11] tests/ssh_linux_malta: Match stricter console output

Match on stricter console output. Signed-off-by: Philippe Mathieu-Daudé --- tests/acceptance/linux_ssh_mips_malta.py | 18 +- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/tests/acceptance/linux_ssh_mips_malta.py b/tests/acceptance/linux_ssh_mips_malta.py index

Re: [PATCH v4 0/11] add failover feature for assigned network devices

Patchew URL: https://patchew.org/QEMU/20191018202040.30349-1-jfreim...@redhat.com/ Hi, This series failed the docker-quick@centos7 build test. Please find the testing commands and their output below. If you have Docker installed, you can probably reproduce it locally. === TEST SCRIPT BEGIN

[PATCH 11/11] tests/ssh_linux_malta: Fix 64-bit target tests

Commit 9090d3332cdcc added tests for specific to the 32-bit machines, which inadvertently make the 64-bit tests failing. Now than we have this information available in the CPU_INFO array, use it to have the 64-bit tests back. Signed-off-by: Philippe Mathieu-Daudé --- .mailmap

Re: [PATCH v4 0/11] add failover feature for assigned network devices

Patchew URL: https://patchew.org/QEMU/20191018202040.30349-1-jfreim...@redhat.com/ Hi, This series failed the docker-mingw@fedora build test. Please find the testing commands and their output below. If you have Docker installed, you can probably reproduce it locally. === TEST SCRIPT BEGIN

Re: [PATCH v2 20/20] hw/pci-host/i440fx: Remove the last PIIX3 traces

Hi Aleksandar, On 10/18/19 7:04 PM, Aleksandar Markovic wrote: On Friday, October 18, 2019, Philippe Mathieu-Daudé > wrote: The PIIX3 is not tied to the i440FX and can even be used without it. Move its creation to the machine code (pc_piix.c). We have

Re: qemu/powernv: coreboot support?

On Sat, Oct 19, 2019 at 03:46:59PM +0200, Cédric Le Goater wrote: > On 18/10/2019 19:28, Marty E. Plummer wrote: > > Hello, > > > > First off, thank you for the work you've done on the ppc64 support, it > > has been very useful. I'm currently working on a coreboot port for the > > talos ii line

Re: [PATCH 00/11] tests/acceptance: Fix 64-bit MIPS target tests

On 10/19/19 5:10 PM, Philippe Mathieu-Daudé wrote: From: PhilMD Oh I sent this from a new workspace, and forgot to set git.user.name :S git.sendemail.from doesn't enforce it. I'll simply resend. Commit 9090d3332cdcc introduced a regression which makes the 64-bit target tests to fail. This

[PATCH v2 06/11] tests/boot_linux_console: Run BusyBox on 5KEc 64-bit cpu

This tests boots a Linux kernel on a Malta machine up to a busybox shell on the serial console. Few commands are executed before halting the machine (via reboot). We use the Fedora 24 kernel extracted from the image at: https://fedoraproject.org/wiki/Architectures/MIPS and the initrd cpio image

[PATCH v2 02/11] tests/acceptance: Fixe wait_for_console_pattern() hangs

From: Philippe Mathieu-Daudé Because of a possible deadlock (QEMU waiting for the socket to become writable) let's close the console socket as soon as we stop to use it. Suggested-by: Cleber Rosa Signed-off-by: Philippe Mathieu-Daudé --- tests/acceptance/avocado_qemu/__init__.py | 1 + 1

[PATCH v2 04/11] tests/acceptance: Refactor exec_command_and_wait_for_pattern()

From: Philippe Mathieu-Daudé The same utility method is already present in two different test files, so let's consolidate it into a single utility function. Signed-off-by: Philippe Mathieu-Daudé --- v2: fix self -> test, failure_message is optional, added doc ---

[PATCH v2 00/11] tests/acceptance: Fix 64-bit MIPS target tests

v2: - Fixed GIT_COMMITTER_NAME - do no include Aleksandar Rikalo mailmap change Commit 9090d3332cdcc introduced a regression which makes the 64-bit target tests to fail. This series fix it (by previously refactoring the linux_ssh_malta test), and also add another test for the 5KEc CPU. I had to

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