From: Liu Jingqi
Add -numa hmat-cache option to provide Memory Side Cache Information.
These memory attributes help to build Memory Side Cache Information
Structure(s) in ACPI Heterogeneous Memory Attribute Table (HMAT).
Reviewed-by: Daniel Black
Signed-off-by: Liu Jingqi
Signed-off-by: Tao
From: Liu Jingqi
This structure describes memory side cache information for memory
proximity domains if the memory side cache is present and the
physical device forms the memory side cache.
The software could use this information to effectively place
the data in memory to maximize the
ACPI table HMAT has been introduced, QEMU now builds HMAT tables for
Heterogeneous Memory with boot option '-numa node'.
Add test cases on PC and Q35 machines with 2 numa nodes.
Because HMAT is generated when system enable numa, the
following tables need to be added for this test:
Is this a fresh image or is it possible that it already had some latent
corruption from a previous run with an unfixed version? If it wasn't
fresh, did you run qemu-img check after upgrading QEMU and it still was
clean, so we know the corruption was introduced by the new version?
Is the problem
From: Liu Jingqi
Add -numa hmat-lb option to provide System Locality Latency and
Bandwidth Information. These memory attributes help to build
System Locality Latency and Bandwidth Information Structure(s)
in ACPI Heterogeneous Memory Attribute Table (HMAT).
Signed-off-by: Liu Jingqi
From: Liu Jingqi
HMAT is defined in ACPI 6.3: 5.2.27 Heterogeneous Memory Attribute Table
(HMAT). The specification references below link:
http://www.uefi.org/sites/default/files/resources/ACPI_6_3_final_Jan30.pdf
It describes the memory attributes, such as memory side cache
attributes and
Patchew URL: https://patchew.org/QEMU/20191115075352.17734-1-tao3...@intel.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [PATCH v16 00/14] Build ACPI Heterogeneous Memory Attribute Table
(HMAT)
Type: series
Message-id:
On Thu, Nov 14, 2019 at 02:34:49PM +0100, Jens Freimann wrote:
> When an error occurs in migrate_add_blocker() it sets a
> negative return value and uses error pointer we pass in.
> Instead of just looking at the error pointer check for a negative return
> value and avoid a coverity error because
On 11/13/19 10:30 PM, Peter Maydell wrote:
> Coverity may also be looking at the case where
> TARGET_AARCH64 is not defined. The fallback definition
> of arm_cpu_vq_map_next_smaller() for that situation
> always returns 0.
Yeah, that makes more sense.
I think we can make the fallback
When a monitor's queue is filled up in handle_qmp_command()
it gets suspended. It's the dispatcher bh's job currently to
resume the monitor, which it does after processing an event
from the queue. However, it is possible for a
CHR_EVENT_CLOSED event to be processed before before the bh
is
On Mon, 11 Nov 2019 09:40:45 +0800
Xiang Zheng wrote:
> From: Dongjiu Geng
>
> This patch implements APEI GHES Table generation via fw_cfg blobs. Now
> it only supports ARMv8 SEA, a type of GHESv2 error source. Afterwards,
> we can extend the supported types if needed. For the CPER section,
>
On 15/11/2019 12:32, Max Reitz wrote:
> On 14.11.19 12:59, Vladimir Sementsov-Ogievskiy wrote:
>> 14.11.2019 14:27, Max Reitz wrote:
>>> On 13.11.19 19:43, Andrey Shinkevich wrote:
Allow writing all the data compressed through the filter driver.
The written data will be aligned by the
I totally agree with everything you said! That would allow accessible use of
remote virtual machines, which I initially thought of as rather unnecessary but
it definitely is not. I just did not dare to even think of the new
possibilities it would offer!
Brlapi already has a file descriptor.
On Wed, Nov 13, 2019 at 05:45:57PM +0100, Markus Armbruster wrote:
> Wolfgang Bumiller writes:
>
> > When a monitor's queue is filled up in handle_qmp_command()
> > it gets suspended. It's the dispatcher bh's job currently to
> > resume the monitor, which it does after processing an event
> >
On Wed, Nov 13, 2019 at 05:00:40PM +0100, Greg Kurz wrote:
> On Wed, 13 Nov 2019 15:31:58 +
> Peter Maydell wrote:
>
> > On Wed, 13 Nov 2019 at 15:10, Greg Kurz wrote:
> > > David is away until the 19th of November, which is the release date
> > > of rc2 according to the planning [*]. Then
On 14.11.19 12:59, Vladimir Sementsov-Ogievskiy wrote:
> 14.11.2019 14:27, Max Reitz wrote:
>> On 13.11.19 19:43, Andrey Shinkevich wrote:
>>> Allow writing all the data compressed through the filter driver.
>>> The written data will be aligned by the cluster size.
>>> Based on the QEMU current
On Mon, 11 Nov 2019 09:40:44 +0800
Xiang Zheng wrote:
> From: Dongjiu Geng
>
> Add APEI/GHES detailed design document
>
> Signed-off-by: Dongjiu Geng
> Signed-off-by: Xiang Zheng
> Reviewed-by: Michael S. Tsirkin
> ---
> docs/specs/acpi_hest_ghes.rst | 95
On 14.11.19 18:39, janine.schnei...@fau.de wrote:
> Hello,
>
> thank you for the quick feedback. I am sorry that I expressed myself so
> unclearly. I don't want to use qemu but want to know how qemu converts vmdk
> to raw. So how exactly is the conversion programmed? How are the sparse
> grains
Add new version of Snowridge, Denverton, Opteron_G3, EPYC, and Dhyana
CPU model to remove MONITOR/MWAIT feature.
After QEMU/KVM use "-overcommit cpu-pm=on" to expose MONITOR/MWAIT
(commit id 6f131f13e68d648a8e4f083c667ab1acd88ce4cd), the MONITOR/MWAIT
feature in these CPU model is unused.
In ACPI 6.3 chapter 5.2.27 Heterogeneous Memory Attribute Table (HMAT),
The initiator represents processor which access to memory. And in 5.2.27.3
Memory Proximity Domain Attributes Structure, the attached initiator is
defined as where the memory controller responsible for a memory proximity
Check configuring HMAT usecase
Suggested-by: Igor Mammedov
Signed-off-by: Tao Xu
---
New patch in v16.
---
tests/numa-test.c | 51 +++
1 file changed, 51 insertions(+)
diff --git a/tests/numa-test.c b/tests/numa-test.c
index 8de8581231..15889c26c0
On Fri, Nov 15, 2019 at 03:50:49PM +0100, Thomas Huth wrote:
> When CONFIG_IDE_ISA is disabled, compilation currently fails:
>
> hw/i386/pc_piix.c: In function ‘pc_init1’:
> hw/i386/pc_piix.c:81:9: error: unused variable ‘i’ [-Werror=unused-variable]
>
> Move the variable declaration to the
On Fri, Nov 15, 2019 at 08:41:45PM +0530, Sai Pavan Boddu wrote:
> A few configuration register writes need not update the spi bus state, so just
> return after the register write.
>
> Signed-off-by: Sai Pavan Boddu
> Reviewed-by: Alistair Francis
> Reviewed-by: Francisco Iglesias
> Tested-by:
The homer object has both a pointer and a "chip" property pointing to the
chip object. Confusing bugs could arise if these ever go out of sync.
Change the property definition so that it explicitely sets the pointer.
Signed-off-by: Greg Kurz
---
hw/ppc/pnv.c |8
On 15/11/19 16:54, Thomas Huth wrote:
> On 15/11/2019 16.54, Peter Maydell wrote:
>> On Fri, 15 Nov 2019 at 15:10, Thomas Huth wrote:
>>>
>>> When CONFIG_IDE_ISA is disabled, compilation currently fails:
>>>
>>> hw/i386/pc_piix.c: In function ‘pc_init1’:
>>> hw/i386/pc_piix.c:81:9: error:
On 15/11/2019 17.15, Peter Maydell wrote:
> On Fri, 15 Nov 2019 at 16:08, Thomas Huth wrote:
>>
>> On 15/11/2019 16.54, Peter Maydell wrote:
>>> On Fri, 15 Nov 2019 at 15:10, Thomas Huth wrote:
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -78,7 +78,6 @@ static void
pnv_xive_vst_size() tries to compute the size of a VSD table from the
information given by FW. The number of entries of the table are
deduced from the result and the MMIO regions of the ESBs and the END
ESBs are then resized accordingly with the computed value. This
reduces the number of elements
Hello,
The QEMU PowerNV machine emulates a baremetal OpenPOWER system and
acts as an hypervisor (L0). Supporting emulation of KVM to run guests
(L1) requires a few more extensions, among which guest support for the
XIVE interrupt controller on POWER9 processor.
The following changes extend the
It is now unused.
Signed-off-by: Cédric Le Goater
---
include/hw/ppc/xive.h | 2 --
hw/intc/pnv_xive.c| 13 -
hw/intc/spapr_xive.c | 8
hw/intc/xive.c| 7 ---
4 files changed, 30 deletions(-)
diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h
When the XIVE IVRE sub-engine (XiveRouter) looks for a Notification
Virtual Target (NVT) to notify, it broadcasts a message on the
PowerBUS to find an XIVE IVPE sub-engine (Presenter) with the NVT
dispatched on one of its HW threads, and then forwards the
notification if any response was received.
We will use it to resend missed interrupts when a vCPU context is
pushed on a HW thread.
Signed-off-by: Cédric Le Goater
---
include/hw/ppc/xive.h | 1 +
hw/intc/xive.c| 21 +++--
2 files changed, 12 insertions(+), 10 deletions(-)
diff --git a/include/hw/ppc/xive.h
The XiveFabric QOM interface acts as the PowerBUS interface between
the interrupt controller and the system and should be implemented by
the QEMU machine. On HW, the XIVE sub-engine is responsible for the
communication with the other chip is the Common Queue (CQ) bridge
unit.
This interface
This is described as optional but I'm not convinced of the numbering
when multiple target fragments are sent.
Signed-off-by: Alex Bennée
---
target/arm/cpu.h | 2 +-
target/arm/gdbstub.c | 16 ++--
target/arm/helper.c | 2 +-
3 files changed, 12 insertions(+), 8 deletions(-)
Signed-off-by: Alex Bennée
---
target/arm/cpu.h | 10 -
target/arm/gdbstub.c | 99
target/arm/helper.c | 69 --
3 files changed, 173 insertions(+), 5 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
Rather than having a static buffer replace str_buf with a GString
which we know can grow on demand. Convert the internal functions to
take a GString instead of a char * and length.
Signed-off-by: Alex Bennée
---
gdbstub.c | 194 --
1 file
On 15/11/2019 10:20, David Gibson wrote:
> On Wed, Nov 13, 2019 at 05:00:40PM +0100, Greg Kurz wrote:
>> On Wed, 13 Nov 2019 15:31:58 +
>> Peter Maydell wrote:
>>
>>> On Wed, 13 Nov 2019 at 15:10, Greg Kurz wrote:
David is away until the 19th of November, which is the release date
On Thu, Nov 14, 2019 at 08:25:31PM +0300, Alexander Popov wrote:
The commit a718978ed58a from July 2015 introduced the assertion which
implies that the size of successful DMA transfers handled in ide_dma_cb()
should be multiple of 512 (the size of a sector). But guest systems can
initiate DMA
On 13/11/19 19:54, Sunil Muthuswamy wrote:
> This refactors the load library of WHV libraries to make it more
> modular. It makes a helper routine that can be called on demand.
> This allows future expansion of load library/functions to support
> functionality that is dependent on some feature
On Fri, Nov 15, 2019 at 01:08:53PM +0100, Thomas Huth wrote:
> On 08/11/2019 10.22, Kashyap Chamarthy wrote:
> > This blog post summarizes the talk "Micro-Optimizing KVM VM-Exits"[1],
> > given by Andrea Arcangeli at the recently concluded KVM Forum 2019.
> >
>
> Hi Kashyap,
>
> first thanks
Add ioctls for all RTC features that are currently supported in linux kernel.
This series covers following 22 iocts:
* RTC_AIE_ON
* RTC_AIE_OFF
* RTC_UIE_ON
* RTC_UIE_OFF
* RTC_PIE_ON
* RTC_PIE_OFF
* RTC_WIE_ON
* RTC_WIE_OFF
* RTC_ALM_SET
* RTC_ALM_READ
RTC_VL_READ - Read voltage low detection information
Read the voltage low for RTCs that support voltage low.
The third ioctl's' argument points to an int in which
the voltage low is returned.
RTC_VL_CLR - Clear voltage low information
Clear the information about voltage low for
This patch implements functionalities of following ioctls:
RTC_IRQP_READ, RTC_IRQP_SET - Read/Set IRQ rate
Read and set the frequency for periodic interrupts, for RTCs
that support periodic interrupts. The periodic interrupt must
be separately enabled or disabled using the
This patch implements functionalities of following ioctls:
RTC_RD_TIME - Read RTC time
Returns this RTC's time in the following structure:
struct rtc_time {
int tm_sec;
int tm_min;
int tm_hour;
int tm_mday;
int tm_mon;
On Fri, 15 Nov 2019 at 04:41, Palmer Dabbelt wrote:
>
> The following changes since commit aa464db69b40b4b695be31085e6d2f1e90956c89:
>
> Update version for v4.2.0-rc1 release (2019-11-12 18:40:02 +)
>
> are available in the Git repository at:
>
> g...@github.com:palmer-dabbelt/qemu.git
Split block_copy_find_inflight_req to be used in seprate.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
block/block-copy.c | 31 +++
1 file changed, 19 insertions(+), 12 deletions(-)
diff --git a/block/block-copy.c b/block/block-copy.c
index 74295d93d5..94e7e855ef
We are going to use aio-task-pool API and extend in-flight request
structure to be a successor of AioTask, so rename things appropriately.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
block/block-copy.c | 82 ++
1 file changed, 40 insertions(+), 42
Hide structure definitions and add explicit API instead, to keep an
eye on the scope of the shared fields.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
include/block/block-copy.h | 57 +++--
block/backup-top.c | 6 ++--
block/backup.c | 27
We'll need async block-copy invocation to use in backup directly.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
include/block/block-copy.h | 13 +++
block/block-copy.c | 48 +++---
2 files changed, 58 insertions(+), 3 deletions(-)
diff --git
We are going to directly use one async block-copy operation for backup
job, so we need rate limitator.
We want to maintain current backup behavior: only background copying is
limited and copy-before-write operations only participate in limit
calculation. Therefore we need one rate limitator for
On Fri, Nov 15, 2019 at 6:03 AM Peter Maydell
wrote:
> Richard, I think we're tripping over the check you added
> in commit af2882289951e. Specifically:
>
> +/* We UNDEF for these UNPREDICTABLE cases. */
> +if (a->rd == 15 || a->rn == 15 || a->rt == 15
> +|| a->rd == a->rn ||
On Fri, Nov 15, 2019 at 6:03 AM Peter Maydell
wrote:
> On Fri, 15 Nov 2019 at 05:03, Michael Goffioul
> wrote:
> > When running QEMU user mode on some code compiled by clang (dynamic
> linker from AOSP-10), the emulator chokes on this instruction:
> >
> >9aa92: e8c0 2277 strexd
From: "Edgar E. Iglesias"
Add the CRP as unimplemented thus avoiding bus errors when
guests access these registers.
Signed-off-by: Edgar E. Iglesias
---
hw/arm/xlnx-versal.c | 2 ++
include/hw/arm/xlnx-versal.h | 3 +++
2 files changed, 5 insertions(+)
diff --git
The OCC object has both a pointer and a "psi" property pointing to the
PSI object. Confusing bugs could arise if these ever go out of sync.
Change the property definition so that it explicitely sets the pointer.
Signed-off-by: Greg Kurz
---
hw/ppc/pnv.c |8
hw/ppc/pnv_occ.c |
The XIVE object has both a pointer and a "chip" property pointing to the
chip object. Confusing bugs could arise if these ever go out of sync.
Change the property definition so that it explicitely sets the pointer.
Signed-off-by: Greg Kurz
---
hw/intc/pnv_xive.c | 13 +++--
Fix the alignment of the items in the "Limitations" section.
Signed-off-by: Sergio Lopez
---
docs/microvm.rst | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/docs/microvm.rst b/docs/microvm.rst
index aae811a922..4cf84746b9 100644
--- a/docs/microvm.rst
+++
hw/vfio/display.c needs the EDID subsystem, select it.
Cc: Alex Williamson
Signed-off-by: Paolo Bonzini
---
hw/vfio/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/vfio/Kconfig b/hw/vfio/Kconfig
index 34da2a3cfd..f0eaa75ce7 100644
--- a/hw/vfio/Kconfig
+++ b/hw/vfio/Kconfig
@@
Oops 'for-5.0' tag is missing :)
On Fri, 15 Nov 2019 17:03:51 +0100
Greg Kurz wrote:
> It has no apparent user.
>
> Signed-off-by: Greg Kurz
> ---
> hw/ppc/pnv.c |2 --
> 1 file changed, 2 deletions(-)
>
> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
> index d7130c3304f0..24bc3d5ab32b
Each vCPU in the system is identified with an NVT identifier which is
pushed in the OS CAM line (QW1W2) of the HW thread interrupt context
register when the vCPU is dispatched on a HW thread. This identifier
is used by the presenter subengine to find a matching target to notify
of an event. It is
This is useful to dump the saved contexts of the vCPUs : configuration
of the base END index of the vCPU and the Interrupt Pending Buffer
register, which is updated when an interrupt can not be presented.
When dumping the NVT table, we skip empty indirect pages which are not
necessarily
On Fri, Nov 15, 2019 at 02:09:25PM +0800, Micky Yun Chan wrote:
Thanks for the patch!
> +context = g_option_context_new(NULL);
Missing g_option_context_free() later in this function. g_auto() is the
easiest way to ensure that.
> +g_option_context_add_main_entries(context, entries,
On the P9 Processor, the thread interrupt context registers of a CPU
can be accessed "directly" when by load/store from the CPU or
"indirectly" by the IC through an indirect TIMA page. This requires to
configure first the PC_TCTXT_INDIRx registers.
Today, we rely on the get_tctx() handler to
On Fri, Nov 15, 2019 at 10:50 AM Edgar E. Iglesias
wrote:
>
> From: "Edgar E. Iglesias"
>
> Add the CRP as unimplemented thus avoiding bus errors when
> guests access these registers.
>
> Signed-off-by: Edgar E. Iglesias
Reviewed-by: Alistair Francis
Alistair
> ---
> hw/arm/xlnx-versal.c
14.11.2019 5:46, Eric Blake wrote:
> Qemu as server currently won't accept export names larger than 256
> bytes, nor create dirty bitmap names longer than 1023 bytes, so most
> uses of qemu as client or server have no reason to get anywhere near
> the NBD spec maximum of a 4k limit per string.
>
On commit abf0bf998dcb John Snow moved some code out of __init__.py
to machine.py. kvm_available() remained in though. So on patch 01
I continue his work by creating a home for that method (the new
'accel' module). Honestly I was unsure about whether move the code
to any existing module or make a
Public bug reported:
Running qemu-system-s390x (1:4.0+dfsg-0ubuntu10) on an x86-64 Focal host
with an upgrade of a Eoan s390x VM to a Focal s390x is triggering random
breakage, for example:
sudo apt-get update && sudo apt-get dist-upgrade
...
...
Unpacking debianutils (4.9) over (4.8.6.3) ...
From: "Edgar E. Iglesias"
Some boot-loaders will access the CRP block and bug out
if recieving bus errors. Since we're in freeze, this does
not try to add a model of the CRP instead we only add it
as unimplemented. This is enough to work around the issue.
Cheers,
Edgar
Edgar E. Iglesias (1):
15.11.2019 18:03, Vladimir Sementsov-Ogievskiy wrote:
> 14.11.2019 5:46, Eric Blake wrote:
>> We document that for qcow2 persistent bitmaps, the name cannot exceed
>> 1023 bytes. It is inconsistent if transient bitmaps do not have to
>> abide by the same limit, and it is unlikely that any
On Fri, 15 Nov 2019 at 16:08, Thomas Huth wrote:
>
> On 15/11/2019 16.54, Peter Maydell wrote:
> > On Fri, 15 Nov 2019 at 15:10, Thomas Huth wrote:
> >> --- a/hw/i386/pc_piix.c
> >> +++ b/hw/i386/pc_piix.c
> >> @@ -78,7 +78,6 @@ static void pc_init1(MachineState *machine,
> >>
The CAM line matching on the PowerNV machine now scans all chips of
the system and all CPUs of a chip to find a dispatched NVT in the
thread contexts.
Signed-off-by: Cédric Le Goater
---
hw/ppc/pnv.c | 35 +++
1 file changed, 35 insertions(+)
diff --git
Now that the machines have handlers implementing the XiveFabric and
XivePresenter interfaces, remove xive_presenter_match() and make use
of the 'match_nvt' handler of the machine.
Signed-off-by: Cédric Le Goater
---
hw/intc/xive.c | 48 +---
1 file
Hi,
This RFC is for supporting SVE registers in QEMU's gdbstub.
However on the way to that there is a bunch of re-factoring to the
core gdbstub code to remove some of the hardcoded size limits from its
various buffers. By using dynamically sized buffers we are less likely
to trip up as we
We use g_new0() as it is the preferred form for such allocations. We
can also ensure that gdbserver_state is reset in one place.
Signed-off-by: Alex Bennée
---
gdbstub.c | 14 +-
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/gdbstub.c b/gdbstub.c
index
This is cleaner than poking memory directly and will make later
clean-ups easier.
Signed-off-by: Alex Bennée
---
target/arm/helper.c | 16 ++--
1 file changed, 6 insertions(+), 10 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index be67e2c66d6..bd821931b3d
On 11/15/19 5:06 PM, Andrew Jones wrote:
>> bitnum = find_last_bit(cpu->sve_vq_map, vq - 1);
>> -return bitnum == vq - 1 ? 0 : bitnum + 1;
>> +
>> +/* We always have vq == 1 present in sve_vq_map. */
>
> This is true with TCG and 99.% likely to be true with KVM...
Eh? It's
I've also seen in the dmesg log:
[ 287.624414] User process fault: interruption code 0007 ilc:3 in
libstdc++.so.6.0.28[3ffb3e0+21d000]
[ 288.991706] User process fault: interruption code 0007 ilc:3 in
libstdc++.so.6.0.28[3ff9008+21d000]
--
You received this bug notification because
The source object has both a pointer and a "xive" property pointing to the
notifier object. Confusing bugs could arise if these ever go out of sync.
Change the property definition so that it explicitely sets the pointer.
The property isn't optional : not being able to set the link is a bug
and
The TCTX object has both a pointer and a "cpu" property pointing to the
vCPU object. Confusing bugs could arise if these ever go out of sync.
Change the property definition so that it explicitely sets the pointer.
Signed-off-by: Greg Kurz
---
hw/intc/xive.c | 22 +-
1
There's a recurring pattern in the code where a const link is added to a
newly instanciated object and the link is then used in the object's realize
function to keep a pointer to the QOM entity which the link points to.
void create_obj_b(Object *obj_a)
{
Object *obj_b;
obj_b =
It has no apparent user.
Signed-off-by: Greg Kurz
---
hw/ppc/pnv.c |2 --
1 file changed, 2 deletions(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index d7130c3304f0..24bc3d5ab32b 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -1091,8 +1091,6 @@ static void
Each XIVE Router model, sPAPR and PowerNV, now implements the 'match_nvt'
handler of the XivePresenter QOM interface. This is simply moving code
and taking into account the new API.
To be noted that the xive_router_get_tctx() helper is not used anymore
when doing CAM matching and will be removed
When PC_TCTXT_CHIPID_OVERRIDE is configured, the PC_TCTXT_CHIPID field
overrides the hardwired chip ID in the Powerbus operations and for CAM
compares. This is typically used in the one block-per-chip configuration
to associate a unique block id number to each IC of the system.
Simplify the model
The CAM line matching sequence in the pseries machine does not change
much apart from the use of the new QOM interfaces. There is an extra
indirection because of the sPAPR IRQ backend of the machine. Only the
XIVE backend implements the new 'match_nvt' handler.
Signed-off-by: Cédric Le Goater
When a vCPU is dispatched on a HW thread, its context is pushed in the
thread registers and it is activated by setting the VO bit in the CAM
line word2. The HW grabs the associated NVT, pulls the IPB bits and
merges them with the IPB of the new context. If interrupts were missed
while the vCPU was
On 15/11/2019 17.24, Kashyap Chamarthy wrote:
> This blog post summarizes the talk "Micro-Optimizing KVM VM-Exits"[1],
> given by Andrea Arcangeli at the recently concluded KVM Forum 2019.
Thanks, pushed now:
https://www.qemu.org/2019/11/15/micro-optimizing-kvm-vmexits/
Thomas
This is cleaner than poking memory directly and will make later
clean-ups easier.
Signed-off-by: Alex Bennée
---
target/m68k/helper.c | 29 +++--
1 file changed, 11 insertions(+), 18 deletions(-)
diff --git a/target/m68k/helper.c b/target/m68k/helper.c
index
We will want to generate similar dynamic XML for gdbstub support of
SVE registers (the upstream doesn't use XML). To that end lightly
rename a few things to make the distinction.
Signed-off-by: Alex Bennée
---
target/arm/cpu.h | 20 +---
target/arm/gdbstub.c | 30
This is in preparation for further re-factoring of the register API
with the rest of the code. Theoretically the read register function
could overwrite the MAX_PACKET_LENGTH buffer although currently all
registers are well within the size range.
Signed-off-by: Alex Bennée
---
gdbstub.c | 52
Patchew URL:
https://patchew.org/QEMU/20191115141444.24155-1-vsement...@virtuozzo.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [RFC 00/24] backup performance: block_status + async
Type: series
Message-id:
On 11/15/19 8:14 AM, Vladimir Sementsov-Ogievskiy wrote:
This brings async request handling and block-status driven chunk sizes
to backup out of the box, which improves backup performance.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
+++ b/qapi/block-core.json
@@ -1455,6 +1455,12 @@
#
Currently kvm_available() checks for the presence of kvm module
and, if target and host arches don't mismatch. This patch adds
an 3rd checking: if QEMU binary was compiled with kvm
support.
Signed-off-by: Wainer dos Santos Moschetta
---
python/qemu/accel.py | 27 +--
1
Since commit cbe6d6365a48 the command `qemu -accel help` returns
the list of accelerators enabled in the QEMU binary. This adds
the list_accel() method which return that same list.
Signed-off-by: Wainer dos Santos Moschetta
---
python/qemu/accel.py | 20
1 file changed, 20
This creates the 'accel' Python module to be the home for
utilities that deal with accelerators. Also moved kvm_available()
from __init__.py to this new module.
Signed-off-by: Wainer dos Santos Moschetta
---
python/qemu/__init__.py | 20 +---
python/qemu/accel.py| 36
ps is showing QEMU is running as follows:
/usr/bin/qemu-system-s390x -name guest=ubuntu20.04-focal-s390x,debug-
threads=on -S -object
secret,id=masterKey0,format=raw,file=/var/lib/libvirt/qemu/domain-10-ubuntu20.04-focal-s3
/master-key.aes -machine s390-ccw-virtio-eoan,accel=tcg,usb=off,dump-
On Fri, Nov 15, 2019 at 01:45:51PM +0100, Laszlo Ersek wrote:
> On 11/08/19 10:22, Kashyap Chamarthy wrote:
[...]
> > +Guest workloads that are hard to virtualize
> > +---
> > +
> > +At the 2019 edition of the KVM Forum in Lyon, kernel developer, Andrea
>
On Fri, 15 Nov 2019 at 15:10, Thomas Huth wrote:
>
> When CONFIG_IDE_ISA is disabled, compilation currently fails:
>
> hw/i386/pc_piix.c: In function ‘pc_init1’:
> hw/i386/pc_piix.c:81:9: error: unused variable ‘i’ [-Werror=unused-variable]
>
> Move the variable declaration to the right code
Fix the alignment in the "Limitations" section and include an
explanation about the particularities of the microvm machine type when
it comes to triggering a guest initiated shut down.
Sergio Lopez (2):
docs/microvm.rst: fix alignment in "Limitations"
docs/microvm.rst: add instructions for
Add a new section explaining the particularities of the microvm
machine type for triggering a guest-initiated shut down.
Signed-off-by: Sergio Lopez
---
docs/microvm.rst | 21 +
1 file changed, 21 insertions(+)
diff --git a/docs/microvm.rst b/docs/microvm.rst
index
This blog post summarizes the talk "Micro-Optimizing KVM VM-Exits"[1],
given by Andrea Arcangeli at the recently concluded KVM Forum 2019.
[1]
https://kvmforum2019.sched.com/event/Tmwr/micro-optimizing-kvm-vm-exits-andrea-arcangeli-red-hat-inc
Signed-off-by: Kashyap Chamarthy
---
v3:
-
The OS CAM line has a special encoding exploited by the HW. Provide
helper routines to hide the details to the TIMA command handlers. This
also clarifies the endianness of different variables : 'qw1w2' is
big-endian and 'cam' is native.
Signed-off-by: Cédric Le Goater
---
hw/intc/xive.c | 41
When an interrupt can not be presented to a vCPU, because it is not
running on any of the HW treads, the XIVE presenter updates the
Interrupt Pending Buffer register of the associated XIVE NVT
structure. This is only done if backlog is activated in the END but
this is generally the case.
The
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