Re: [PATCH v2 9/9] pc-bios: s390x: Make u32 ptr check explicit

2020-05-21 Thread Thomas Huth
On 14/05/2020 14.37, Janosch Frank wrote: > Let's make it a bit more clear that we check the full 64 bits to fit > into the 32 we return. > > Signed-off-by: Janosch Frank > Suggested-by: David Hildenbrand > Reviewed-by: David Hildenbrand > --- > pc-bios/s390-ccw/helper.h | 2 +- > 1 file

Re: [PATCH Kernel v22 0/8] Add UAPIs to support migration for VFIO devices

2020-05-21 Thread Kirti Wankhede
On 5/21/2020 12:34 PM, Yan Zhao wrote: On Thu, May 21, 2020 at 12:39:48PM +0530, Kirti Wankhede wrote: On 5/21/2020 10:38 AM, Yan Zhao wrote: On Wed, May 20, 2020 at 10:46:12AM -0600, Alex Williamson wrote: On Wed, 20 May 2020 19:10:07 +0530 Kirti Wankhede wrote: On 5/20/2020 8:25 AM,

[PATCH] target-i386: do not force-expose WAITPKG if -overcommit cpu-pm=on

2020-05-21 Thread Paolo Bonzini
By force-enabling the WAITPKG bit whenever -overcommit cpu-pm=on is used, commit 67192a298f ("x86/cpu: Add support for UMONITOR/UMWAIT/TPAUSE", 2019-10-23) broke that option is the host processor does not have WAITPKG or the host kernel is too old. This is because TPAUSE, UMWAIT and UMONITOR are

[PATCH 6/9] hw/arm/smmu-common: Manage IOTLB block entries

2020-05-21 Thread Eric Auger
At the moment each entry in the IOTLB corresponds to a page sized mapping (4K, 16K or 64K), even if the page belongs to a mapped block. In case of block mapping this unefficiently consume IOTLB entries. Change the value of the entry so that it reflects the actual mapping it belongs to (block or

[PATCH 0/9] SMMUv3.2 Range-based TLB Invalidation Support

2020-05-21 Thread Eric Auger
SMMU3.2 brings the support of range-based TLB invalidation and level hint. When this feature is supported, the SMMUv3 driver is allowed to send TLB invalidations for a range of IOVAs instead of using page based invalidation. Implementing this feature in the virtual SMMUv3 device is mandated for

Re: [PATCH Kernel v22 0/8] Add UAPIs to support migration for VFIO devices

2020-05-21 Thread Kirti Wankhede
On 5/21/2020 12:34 PM, Yan Zhao wrote: On Thu, May 21, 2020 at 12:39:48PM +0530, Kirti Wankhede wrote: On 5/21/2020 10:38 AM, Yan Zhao wrote: On Wed, May 20, 2020 at 10:46:12AM -0600, Alex Williamson wrote: On Wed, 20 May 2020 19:10:07 +0530 Kirti Wankhede wrote: On 5/20/2020 8:25 AM,

Re: [PATCH V2] Add a new PIIX option to control PCI hot unplugging of devices on non-root buses

2020-05-21 Thread Igor Mammedow
On Wed, 20 May 2020 12:13:35 -0400 "Michael S. Tsirkin" wrote: > On Wed, May 20, 2020 at 02:20:12PM +0200, Igor Mammedow wrote: > > On Wed, 20 May 2020 07:23:21 -0400 > > "Michael S. Tsirkin" wrote: > > > > > On Wed, May 20, 2020 at 01:05:47PM +0200, Igor Mammedow wrote: > > > > On Wed, 20

Re: [PATCH v3 09/22] acpi: ged: rename event memory region

2020-05-21 Thread Igor Mammedow
On Wed, 20 May 2020 15:19:50 +0200 Gerd Hoffmann wrote: > Rename memory region and callbacks and ops to carry "evt" in the name > because a second region will be added shortly. > > Signed-off-by: Gerd Hoffmann Reviewed-by: Igor Mammedow > --- > include/hw/acpi/generic_event_device.h | 2

Re: [PATCH v3 10/22] acpi: ged: add control regs

2020-05-21 Thread Igor Mammedov
On Wed, 20 May 2020 15:19:51 +0200 Gerd Hoffmann wrote: > Add control regs (sleep, reset) for hw-reduced acpi. > > Signed-off-by: Gerd Hoffmann this should be acompanied by docs update docs/specs/acpi_hw_reduced_hotplug.rst to document new registers and their semantics and probaly rename

Re: [PATCH Kernel v22 0/8] Add UAPIs to support migration for VFIO devices

2020-05-21 Thread Kirti Wankhede
On 5/21/2020 10:38 AM, Yan Zhao wrote: On Wed, May 20, 2020 at 10:46:12AM -0600, Alex Williamson wrote: On Wed, 20 May 2020 19:10:07 +0530 Kirti Wankhede wrote: On 5/20/2020 8:25 AM, Yan Zhao wrote: On Tue, May 19, 2020 at 10:58:04AM -0600, Alex Williamson wrote: Hi folks, My

Re: [PATCH] arm/aspeed: Rework NIC attachment

2020-05-21 Thread Cédric Le Goater
On 5/20/20 5:43 PM, Markus Armbruster wrote: > Cédric Le Goater writes: > >> On 5/20/20 8:34 AM, Markus Armbruster wrote: >>> Cédric Le Goater writes: >>> The AST2400 and AST2500 SoCs have two MACs but only the first MAC0 is active on the Aspeed machines using these SoCs. The AST2600

Re: kvm_buf_set_msrs: Assertion `ret == cpu->kvm_msr_buf->nmsrs' failed.

2020-05-21 Thread Li Feng
Paolo, Million thanks. I will try to dig into this code in my spare time. Thanks, Feng Li Paolo Bonzini 于2020年5月20日周三 下午6:27写道: > > On 20/05/20 12:15, Li Feng wrote: > > /root/qemu-master/x86_64-softmmu/qemu-system-x86_64 -enable-kvm > > -device virtio-balloon -cpu > >

[PATCH 4/9] hw/arm/smmu: Introduce SMMUTLBEntry for PTW and IOTLB value

2020-05-21 Thread Eric Auger
Introduce a specialized SMMUTLBEntry to store the result of the PTW and cache in the IOTLB. This structure extends the generic IOMMUTLBEntry struct with the level of the entry and the granule size. Those latter will be useful when implementing range invalidation. Signed-off-by: Eric Auger ---

[PATCH 1/9] hw/arm/smmu-common: Factorize some code in smmu_ptw_64()

2020-05-21 Thread Eric Auger
Page and block PTE decoding can share some code. Let's first handle table PTE and factorize some code shared by page and block PTEs. Signed-off-by: Eric Auger --- hw/arm/smmu-common.c | 51 1 file changed, 18 insertions(+), 33 deletions(-) diff

Re: [PATCH v2 8/9] pc-bios: s390x: Replace 0x00 with 0x0 or 0

2020-05-21 Thread Thomas Huth
On 14/05/2020 14.37, Janosch Frank wrote: > 0x00 looks odd, time to replace it with 0 or 0x0 (for pointers). > > Signed-off-by: Janosch Frank > --- > pc-bios/s390-ccw/dasd-ipl.c | 14 +++--- > 1 file changed, 7 insertions(+), 7 deletions(-) > > diff --git a/pc-bios/s390-ccw/dasd-ipl.c

Re: [PATCH v2 8/8] s390: guest support for diagnose 0x318

2020-05-21 Thread Collin Walling
On 5/20/20 7:30 AM, Cornelia Huck wrote: > On Fri, 15 May 2020 18:20:32 -0400 > Collin Walling wrote: > >> DIAGNOSE 0x318 (diag 318) allows the storage of diagnostic data that >> is collected by the firmware in the case of hardware/firmware service >> events. >> >> The instruction is invoked in

Re: [PATCH v4] target/i386: Add notes for versioned CPU models

2020-05-21 Thread Tao Xu
Hi Eduardo Could you review this patch? Tao Xu On 3/24/2020 1:10 PM, Xu, Tao3 wrote: Add which features are added or removed in this version. Signed-off-by: Tao Xu --- The output is as follows: qemu-system-x86_64 -cpu help | grep "\[" x86 Cascadelake-Server-v2 Intel Xeon Processor

Re: [PATCH Kernel v22 0/8] Add UAPIs to support migration for VFIO devices

2020-05-21 Thread Yan Zhao
On Thu, May 21, 2020 at 12:39:48PM +0530, Kirti Wankhede wrote: > > > On 5/21/2020 10:38 AM, Yan Zhao wrote: > > On Wed, May 20, 2020 at 10:46:12AM -0600, Alex Williamson wrote: > > > On Wed, 20 May 2020 19:10:07 +0530 > > > Kirti Wankhede wrote: > > > > > > > On 5/20/2020 8:25 AM, Yan Zhao

Re: [PATCH v1 04/10] linux-user: completely re-write init_guest_space

2020-05-21 Thread Alex Bennée
Thomas Huth writes: > On 13/05/2020 19.51, Alex Bennée wrote: >> First we ensure all guest space initialisation logic comes through >> probe_guest_base once we understand the nature of the binary we are >> loading. The convoluted init_guest_space routine is removed and >> replaced with a

Re: [PATCH 50/55] s390x/event-facility: Simplify creation of SCLP event devices

2020-05-21 Thread David Hildenbrand
>> +static void realize_event_facility(DeviceState *dev, Error **errp) >> +{ >> +SCLPEventFacility *event_facility = EVENT_FACILITY(dev); >> +Error *local_err = NULL; >> + >> +qdev_realize(DEVICE(_facility->quiesce), >> + BUS(_facility->sbus), _err); >> +if

Re: [PATCH v3 12/22] acpi: move acpi_dsdt_add_power_button() to ged

2020-05-21 Thread Igor Mammedov
On Wed, 20 May 2020 15:19:53 +0200 Gerd Hoffmann wrote: > Allow reuse for microvm. > > Signed-off-by: Gerd Hoffmann Reviewed-by: Igor Mammedov > --- > include/hw/acpi/generic_event_device.h | 1 + > hw/acpi/generic_event_device.c | 8 > hw/arm/virt-acpi-build.c

[PATCH 7/9] hw/arm/smmuv3: Introduce smmuv3_s1_range_inval() helper

2020-05-21 Thread Eric Auger
Let's introduce an helper for S1 IOVA range invalidation. This will be used for NH_VA and NH_VAA commands. It decodes the same fields, trace, calls the UNMAP notifiers and invalidate the corresponding IOTLB entries. At the moment, we do not support 3.2 range invalidation yet. So it reduces to a

[PATCH 5/9] hw/arm/smmuv3: Store the starting level in SMMUTransTableInfo

2020-05-21 Thread Eric Auger
Compute the starting level on CD decoding and store it into SMMUTransTableInfo. We will need this information on IOTLB lookup so let's avoid to recompute it each time. Signed-off-by: Eric Auger --- include/hw/arm/smmu-common.h | 1 + hw/arm/smmu-common.c | 2 +- hw/arm/smmuv3.c

Re: [virtio-dev] Re: Fwd: Qemu Support for Virtio Video V4L2 driver

2020-05-21 Thread Alexandre Courbot
On Thu, May 21, 2020 at 1:21 AM Nicolas Dufresne wrote: > > Le mercredi 20 mai 2020 à 12:19 +0900, Alexandre Courbot a écrit : > > On Wed, May 20, 2020 at 2:29 AM Nicolas Dufresne > > wrote: > > > Le mardi 19 mai 2020 à 17:37 +0900, Keiichi Watanabe a écrit : > > > > Hi Nicolas, > > > > > > > >

Re: [PATCH v3 11/22] acpi: ged: add x86 device variant.

2020-05-21 Thread Igor Mammedov
On Wed, 20 May 2020 15:19:52 +0200 Gerd Hoffmann wrote: > Set AcpiDeviceIfClass->madt_cpu, > otherwise identical to TYPE_ACPI_GED. > > Signed-off-by: Gerd Hoffmann Reviewed-by: Igor Mammedov > --- > include/hw/acpi/generic_event_device.h | 4 +++ > hw/i386/generic_event_device_x86.c |

Re: [PATCH v2 2/2] spapr: Add a new level of NUMA for GPUs

2020-05-21 Thread Greg Kurz
On Thu, 21 May 2020 15:13:45 +1000 David Gibson wrote: > On Thu, May 21, 2020 at 01:36:16AM +0200, Greg Kurz wrote: > > On Mon, 18 May 2020 16:44:18 -0500 > > Reza Arbab wrote: > > > > > NUMA nodes corresponding to GPU memory currently have the same > > > affinity/distance as normal memory

[PATCH 8/9] hw/arm/smmuv3: Get prepared for range invalidation

2020-05-21 Thread Eric Auger
Enhance the smmu_iotlb_inv_iova() helper with range invalidation. This uses the new fields passed in the NH_VA and NH_VAA commands: the size of the range, the level and the granule. As NH_VA and NH_VAA both use those fields, their decoding and handling is factorized in a new

Re: [PATCH v4 5/5] target/i386: remove Icelake-Client CPU model

2020-05-21 Thread Daniel P . Berrangé
On Thu, May 21, 2020 at 09:40:55AM +0800, Robert Hoo wrote: > On Wed, 2020-05-20 at 10:17 +0100, Daniel P. Berrangé wrote: > > On Wed, May 20, 2020 at 10:10:07AM +0800, Chenyi Qiang wrote: > > > There are no Icelake Desktop products in the market. Remove the > > > Icelake-Client CPU model. > > >

[PATCH v8 01/62] target/riscv: add vector extension field in CPURISCVState

2020-05-21 Thread LIU Zhiwei
The 32 vector registers will be viewed as a continuous memory block. It avoids the convension between element index and (regno, offset). Thus elements can be directly accessed by offset from the first vector base address. Signed-off-by: LIU Zhiwei Acked-by: Alistair Francis Reviewed-by: Richard

[PATCH v8 05/62] target/riscv: add an internals.h header

2020-05-21 Thread LIU Zhiwei
The internals.h keeps things that are not relevant to the actual architecture, only to the implementation, separate. Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/internals.h | 24 1 file changed, 24

Re: [PATCH 0/4] Add support for SafeStack

2020-05-21 Thread Stefan Hajnoczi
On Wed, May 13, 2020 at 10:48:04AM -0400, Daniele Buono wrote: > Hello everybody, just pinging since it it's been a few days. Hi Daniele, Sorry I'm late to the party. This looks useful, the patches are not invasive and provide the option of enabling extra security. I have left comments on

[PATCH v8 08/62] target/riscv: add fault-only-first unit stride load

2020-05-21 Thread LIU Zhiwei
The unit-stride fault-only-fault load instructions are used to vectorize loops with data-dependent exit conditions(while loops). These instructions execute as a regular load except that they will only take a trap on element 0. Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by:

Re: [PATCH QEMU v23 05/18] vfio: Add migration region initialization and finalize function

2020-05-21 Thread Dr. David Alan Gilbert
* Kirti Wankhede (kwankh...@nvidia.com) wrote: > - Migration functions are implemented for VFIO_DEVICE_TYPE_PCI device in this > patch series. > - VFIO device supports migration or not is decided based of migration region > query. If migration region query is successful and migration region >

Re: [PATCH 2/2] sd: disable sdhci-pci device by default

2020-05-21 Thread P J P
+-- On Wed, 20 May 2020, Philippe Mathieu-Daudé wrote --+ | Prasad, I once tried to remove it, and Kevin said he was using it: | | https://lists.nongnu.org/archive/html/qemu-devel/2017-12/msg02765.html | | I do find qemu's PCI SDHCI support useful for testing. | SeaBIOS can launch an OS from

[PATCH v8 12/62] target/riscv: vector integer add-with-carry / subtract-with-borrow instructions

2020-05-21 Thread LIU Zhiwei
Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/helper.h | 33 ++ target/riscv/insn32.decode | 11 ++ target/riscv/insn_trans/trans_rvv.inc.c | 113 +++ target/riscv/vector_helper.c

[PATCH v8 16/62] target/riscv: vector integer comparison instructions

2020-05-21 Thread LIU Zhiwei
Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 57 +++ target/riscv/insn32.decode | 20 target/riscv/insn_trans/trans_rvv.inc.c | 46 + target/riscv/vector_helper.c

[PATCH v8 19/62] target/riscv: vector integer divide instructions

2020-05-21 Thread LIU Zhiwei
Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 33 +++ target/riscv/insn32.decode | 8 +++ target/riscv/insn_trans/trans_rvv.inc.c | 10 target/riscv/vector_helper.c| 74

[PATCH v8 23/62] target/riscv: vector integer merge and move instructions

2020-05-21 Thread LIU Zhiwei
Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/helper.h | 17 target/riscv/insn32.decode | 7 ++ target/riscv/insn_trans/trans_rvv.inc.c | 113 target/riscv/vector_helper.c

Re: [PATCH] linux-user: limit check to HOST_LONG_BITS == 32

2020-05-21 Thread Peter Maydell
On Thu, 21 May 2020 at 11:22, Alex Bennée wrote: > > Newer clangs rightly spot that you can never exceed the full address > space of 64 bit hosts with: > > linux-user/elfload.c:2076:41: error: result of comparison 'unsigned > long' > 18446744073709551615 is always false >

[PATCH v8 27/62] target/riscv: vector widening saturating scaled multiply-add

2020-05-21 Thread LIU Zhiwei
Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 22 +++ target/riscv/insn32.decode | 7 + target/riscv/insn_trans/trans_rvv.inc.c | 9 ++ target/riscv/vector_helper.c| 205

[PATCH v8 34/62] target/riscv: vector widening floating-point multiply

2020-05-21 Thread LIU Zhiwei
Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 5 + target/riscv/insn32.decode | 2 ++ target/riscv/insn_trans/trans_rvv.inc.c | 4 target/riscv/vector_helper.c| 22

[PATCH v8 39/62] target/riscv: vector floating-point sign-injection instructions

2020-05-21 Thread LIU Zhiwei
Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 19 ++ target/riscv/insn32.decode | 6 ++ target/riscv/insn_trans/trans_rvv.inc.c | 8 +++ target/riscv/vector_helper.c| 85

[PATCH v8 42/62] target/riscv: vector floating-point merge instructions

2020-05-21 Thread LIU Zhiwei
Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 4 +++ target/riscv/insn32.decode | 2 ++ target/riscv/insn_trans/trans_rvv.inc.c | 38 + target/riscv/vector_helper.c| 24 4 files changed, 68

[PATCH v8 41/62] target/riscv: vector floating-point classify instructions

2020-05-21 Thread LIU Zhiwei
Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/fpu_helper.c | 33 + target/riscv/helper.h | 4 ++ target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvv.inc.c | 3 + target/riscv/internals.h

Re: [PATCH v3 5/5] iotests: add commit top->base cases to 274

2020-05-21 Thread Vladimir Sementsov-Ogievskiy
20.05.2020 19:39, Eric Blake wrote: On 5/20/20 3:35 AM, Vladimir Sementsov-Ogievskiy wrote: These cases are fixed by previous patches around block_status and is_allocated. Signed-off-by: Vladimir Sementsov-Ogievskiy ---   tests/qemu-iotests/274 | 20  

[PATCH v8 43/62] target/riscv: vector floating-point/integer type-convert instructions

2020-05-21 Thread LIU Zhiwei
Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/helper.h | 13 ++ target/riscv/insn32.decode | 4 +++ target/riscv/insn_trans/trans_rvv.inc.c | 6 + target/riscv/vector_helper.c| 33 + 4

Re: [PATCH v3 2/3] crypto/linux_keyring: add 'secret_keyring' secret object.

2020-05-21 Thread Daniel P . Berrangé
On Mon, May 18, 2020 at 11:28:03PM +0300, Alexey Krasikov wrote: > Add the ability for the secret object to obtain secret data from the > Linux in-kernel key managment and retention facility, as an extra option > to the existing ones: reading from a file or passing directly as a > string. > > The

[PATCH v8 46/62] target/riscv: vector single-width integer reduction instructions

2020-05-21 Thread LIU Zhiwei
Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/helper.h | 33 +++ target/riscv/insn32.decode | 8 +++ target/riscv/insn_trans/trans_rvv.inc.c | 18 ++ target/riscv/vector_helper.c| 74 + 4

[PATCH v8 50/62] target/riscv: vector mask-register logical instructions

2020-05-21 Thread LIU Zhiwei
Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/helper.h | 9 ++ target/riscv/insn32.decode | 8 + target/riscv/insn_trans/trans_rvv.inc.c | 35 ++ target/riscv/vector_helper.c| 40

Re: [PATCH 0/2] Update use_goto_tb() in hppa and rx targets

2020-05-21 Thread Ahmed Karaman
On Tue, May 19, 2020 at 8:01 PM Richard Henderson wrote: > > On 5/19/20 9:21 AM, Ahmed Karaman wrote: > > The issue arose because the page crossings check in use_goto_tb() > > function is required only in the system mode. Checking it in both > > modes causes an unnecessary overhead in the user

Re: [PATCH v5 1/5] iotests: Fix test 178

2020-05-21 Thread Vladimir Sementsov-Ogievskiy
21.05.2020 01:01, Eric Blake wrote: A recent change to qemu-img changed expected error message output, but 178 takes long enough to execute that it does not get run by 'make check' or './check -g quick'. Fixes: 43d589b074 Signed-off-by: Eric Blake Reviewed-by: Vladimir Sementsov-Ogievskiy

[PATCH v8 57/62] target/riscv: integer scalar move instruction

2020-05-21 Thread LIU Zhiwei
Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvv.inc.c | 60 + target/riscv/internals.h| 6 +++ 3 files changed, 67 insertions(+) diff --git

[PATCH v8 59/62] target/riscv: vector slide instructions

2020-05-21 Thread LIU Zhiwei
Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/helper.h | 17 target/riscv/insn32.decode | 7 ++ target/riscv/insn_trans/trans_rvv.inc.c | 18 target/riscv/vector_helper.c| 114 4 files

Re: [PATCH 2/2] xen/9pfs: yield when there isn't enough room on the ring

2020-05-21 Thread Christian Schoenebeck
On Mittwoch, 20. Mai 2020 19:35:00 CEST Stefano Stabellini wrote: > On Wed, 20 May 2020, Christian Schoenebeck wrote: > > On Mittwoch, 20. Mai 2020 03:47:12 CEST Stefano Stabellini wrote: > > > From: Stefano Stabellini > > > > > > Instead of truncating replies, which is problematic, wait until

[PATCH v8 01/62] target/riscv: add vector extension field in CPURISCVState

2020-05-21 Thread LIU Zhiwei
The 32 vector registers will be viewed as a continuous memory block. It avoids the convension between element index and (regno, offset). Thus elements can be directly accessed by offset from the first vector base address. Signed-off-by: LIU Zhiwei Acked-by: Alistair Francis Reviewed-by: Richard

Re: [PATCH v3 14/22] microvm: use 2G split unconditionally

2020-05-21 Thread Igor Mammedov
On Wed, 20 May 2020 15:19:55 +0200 Gerd Hoffmann wrote: > Looks like the logiv was copied over from q35. > > q35 does this for backward compatibility, there is no reason to do this > on microvm though. So split @ 2G unconditionally. not related to your ACPI rework, but just an idea for future

Re: [PATCH 1/4] coroutine: support SafeStack in ucontext backend

2020-05-21 Thread Stefan Hajnoczi
On Wed, Apr 29, 2020 at 03:44:17PM -0400, Daniele Buono wrote: > diff --git a/include/qemu/coroutine_int.h b/include/qemu/coroutine_int.h > index bd6b0468e1..2ffd75ddbe 100644 > --- a/include/qemu/coroutine_int.h > +++ b/include/qemu/coroutine_int.h > @@ -28,6 +28,12 @@ > #include "qemu/queue.h"

[PATCH v8 00/62] target/riscv: support vector extension v0.7.1

2020-05-21 Thread LIU Zhiwei
This patchset implements the vector extension for RISC-V on QEMU. You can also find the patchset and all *test cases* in my repo(https://github.com/romanheros/qemu.git branch:vector-upstream-v8). All the test cases are in the directory qemu/tests/riscv/vector/. They are riscv64 linux user mode

[PATCH v8 04/62] target/riscv: add vector configure instruction

2020-05-21 Thread LIU Zhiwei
vsetvl and vsetvli are two configure instructions for vl, vtype. TB flags should update after configure instructions. The (ill, lmul, sew ) of vtype and the bit of (VSTART == 0 && VL == VLMAX) will be placed within tb_flags. Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by:

Re: [PATCH QEMU v23 04/18] vfio: Add save and load functions for VFIO PCI devices

2020-05-21 Thread Dr. David Alan Gilbert
* Kirti Wankhede (kwankh...@nvidia.com) wrote: > These functions save and restore PCI device specific data - config > space of PCI device. > Tested save and restore with MSI and MSIX type. > > Signed-off-by: Kirti Wankhede > Reviewed-by: Neo Jia So I'm OK with this from the migration side, but

Re: [PATCH 3/4] configure: add flag to enable SafeStack

2020-05-21 Thread Stefan Hajnoczi
On Wed, Apr 29, 2020 at 03:44:19PM -0400, Daniele Buono wrote: > This patch adds a flag to enable the SafeStack instrumentation provided > by LLVM. > The checks make sure that the compiler supports the flags, and that we > are using the proper coroutine implementation (coroutine-ucontext). > While

[PATCH v8 06/62] target/riscv: add vector stride load and store instructions

2020-05-21 Thread LIU Zhiwei
Vector strided operations access the first memory element at the base address, and then access subsequent elements at address increments given by the byte offset contained in the x register specified by rs2. Vector unit-stride operations access elements stored contiguously in memory starting from

cluster_size got from backup_calculate_cluster_size()

2020-05-21 Thread Derek Su
Hi, The cluster_size got from backup_calculate_cluster_size(), MAX(BACKUP_CLUSTER_SIZE_DEFAULT, bdi.cluster_size), is 64K regardless of the target image's cluster size. For example: If the cluster size of source and target qcow2 images are both 16K, the 64K from

[PATCH v8 07/62] target/riscv: add vector index load and store instructions

2020-05-21 Thread LIU Zhiwei
Vector indexed operations add the contents of each element of the vector offset operand specified by vs2 to the base effective address to give the effective address of each element. Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson ---

Re: [PATCH] crypto: add "none" random provider

2020-05-21 Thread Daniel P . Berrangé
On Wed, May 20, 2020 at 03:20:23PM +0200, Marek Marczykowski-Górecki wrote: > In case of not using random-number needing feature, it makes sense to > skip RNG init too. This is especially helpful when QEMU is sandboxed in > Stubdomain under Xen, where there is very little entropy so initial >

[PATCH v8 11/62] target/riscv: vector widening integer add and subtract

2020-05-21 Thread LIU Zhiwei
Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 49 +++ target/riscv/insn32.decode | 16 ++ target/riscv/insn_trans/trans_rvv.inc.c | 186

Re: [PATCH V2] Add a new PIIX option to control PCI hot unplugging of devices on non-root buses

2020-05-21 Thread Michael S. Tsirkin
On Thu, May 21, 2020 at 09:32:17AM +0200, Igor Mammedow wrote: > On Wed, 20 May 2020 12:13:35 -0400 > "Michael S. Tsirkin" wrote: > > > On Wed, May 20, 2020 at 02:20:12PM +0200, Igor Mammedow wrote: > > > On Wed, 20 May 2020 07:23:21 -0400 > > > "Michael S. Tsirkin" wrote: > > > > > > > On

Re: [PATCH v3 19/22] microvm/acpi: use seabios with acpi=on

2020-05-21 Thread Igor Mammedov
On Wed, 20 May 2020 15:20:00 +0200 Gerd Hoffmann wrote: > With acpi=off continue to use qboot. > > Signed-off-by: Gerd Hoffmann Reviewed-by: Igor Mammedov > --- > hw/i386/microvm.c | 5 - > 1 file changed, 4 insertions(+), 1 deletion(-) > > diff --git a/hw/i386/microvm.c

[PATCH v8 15/62] target/riscv: vector narrowing integer right shift instructions

2020-05-21 Thread LIU Zhiwei
Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 13 target/riscv/insn32.decode | 6 ++ target/riscv/insn_trans/trans_rvv.inc.c | 90 + target/riscv/vector_helper.c

[PATCH v8 20/62] target/riscv: vector widening integer multiply instructions

2020-05-21 Thread LIU Zhiwei
Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 19 + target/riscv/insn32.decode | 6 +++ target/riscv/insn_trans/trans_rvv.inc.c | 8 target/riscv/vector_helper.c| 51

[PATCH v8 21/62] target/riscv: vector single-width integer multiply-add instructions

2020-05-21 Thread LIU Zhiwei
Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 33 ++ target/riscv/insn32.decode | 8 +++ target/riscv/insn_trans/trans_rvv.inc.c | 10 +++ target/riscv/vector_helper.c| 88

[PATCH v8 24/62] target/riscv: vector single-width saturating add and subtract

2020-05-21 Thread LIU Zhiwei
Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 33 ++ target/riscv/insn32.decode | 10 + target/riscv/insn_trans/trans_rvv.inc.c | 16 + target/riscv/vector_helper.c| 385

[PATCH v8 28/62] target/riscv: vector single-width scaling shift instructions

2020-05-21 Thread LIU Zhiwei
Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 17 target/riscv/insn32.decode | 6 ++ target/riscv/insn_trans/trans_rvv.inc.c | 8 ++ target/riscv/vector_helper.c| 117

[PATCH v8 32/62] target/riscv: vector widening floating-point add/subtract instructions

2020-05-21 Thread LIU Zhiwei
Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 17 +++ target/riscv/insn32.decode | 8 ++ target/riscv/insn_trans/trans_rvv.inc.c | 145 target/riscv/vector_helper.c

[PATCH v8 35/62] target/riscv: vector single-width floating-point fused multiply-add instructions

2020-05-21 Thread LIU Zhiwei
Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 49 + target/riscv/insn32.decode | 16 ++ target/riscv/insn_trans/trans_rvv.inc.c | 18 ++ target/riscv/vector_helper.c| 251

[PATCH v8 38/62] target/riscv: vector floating-point min/max instructions

2020-05-21 Thread LIU Zhiwei
Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 13 target/riscv/insn32.decode | 4 target/riscv/insn_trans/trans_rvv.inc.c | 6 ++ target/riscv/vector_helper.c

[PATCH v8 44/62] target/riscv: widening floating-point/integer type-convert instructions

2020-05-21 Thread LIU Zhiwei
Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/helper.h | 11 ++ target/riscv/insn32.decode | 5 +++ target/riscv/insn_trans/trans_rvv.inc.c | 47 + target/riscv/vector_helper.c| 42

Re: [PATCH v3 3/3] test-crypto-secret: add 'secret_keyring' object tests.

2020-05-21 Thread Daniel P . Berrangé
On Mon, May 18, 2020 at 11:28:04PM +0300, Alexey Krasikov wrote: > Add tests: > test_secret_keyring_good; > test_secret_keyring_revoked_key; > test_secret_keyring_expired_key; > test_secret_keyring_bad_serial_key; > test_secret_keyring_bad_key_access_right; > > Added tests require

[PATCH v8 45/62] target/riscv: narrowing floating-point/integer type-convert instructions

2020-05-21 Thread LIU Zhiwei
Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/helper.h | 11 ++ target/riscv/insn32.decode | 5 +++ target/riscv/insn_trans/trans_rvv.inc.c | 47 + target/riscv/vector_helper.c| 39

[PATCH v8 47/62] target/riscv: vector wideing integer reduction instructions

2020-05-21 Thread LIU Zhiwei
Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/helper.h | 7 +++ target/riscv/insn32.decode | 2 ++ target/riscv/insn_trans/trans_rvv.inc.c | 4 target/riscv/vector_helper.c| 11 +++ 4 files changed, 24

Re: [PATCH QEMU v23 06/18] vfio: Add VM state change handler to know state of VM

2020-05-21 Thread Dr. David Alan Gilbert
* Kirti Wankhede (kwankh...@nvidia.com) wrote: > VM state change handler gets called on change in VM's state. This is used to > set > VFIO device state to _RUNNING. > > Signed-off-by: Kirti Wankhede > Reviewed-by: Neo Jia Reviewed-by: Dr. David Alan Gilbert > --- > hw/vfio/migration.c

[PATCH v8 49/62] target/riscv: vector widening floating-point reduction instructions

2020-05-21 Thread LIU Zhiwei
Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/helper.h | 3 ++ target/riscv/insn32.decode | 2 ++ target/riscv/insn_trans/trans_rvv.inc.c | 3 ++ target/riscv/vector_helper.c| 46 + 4 files

Re: sharing intention for developing per-target, dynamically loadable accelerator modules

2020-05-21 Thread Claudio Fontana
On 5/19/20 9:53 AM, Claudio Fontana wrote: > On 5/18/20 8:18 PM, Alex Bennée wrote: >> >> Claudio Fontana writes: >> >>> Hello all, >>> >>> my intention would be to develop per-target, dynamically loadable >>> accelerator modules. >>> >>> This would allow to distribute a single QEMU base binary,

[PATCH v8 52/62] target/riscv: vmfirst find-first-set mask bit

2020-05-21 Thread LIU Zhiwei
Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/helper.h | 2 ++ target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvv.inc.c | 32 + target/riscv/vector_helper.c| 19 +++ 4

[PATCH v8 54/62] target/riscv: vector iota instruction

2020-05-21 Thread LIU Zhiwei
Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/helper.h | 5 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvv.inc.c | 27 +++ target/riscv/vector_helper.c| 29

Re: [PATCH v3 14/22] microvm: use 2G split unconditionally

2020-05-21 Thread Igor Mammedov
On Wed, 20 May 2020 15:19:55 +0200 Gerd Hoffmann wrote: > Looks like the logiv was copied over from q35. > > q35 does this for backward compatibility, there is no reason to do this > on microvm though. So split @ 2G unconditionally. > > Signed-off-by: Gerd Hoffmann Reviewed-by: Igor

[PATCH v8 00/62] target/riscv: support vector extension v0.7.1

2020-05-21 Thread LIU Zhiwei
This patchset implements the vector extension for RISC-V on QEMU. You can also find the patchset and all *test cases* in my repo(https://github.com/romanheros/qemu.git branch:vector-upstream-v8). All the test cases are in the directory qemu/tests/riscv/vector/. They are riscv64 linux user mode

[PATCH v8 02/62] target/riscv: implementation-defined constant parameters

2020-05-21 Thread LIU Zhiwei
vlen is the vector register length in bits. elen is the max element size in bits. vext_spec is the vector specification version, default value is v0.7.1. Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/cpu.c | 7 +++

Re: [PATCH 4/4] check-block: Enable iotests with SafeStack

2020-05-21 Thread Stefan Hajnoczi
On Wed, Apr 29, 2020 at 03:44:20PM -0400, Daniele Buono wrote: > SafeStack is a stack protection technique implemented in llvm. It is > enabled with a -fsanitize flag. > iotests are currently disabled when any -fsanitize option is used. > Since SafeStack is useful on production environments, and

[PATCH v8 09/62] target/riscv: add vector amo operations

2020-05-21 Thread LIU Zhiwei
Vector AMOs operate as if aq and rl bits were zero on each element with regard to ordering relative to other instructions in the same hart. Vector AMOs provide no ordering guarantee between element operations in the same vector AMO instruction Signed-off-by: LIU Zhiwei Reviewed-by: Alistair

[PATCH v8 10/62] target/riscv: vector single-width integer add and subtract

2020-05-21 Thread LIU Zhiwei
Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/helper.h | 25 ++ target/riscv/insn32.decode | 10 + target/riscv/insn_trans/trans_rvv.inc.c | 291 target/riscv/vector_helper.c

[PATCH v8 13/62] target/riscv: vector bitwise logical instructions

2020-05-21 Thread LIU Zhiwei
Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 25 target/riscv/insn32.decode | 9 + target/riscv/insn_trans/trans_rvv.inc.c | 11 ++ target/riscv/vector_helper.c

Re: [PATCH v3 16/22] microvm/acpi: add minimal acpi support

2020-05-21 Thread Igor Mammedov
On Wed, 20 May 2020 15:19:57 +0200 Gerd Hoffmann wrote: > $subject says all. Can be controlled using -M microvm,acpi=on/off. thanks for really nice and clean impl. There are a couple minor notes below, but otherwise Reviewed-by: Igor Mammedov > > Signed-off-by: Gerd Hoffmann > --- >

[PATCH v8 14/62] target/riscv: vector single-width bit shift instructions

2020-05-21 Thread LIU Zhiwei
Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 25 target/riscv/insn32.decode | 9 +++ target/riscv/insn_trans/trans_rvv.inc.c | 52 target/riscv/vector_helper.c

Re: [PULL 00/10] softfloat misc cleanups

2020-05-21 Thread Peter Maydell
On Tue, 19 May 2020 at 17:49, Richard Henderson wrote: > > The following changes since commit f2465433b43fb87766d79f42191607dac4aed5b4: > > Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request' > into staging (2020-05-19 13:42:58 +0100) > > are available in the Git repository

[PATCH] linux-user: limit check to HOST_LONG_BITS == 32

2020-05-21 Thread Alex Bennée
Newer clangs rightly spot that you can never exceed the full address space of 64 bit hosts with: linux-user/elfload.c:2076:41: error: result of comparison 'unsigned long' > 18446744073709551615 is always false [-Werror,-Wtautological-type-limit-compare] 4685 if ((guest_hiaddr -

[PATCH v8 22/62] target/riscv: vector widening integer multiply-add instructions

2020-05-21 Thread LIU Zhiwei
Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 22 target/riscv/insn32.decode | 7 target/riscv/insn_trans/trans_rvv.inc.c | 9 + target/riscv/vector_helper.c|

Re: [PATCH v3 21/22] [RfC] acpi: add per machine type acpi default

2020-05-21 Thread Igor Mammedov
On Wed, 20 May 2020 15:20:02 +0200 Gerd Hoffmann wrote: > Allow setting acpi default value for each machine type. > > Signed-off-by: Gerd Hoffmann > --- > include/hw/i386/x86.h | 1 + > hw/i386/x86.c | 21 ++--- > 2 files changed, 19 insertions(+), 3 deletions(-) > >

Re: [Bug 1877716] Re: Win10 guest unusable after a few minutes

2020-05-21 Thread Stefan Hajnoczi
The fix has been merged: https://git.qemu.org/?p=qemu.git;a=commit;h=f2465433b43fb87766d79f42191607dac4aed5b4 -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1877716 Title: Win10 guest unusable

[PATCH v8 25/62] target/riscv: vector single-width averaging add and subtract

2020-05-21 Thread LIU Zhiwei
Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis --- target/riscv/helper.h | 17 target/riscv/insn32.decode | 5 ++ target/riscv/insn_trans/trans_rvv.inc.c | 7 ++ target/riscv/vector_helper.c| 100 4 files

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