On Mon, Aug 31, 2020 at 01:43:07PM -0500, Babu Moger wrote:
> apic_id contains all the information required to build
> CPUID_8000_001E. core_id and node_id is already part of
> apic_id generated by x86_topo_ids_from_apicid.
>
> Also remove the restriction on number bits on core_id and
> node_id.
From: Klaus Jensen
The emulated nvme device (hw/block/nvme.c) is currently using an
internal Intel device id.
Prepare to change that by allocating a device id under the 1b36 (Red
Hat, Inc.) vendor id.
Signed-off-by: Klaus Jensen
Acked-by: Keith Busch
Acked-by: Gerd Hoffmann
Reviewed-by:
One of the goals of having less boilerplate on QOM declarations
is to avoid human error. Requiring an extra argument that is
never used is an opportunity for mistakes.
Remove the unused argument from OBJECT_DECLARE_TYPE and
OBJECT_DECLARE_SIMPLE_TYPE.
Coccinelle patch used to convert all users
On 9/18/20 4:38 PM, Eduardo Habkost wrote:
> On Mon, Aug 31, 2020 at 01:43:07PM -0500, Babu Moger wrote:
>> apic_id contains all the information required to build
>> CPUID_8000_001E. core_id and node_id is already part of
>> apic_id generated by x86_topo_ids_from_apicid.
>>
>> Also remove the
From: Richard Henderson
Fix alignment of CPURISCVState.vreg.
Signed-off-by: Richard Henderson
Reviewed-by: Alistair Francis
Message-Id: <20200916004638.2444147-6-richard.hender...@linaro.org>
Signed-off-by: Eduardo Habkost
---
target/riscv/cpu.c | 1 +
1 file changed, 1 insertion(+)
diff
On Sep 14 07:14, Dmitry Fomichev wrote:
> The emulation code has been changed to advertise NVM Command Set when
> "zoned" device property is not set (default) and Zoned Namespace
> Command Set otherwise.
>
> Handlers for three new NVMe commands introduced in Zoned Namespace
> Command Set
> -Original Message-
> From: Klaus Jensen
> Sent: Friday, September 18, 2020 5:20 PM
> To: Dmitry Fomichev
> Cc: Keith Busch ; Klaus Jensen
> ; Kevin Wolf ; Philippe
> Mathieu-Daudé ; Maxim Levitsky
> ; Fam Zheng ; Niklas Cassel
> ; Damien Le Moal ;
> qemu-bl...@nongnu.org;
On Fri, Sep 04, 2020 at 04:54:16PM +0200, Vitaly Kuznetsov wrote:
> There was a typo which went unnoticed.
>
> Fixes: e48ddcc6ce13 ("i386/kvm: implement 'hv-passthrough' mode")
> Signed-off-by: Vitaly Kuznetsov
Similar fix had been submitted at:
On Fri, Sep 04, 2020 at 04:54:13PM +0200, Vitaly Kuznetsov wrote:
> As a preparation to expanding Hyper-V CPU features early, move
> hyperv_interface_id initialization to x86_cpu_realizefn().
>
> Signed-off-by: Vitaly Kuznetsov
> ---
> target/i386/cpu.c | 6 ++
> target/i386/cpu.h | 1 +
>
> -Original Message-
> From: Klaus Jensen
> Sent: Friday, September 18, 2020 5:30 PM
> To: Dmitry Fomichev
> Cc: Keith Busch ; Klaus Jensen
> ; Kevin Wolf ; Philippe
> Mathieu-Daudé ; Maxim Levitsky
> ; Fam Zheng ; Niklas Cassel
> ; Damien Le Moal ;
> qemu-bl...@nongnu.org;
On Fri, Sep 04, 2020 at 04:54:15PM +0200, Vitaly Kuznetsov wrote:
> As a preparation to expanding Hyper-V CPU features early, move
> hyperv_limits initialization to x86_cpu_realizefn().
>
> Signed-off-by: Vitaly Kuznetsov
> ---
> target/i386/cpu.c | 5 +
> target/i386/cpu.h | 1 +
>
On Tue, Aug 20, 2019 at 06:30:30PM +0800, Zhenyu Wang wrote:
> Fix typo to use correct edx value for FEATURE_HYPERV_EDX when
> hyperv_passthrough is enabled.
>
> Signed-off-by: Zhenyu Wang
CCing other maintainers (please use ./scripts/get_maintainer.pl
to make sure maintainers don't miss
On Fri, Sep 04, 2020 at 04:54:31PM +0200, Vitaly Kuznetsov wrote:
> To make Hyper-V features appear in e.g. QMP query-cpu-model-expansion we
> need to expand and set the corresponding CPUID leaves early. Modify
> x86_cpu_get_supported_feature_word() to call newly intoduced Hyper-V
> specific
Patchew URL:
https://patchew.org/QEMU/20200918204714.27276-1-ehabk...@redhat.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20200918204714.27276-1-ehabk...@redhat.com
Subject: [PULL 00/17] QOM queue, 2020-09-18
Patchew URL:
https://patchew.org/QEMU/20200918204714.27276-1-ehabk...@redhat.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20200918204714.27276-1-ehabk...@redhat.com
Subject: [PULL 00/17] QOM queue, 2020-09-18
We can not have more group than 'wpgrps_size'.
Assert if we are accessing a group above this limit.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/sd/sd.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/sd/sd.c b/hw/sd/sd.c
index 4454d168e2f..c3febed2434 100644
--- a/hw/sd/sd.c
+++
On Tue, Sep 15, 2020 at 05:46:32PM -0700, Richard Henderson wrote:
> I've seen some failures on arm and s390x hosts after
> enabling host vector support. It turns out that the
> malloc for these hosts does not provide 16-byte alignment.
>
> We already have a function that can alloc with
We'll need a separate function, which will only "mark" request
serialising with specified align but not wait for conflicting
requests. So, it will be like old bdrv_mark_request_serialising(),
before merging bdrv_wait_serialising_requests_locked() into it.
To reduce the possible mess, let's do the
The comments states, that on misaligned request we should have already
been waiting. But for bdrv_padding_rmw_read, we called
bdrv_mark_request_serialising with align = request_alignment, and now
we serialise with align = cluster_size. So we may have to wait again
with larger alignment.
Note,
Do generic processing even for drivers which define .bdrv_check_perm
handler. It's needed for further preallocate filter: it will need to do
additional action on bdrv_check_perm, but don't want to reimplement
generic logic.
The patch doesn't change existing behaviour: the only driver that
Signed-off-by: Richard Henderson
---
v2: Fix select offsetting and argument order (laurent desnogues).
---
target/arm/helper-sve.h| 14 ++
target/arm/sve.decode | 12 +
target/arm/sve_helper.c| 23
target/arm/translate-sve.c | 55
Signed-off-by: Richard Henderson
---
target/arm/helper-sve.h| 14
target/arm/sve.decode | 5 +
target/arm/sve_helper.c| 44 ++
target/arm/translate-sve.c | 39 +
4 files changed, 102 insertions(+)
Signed-off-by: Richard Henderson
---
target/arm/helper-sve.h| 14 ++
target/arm/sve.decode | 14 ++
target/arm/sve_helper.c| 30 +
target/arm/translate-sve.c | 54 ++
4 files changed, 112 insertions(+)
diff
Signed-off-by: Richard Henderson
---
v2: Fix select offsets (laurent desnogues).
---
target/arm/helper-sve.h| 24
target/arm/sve.decode | 19
target/arm/sve_helper.c| 43 +++
target/arm/translate-sve.c | 46
Signed-off-by: Richard Henderson
---
target/arm/helper-sve.h| 54 ++
target/arm/sve.decode | 11
target/arm/sve_helper.c| 39 +++
target/arm/translate-sve.c | 8 ++
4 files changed, 112 insertions(+)
diff
This completes the section "SVE2 bitwise shift right narrow".
Signed-off-by: Richard Henderson
---
target/arm/helper-sve.h| 16 ++
target/arm/sve.decode | 4 ++
target/arm/sve_helper.c| 24 +
target/arm/translate-sve.c | 105 +
4
Signed-off-by: Richard Henderson
---
target/arm/helper-sve.h| 9 +
target/arm/sve.decode | 18 ++
target/arm/sve_helper.c| 30 ++
target/arm/translate-sve.c | 32
4 files changed, 81 insertions(+),
Exclude PMULL from this category for the moment.
Signed-off-by: Richard Henderson
---
target/arm/helper-sve.h| 15 +++
target/arm/sve.decode | 9 +
target/arm/sve_helper.c| 31 +++
target/arm/translate-sve.c | 9 +
4 files
In addition, use the same vector generator interface for AdvSIMD.
This fixes a bug in which the AdvSIMD insn failed to clear the
high bits of the SVE register.
Signed-off-by: Richard Henderson
---
target/arm/helper-sve.h| 4 ++
target/arm/helper.h| 2 +
Currently only used by FMUL, but will shortly be used more.
Signed-off-by: Richard Henderson
---
target/arm/sve.decode | 16
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
index 5815ba9b1c..a121e55f07 100644
---
From: Philippe Mathieu-Daudé
The 'arm_quanta_gsj_initrd' test is timeouting on GitLab CI:
https://gitlab.com/philmd/qemu/-/jobs/745483978#L846
and also sometimes on my workstation, so proceed as with
the other slow tests: do not run it by default.
The test can still be run setting the
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 5 +
target/arm/sve.decode | 7 +++
target/arm/translate-sve.c | 38 ++
3 files changed, 50 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index
From: Stephen Long
Signed-off-by: Stephen Long
Message-Id: <20200428174332.17162-2-stepl...@quicinc.com>
Signed-off-by: Richard Henderson
---
target/arm/helper-sve.h| 5 +
target/arm/sve.decode | 4
target/arm/sve_helper.c| 20
On 9/16/20 7:19 AM, Claudio Fontana wrote:
> Motivation and higher level steps:
>
> https://lists.gnu.org/archive/html/qemu-devel/2020-05/msg04628.html
>
> Current state is mostly all reviewed, but I include here a few resolutions
> of rebasing conflicts and a new patch to use current_machine
From: Klaus Jensen
Fix a typo in the sq doorbell trace event.
Signed-off-by: Klaus Jensen
---
hw/block/trace-events | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/block/trace-events b/hw/block/trace-events
index ec94c56a4165..8ff4cbc4932c 100644
---
From: Klaus Jensen
Style fixes.
Signed-off-by: Klaus Jensen
Reviewed-by: Philippe Mathieu-Daudé
---
hw/block/nvme.c | 25 +
1 file changed, 13 insertions(+), 12 deletions(-)
diff --git a/hw/block/nvme.c b/hw/block/nvme.c
index 78c3ac80fd4c..10568cbf8761 100644
---
From: Klaus Jensen
Make the default request status NVME_SUCCESS so only error status codes
have to be set.
Signed-off-by: Klaus Jensen
Reviewed-by: Philippe Mathieu-Daudé
---
hw/block/nvme.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/hw/block/nvme.c
From: Klaus Jensen
Move common error handling to a label.
Signed-off-by: Klaus Jensen
---
hw/block/nvme.c | 16 +---
1 file changed, 9 insertions(+), 7 deletions(-)
diff --git a/hw/block/nvme.c b/hw/block/nvme.c
index 8ffe407ef658..78c3ac80fd4c 100644
--- a/hw/block/nvme.c
+++
From: Klaus Jensen
There are two reasons for changing this:
1. The nvme device currently uses an internal Intel device id.
2. Since commits "nvme: fix write zeroes offset and count" and "nvme:
support multiple namespaces" the controller device no longer has
the quirks that the
From: Richard Henderson
Fix alignment of CPUARMState.vfp.zregs.
Signed-off-by: Richard Henderson
Message-Id: <20200916004638.2444147-4-richard.hender...@linaro.org>
Signed-off-by: Eduardo Habkost
---
target/arm/cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/arm/cpu.c
From: Richard Henderson
Fix alignment of CPUPPCState.vsr.
Signed-off-by: Richard Henderson
Acked-by: David Gibson
Message-Id: <20200916004638.2444147-5-richard.hender...@linaro.org>
Signed-off-by: Eduardo Habkost
---
target/ppc/translate_init.c.inc | 1 +
1 file changed, 1 insertion(+)
object_class_dynamic_cast_assert() is not used by
INTERFACE_CHECK, remove misleading mention of that function in
the documentation.
Message-Id: <20200916193101.511600-2-ehabk...@redhat.com>
Signed-off-by: Eduardo Habkost
---
include/qom/object.h | 2 +-
1 file changed, 1 insertion(+), 1
From: Markus Armbruster
object_property_get_enum() is the only object_property_FOO() that is
documented to return an undefined value on error. It does no such
thing, actually: it returns 0 on some errors, and -1 on others.
Needlessly complicated. Always return -1 on error, and adjust the
On Mon, Sep 14, 2020 at 02:56:17PM +0100, Daniel P. Berrangé wrote:
> When debugging QEMU it is often useful to put a breakpoint on the
> error_setg_internal method impl.
>
> Unfortunately the object_property_add / object_class_property_add
> methods call object_property_find /
Some of the enum constant names conflict with a QOM type check
macro (SIFIVE_E_PRCI). This needs to be addressed to allow us to
transform the QOM type check macros into functions generated by
OBJECT_DECLARE_TYPE().
Rename all the constants to SIFIVE_E_DEV_*, to avoid conflicts.
Signed-off-by:
From: Marc-André Lureau
Add an alias target "update-dtb" to recompile the device-tree "sources"
to the "blob" format.
Signed-off-by: Marc-André Lureau
---
pc-bios/Makefile| 19 ---
pc-bios/meson.build | 12
2 files changed, 12 insertions(+), 19 deletions(-)
Hi Luwei Kang,
I was looking for info on intel-pt and just saw this series, and
it was never reviewed or merged (sorry for missing it!). Is this
still the approach we want to follow for intel-pt?
I'm CCing Jiri Denemark because this might be relevant for a
libvirt issue related to intel-pt we
From: Marc-André Lureau
Hi,
Here is a series of patches to convert the remaining Makefile in pc-bios/ to
meson. I have done various tests to check that the resulting binaries are
working as expected, but I didn't cover it all, and I am not sure the test su=
ite
covers them all either.
Please
On Fri, Sep 04, 2020 at 04:54:12PM +0200, Vitaly Kuznetsov wrote:
> As a preparation to expanding Hyper-V CPU features early, move
> hyperv_vendor_id initialization to x86_cpu_realizefn().
>
> Signed-off-by: Vitaly Kuznetsov
> ---
> target/i386/cpu.c | 15 ++-
> target/i386/cpu.h |
On Fri, Sep 04, 2020 at 04:54:31PM +0200, Vitaly Kuznetsov wrote:
> To make Hyper-V features appear in e.g. QMP query-cpu-model-expansion we
> need to expand and set the corresponding CPUID leaves early. Modify
> x86_cpu_get_supported_feature_word() to call newly intoduced Hyper-V
> specific
Public bug reported:
qemu trunk as of today leaks memory FAST when freedos' edit is running.
To reproduce, download:
https://www.ibiblio.org/pub/micro/pc-
stuff/freedos/files/repositories/1.3/cdrom.iso
Then run:
$ qemu-system-i386 -cdrom cdrom.iso
select your language then select "return to
Patchew URL:
https://patchew.org/QEMU/20200918204714.27276-1-ehabk...@redhat.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20200918204714.27276-1-ehabk...@redhat.com
Subject: [PULL 00/17] QOM queue, 2020-09-18
Patchew URL:
https://patchew.org/QEMU/20200918204714.27276-1-ehabk...@redhat.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20200918204714.27276-1-ehabk...@redhat.com
Subject: [PULL 00/17] QOM queue, 2020-09-18
The following changes since commit 053a4177817db307ec854356e95b5b350800a216:
Merge remote-tracking branch 'remotes/philmd-gitlab/tags/fw_cfg-20200918'
into staging (2020-09-18 16:34:26 +0100)
are available in the Git repository at:
git://github.com/ehabkost/qemu.git tags/machine-next-pull
From: Richard Henderson
It turns out that some hosts have a default malloc alignment less
than that required for vectors.
We assume that, with compiler annotation on CPUArchState, that we
can properly align the vector portion of the guest state. Fix the
alignment of the allocation by using
On Mon, Sep 14, 2020 at 09:37:20AM +0200, Igor Mammedov wrote:
> On Fri, 11 Sep 2020 11:04:47 -0400
> "Michael S. Tsirkin" wrote:
>
> > On Fri, Sep 11, 2020 at 09:32:02AM -0400, Igor Mammedov wrote:
> > > it's was deprecated since 3.1
> > >
> > > Support for invalid topologies is removed, the
On Fri, Sep 04, 2020 at 04:54:14PM +0200, Vitaly Kuznetsov wrote:
> As a preparation to expanding Hyper-V CPU features early, move
> hyperv_version_id initialization to x86_cpu_realizefn().
>
> Signed-off-by: Vitaly Kuznetsov
> ---
> target/i386/cpu.c | 4
> target/i386/cpu.h | 1 +
>
On Fri, Sep 04, 2020 at 04:54:21PM +0200, Vitaly Kuznetsov wrote:
> We have all the required data in X86CPU already and as we are about to
> split hyperv_handle_properties() into hyperv_expand_features()/
> hyperv_fill_cpuids() we can remove the blind copy. The functional change
> is that QEMU
Patchew URL:
https://patchew.org/QEMU/20200918204714.27276-1-ehabk...@redhat.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20200918204714.27276-1-ehabk...@redhat.com
Subject: [PULL 00/17] QOM queue, 2020-09-18
Patchew URL:
https://patchew.org/QEMU/20200918204759.225810-1-marcandre.lur...@redhat.com/
Hi,
This series failed the docker-quick@centos7 build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST
Patchew URL:
https://patchew.org/QEMU/20200918204714.27276-1-ehabk...@redhat.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20200918204714.27276-1-ehabk...@redhat.com
Subject: [PULL 00/17] QOM queue, 2020-09-18
Patchew URL:
https://patchew.org/QEMU/20200918204714.27276-1-ehabk...@redhat.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20200918204714.27276-1-ehabk...@redhat.com
Subject: [PULL 00/17] QOM queue, 2020-09-18
Hi, Richard,
On Wed, Sep 16, 2020 at 11:15 PM Richard Henderson
wrote:
>
> On 9/15/20 7:12 PM, Huacai Chen wrote:
> > +case OPC_GSLQ:
> > +gen_base_offset_addr(ctx, t0, rs, lsq_offset);
> > +tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEQ |
> > +
Hi, Philippe,
On Thu, Sep 17, 2020 at 3:53 PM Philippe Mathieu-Daudé wrote:
>
> On 9/16/20 12:47 PM, Philippe Mathieu-Daudé wrote:
> > On 9/16/20 11:49 AM, Huacai Chen wrote:
> >> On Wed, Sep 16, 2020 at 3:56 PM Philippe Mathieu-Daudé
> >> wrote:
> >>> On 9/16/20 4:12 AM, Huacai Chen wrote:
>
Patchew URL:
https://patchew.org/QEMU/20200918204714.27276-1-ehabk...@redhat.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20200918204714.27276-1-ehabk...@redhat.com
Subject: [PULL 00/17] QOM queue, 2020-09-18
Chiming in here as the user who initially suggested Arch use this:
--extra-ldflags="$LDFLAGS"
qemu-5.0.0 introduced a breaking change whereby LDFLAGS from the
environment were ignored. For Arch, this resulted in exclusion of `--as-
needed' from the link, which naturally caused dependency chaos.
On Fri, Sep 04, 2020 at 04:54:18PM +0200, Vitaly Kuznetsov wrote:
> As a preparation to expanding Hyper-V CPU features early, add
> reserved FEAT_HYPERV_ECX CPUID leaf.
>
> Signed-off-by: Vitaly Kuznetsov
> ---
> target/i386/cpu.c | 5 +
> target/i386/cpu.h | 1 +
> target/i386/kvm.c | 2 ++
Patchew URL:
https://patchew.org/QEMU/20200918204714.27276-1-ehabk...@redhat.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20200918204714.27276-1-ehabk...@redhat.com
Subject: [PULL 00/17] QOM queue, 2020-09-18
Huh. I thought we ignored the environment LDFLAGS/CFLAGS from much
earlier than 5.0 and was about to ask if honouring it was a change
introduced with the Meson switch! My (not necessarily very considered)
opinion is that generally it's better not to honour the environment
CFLAGS and LDFLAGS
This patch shold fix the regression:
diff --git a/configure b/configure
index 0004c46525..0786144043 100755
--- a/configure
+++ b/configure
@@ -7414,6 +7414,7 @@ NINJA=${ninja:-$PWD/ninjatool} $meson setup \
-Dwerror=$(if test "$werror" = yes; then echo true; else echo false;
fi) \
Note, this also occurs with freeDOS 1.2, at least.
Note 2, 4.2 stable does not exhibit the bug.
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1896298
Title:
memory leak
Status in QEMU:
New
On 2020/9/18 22:06, Fam Zheng wrote:
>
> I can see how blocking in a slow io_submit can cause trouble for main
> thread. I think one way to fix it (until it's made truly async in new
> kernels) is moving the io_submit call to thread pool, and wrapped in a
> coroutine, perhaps.
>
I'm not sure if
And qemu log build using make -V=1.
Hope it helps.
** Attachment added: "qemuv1-2.log"
https://bugs.launchpad.net/qemu/+bug/1896096/+attachment/5412260/+files/qemuv1-2.log
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
Configure line: configure \
--prefix=/usr \
--sysconfdir=/etc \
--localstatedir=/var \
--libexecdir=/usr/lib/qemu \
--smbd=/usr/bin/smbd \
--extra-ldflags="-Wl,-O1,--sort-common,--as-needed,-z,relro,-z,now" \
--enable-modules \
--enable-sdl \
--disable-werror \
As it is legal to WRITE/ERASE the address/block 0,
change the value of this definition to an illegal
address: UINT32_MAX.
Signed-off-by: Philippe Mathieu-Daudé
---
Cc: Dr. David Alan Gilbert
Cc: Markus Armbruster
Same problem I had with the pflash device last year...
This break migration :(
On 9/18/20 4:33 PM, Philippe Mathieu-Daudé wrote:
> The 'arm_quanta_gsj_initrd' test is timeouting on GitLab CI:
> https://gitlab.com/philmd/qemu/-/jobs/745483978#L846
> and also sometimes on my workstation, so proceed as with
> the other slow tests: do not run it by default.
> The test can still
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
tests/qemu-iotests/298 | 186 +
tests/qemu-iotests/298.out | 5 +
tests/qemu-iotests/group | 1 +
3 files changed, 192 insertions(+)
create mode 100644 tests/qemu-iotests/298
create mode 100644
Split these operations out into a header that can be shared
between neon and sve. The "sat" pointer acts both as a boolean
for control of saturating behavior and controls the difference
in behavior between neon and sve -- QC bit or no QC bit.
Widen the shift operand in the new helpers, as the
Wrote too much with punpk1 with vl % 512 != 0.
Reviewed-by: Peter Maydell
Reported-by: Laurent Desnogues
Signed-off-by: Richard Henderson
---
target/arm/sve_helper.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
index
Missed out on compressing the second half of a predicate
with length vl % 512 > 256.
Adjust all of the x + (y << s) to x | (y << s) as a
general style fix. Drop the extract64 because the input
uint64_t are known to be already zero-extended from the
current size of the predicate.
Reported-by:
Signed-off-by: Richard Henderson
---
v2: Fix sqabs, sqneg (laurent desnogues)
---
target/arm/helper-sve.h| 13 +++
target/arm/sve.decode | 7 ++
target/arm/sve_helper.c| 29 +++
target/arm/translate-sve.c | 47 ++
Signed-off-by: Richard Henderson
---
target/arm/helper-sve.h| 5 +
target/arm/sve.decode | 5 +
target/arm/sve_helper.c| 20
target/arm/translate-sve.c | 19 +++
4 files changed, 49 insertions(+)
diff --git a/target/arm/helper-sve.h
From: Stephen Long
Signed-off-by: Stephen Long
Reviewed-by: Richard Henderson
Signed-off-by: Richard Henderson
---
v2: Load all inputs before writing any output (laurent desnogues)
---
target/arm/helper-sve.h| 35 +
target/arm/sve.decode | 8 +++
Rename the existing sve_while (less-than) helper to sve_whilel
to make room for a new sve_whileg helper for greater-than.
Signed-off-by: Richard Henderson
---
v2: Use a new helper function to implement this.
---
target/arm/helper-sve.h| 3 +-
target/arm/sve.decode | 2 +-
Signed-off-by: Richard Henderson
---
target/arm/sve.decode | 8
target/arm/translate-sve.c | 23 +++
2 files changed, 31 insertions(+)
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
index fa0a572da6..467a93052f 100644
--- a/target/arm/sve.decode
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 5 +
target/arm/sve.decode | 4
target/arm/translate-sve.c | 16
3 files changed, 25 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index f5052a58a4..67b2834035 100644
---
For SVE, we potentially have a 4th argument coming from the
movprfx instruction. Currently we do not optimize movprfx,
so the problem is not visible.
Signed-off-by: Richard Henderson
---
target/arm/helper.h | 20 +++---
target/arm/sve.decode | 7 +-
Used by FMLA and DOT, but will shortly be used more.
Split FMLA from FMLS to avoid an extra sub field;
similarly for SDOT from UDOT.
Signed-off-by: Richard Henderson
---
target/arm/sve.decode | 29 +++--
target/arm/translate-sve.c | 38
Signed-off-by: Richard Henderson
---
target/arm/helper.h| 14 ++
target/arm/sve.decode | 8
target/arm/translate-sve.c | 8
target/arm/vec_helper.c| 88 ++
4 files changed, 118 insertions(+)
diff --git a/target/arm/helper.h
Signed-off-by: Richard Henderson
---
target/arm/helper-sve.h| 6 ++
target/arm/sve.decode | 12 +++
target/arm/sve_helper.c| 50 +
target/arm/translate-sve.c | 213 +
4 files changed, 281 insertions(+)
diff --git
From: Stephen Long
Add decoding logic for SVE2 64-bit/32-bit gather non-temporal
load insns.
64-bit
* LDNT1SB
* LDNT1B (vector plus scalar)
* LDNT1SH
* LDNT1H (vector plus scalar)
* LDNT1SW
* LDNT1W (vector plus scalar)
* LDNT1D (vector plus scalar)
32-bit
* LDNT1SB
* LDNT1B (vector plus
Signed-off-by: Richard Henderson
---
target/arm/sve.decode | 6 ++
target/arm/translate-sve.c | 11 +++
2 files changed, 17 insertions(+)
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
index 0be8a020f6..9b0d0f3a5d 100644
--- a/target/arm/sve.decode
+++
Signed-off-by: Richard Henderson
---
target/arm/sve.decode | 4 ++
target/arm/translate-sve.c | 97 ++
2 files changed, 101 insertions(+)
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
index 6808ff4194..e0d093c5d7 100644
---
Signed-off-by: Richard Henderson
---
target/arm/helper.h| 10 +
target/arm/sve.decode | 4 ++
target/arm/translate-sve.c | 18
target/arm/vec_helper.c| 84 ++
4 files changed, 116 insertions(+)
diff --git a/target/arm/helper.h
You have to unset LDFLAGS, or remove -pie. Specifying --extra-ldflags is
useless because Meson already obeys the LDFLAGS environment variable.
Il ven 18 set 2020, 19:11 Frederic Bezies <1896...@bugs.launchpad.net> ha
scritto:
> And qemu log build using make -V=1.
>
> Hope it helps.
>
> **
From: Babu Moger
apic_id contains all the information required to build
CPUID_8000_001E. core_id and node_id is already part of
apic_id generated by x86_topo_ids_from_apicid.
Also remove the restriction on number bits on core_id and
node_id.
Remove all the hardcoded values and replace with
From: Vitaly Kuznetsov
Hyper-V TLFS prior to version 6.0 had a mistake in it: special value
'0x' for CPUID 0x4004.EBX was called 'never to retry', this
looked weird (like why it's not '0' which supposedly have the same effect?)
but nobody raised the question. In TLFS version 6.0 the
The following changes since commit 053a4177817db307ec854356e95b5b350800a216:
Merge remote-tracking branch 'remotes/philmd-gitlab/tags/fw_cfg-20200918'
into staging (2020-09-18 16:34:26 +0100)
are available in the Git repository at:
git://github.com/ehabkost/qemu.git tags/x86-next-pull
From: Klaus Jensen
This is the next round of my patches for the nvme device.
This includes a bit of cleanup and two new features:
* support for scatter/gather lists
* multiple namespaces support through a new nvme-ns device
Finally, the series wraps up with changing the PCI vendor and
From: Klaus Jensen
Since the controller has only supported PRPs so far it has not been
required to check the ending address (addr + len - 1) of the CMB access
for validity since it has been guaranteed to be in range of the CMB.
This changes when the controller adds support for SGLs (next
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