On 25/11/2020 11.54, Thomas Huth wrote:
> We need the CCW address on the libvirt side to correctly identify
> the disk, so add this information to the GuestDiskAddress on s390x.
>
> Buglink: https://bugzilla.redhat.com/show_bug.cgi?id=1755075
> Signed-off-by: Thomas Huth
> ---
>
On Sat, Dec 12, 2020 at 12:15:29AM +, Peter Maydell wrote:
> This patchseries converts the PPC UIC "Universal Interrupt
> Controller" to a QOM device. My main reason for doing it is that
> this fixes a couple of long-standing trivial Coverity issues -- the
> current ppcuic_init() function
On Sat, Dec 12, 2020 at 12:15:31AM +, Peter Maydell wrote:
> Currently the PPC UIC ("Universal Interrupt Controller") is implemented
> as a non-QOM device in ppc4xx_devs.c. Convert it to a proper QOM device
> in hw/intc.
>
> The ppcuic_init() function is retained for the moment with its
On Mon, Dec 14, 2020 at 6:24 PM Alex Bennée wrote:
>
>
> Bin Meng writes:
>
> > From: Bin Meng
> >
> > At present the upstream U-Boot (as of today, v2021.01-rc3) does not
> > boot on QEMU sabrelite machine.
>
> Are there any public build artefacts for u-boot on saberlite that could
> be used
On Wed, 28 Oct 2020 at 14:26, Mihai Carabas wrote:
>
> From: Peng Hao
>
> Add mmio mode as a pci device support info in docs/specs/pvpanic.txt.
>
> Signed-off-by: Peng Hao
> Signed-off-by: Mihai Carabas
> ---
> docs/specs/pvpanic.txt | 12 +++-
> 1 file changed, 11 insertions(+), 1
On Wed, 28 Oct 2020 at 14:20, Mihai Carabas wrote:
>
> From: Philippe Mathieu-Daudé
>
> The 'pvpanic' ISA device can be use by any machine with an ISA bus.
>
> Reviewed-by: Peter Maydell
> Signed-off-by: Philippe Mathieu-Daudé
> Signed-off-by: Peng Hao
> Signed-off-by: Mihai Carabas
> ---
>
On Fri, 11 Dec 2020 17:05:27 -0500
Eduardo Habkost wrote:
> The function will be moved to common QOM code, as it is not
> specific to TYPE_DEVICE anymore.
>
> Reviewed-by: Stefan Berger
> Signed-off-by: Eduardo Habkost
> ---
> Changes v1 -> v2:
> * Rename to object_field_prop_ptr() instead of
La 14.12.2020 13:03, Peter Maydell a scris:
On Wed, 28 Oct 2020 at 14:17, Mihai Carabas wrote:
This patchset adds support for pvpanic pci device. The patchset was assembled
from chuncks from some old patches [1] from 2018 which were left unmerged and
some additions from me.
How to test this:
The kernel KVM_CLEAR_DIRTY_LOG interface has align requirement on both the
start and the size of the given range of pages. We have been careful to
handle the unaligned cases when performing CLEAR on one slot. But it seems
that we forget to take the unaligned *size* case into account when
preparing
Public bug reported:
When I was fuzzing virtio-vga device of the latest QEMU (1758428, Dec
12, built with --enable-sanitizers --enable-fuzzing), an assertion
failed in include/exec/memory_ldst_cached.h.inc.
--[ Reproducer
cat << EOF | ./build/i386-softmmu/qemu-system-i386 -machine accel=qtest \
On 10/12/20 14:47, marcandre.lur...@redhat.com wrote:
From: Marc-André Lureau
Hi,
Since commit efc6c07 ("configure: Add a test for the minimum compiler version"),
QEMU explicitely depends on GCC >= 4.8.
v3:
- drop first patch replacing QEMU_GNUC_PREREQ with G_GNUC_CHECK_VERSION
- add
On Fri, 11 Dec 2020 17:05:15 -0500
Eduardo Habkost wrote:
> Replace `Property *prop` parameter with `char *name`, to reduce
> dependency of getter and setter functions on the Property struct
> (which will be changed in following patches).
>
> Signed-off-by: Eduardo Habkost
> ---
> This is a
Bin Meng writes:
> From: Bin Meng
>
> At present, when booting U-Boot on QEMU sabrelite, we see:
>
> Net: Board Net Initialization Failed
> No ethernet found.
>
> U-Boot scans PHY at address 4/5/6/7 (see board_eth_init() in the
> U-Boot source: board/boundary/nitrogen6x/nitrogen6x.c).
On Mon, Dec 14, 2020 at 6:42 PM Alex Bennée wrote:
>
>
> Bin Meng writes:
>
> > From: Bin Meng
> >
> > At present, when booting U-Boot on QEMU sabrelite, we see:
> >
> > Net: Board Net Initialization Failed
> > No ethernet found.
> >
> > U-Boot scans PHY at address 4/5/6/7 (see
On Mon, 14 Dec 2020 at 10:47, Peter Maydell wrote:
>
> On Wed, 28 Oct 2020 at 14:20, Mihai Carabas wrote:
> >
> > From: Philippe Mathieu-Daudé
> >
> > The 'pvpanic' ISA device can be use by any machine with an ISA bus.
> >
> > Reviewed-by: Peter Maydell
> > Signed-off-by: Philippe
On Wed, 28 Oct 2020 at 14:17, Mihai Carabas wrote:
>
> This patchset adds support for pvpanic pci device. The patchset was assembled
> from chuncks from some old patches [1] from 2018 which were left unmerged and
> some additions from me.
>
> How to test this:
> /usr/bin/qemu-system-aarch64 \
>
Section 13.5.2 of LoPAPR mandates various DR related indentifiers
for all hot-pluggable entities to be exposed in the "ibm,drc-indexes",
"ibm,drc-power-domains", "ibm,drc-names" and "ibm,drc-types" properties
of their parent node. These properties are created with spapr_dt_drc().
PHBs and LMBs
On Wed, 16 Sep 2020 10:51:50 +0100
Stefan Hajnoczi wrote:
> Make it possible to present read-only files to the guest as "unarmed"
> NVDIMMs. The Linux NVDIMM device (/dev/pmemX) is read-only.
>
> Acked-by: Michael S. Tsirkin
> Reviewed-by: Philippe Mathieu-Daudé
> Signed-off-by: Stefan
Keith Packard writes:
> This series adds support for RISC-V Semihosting, version 0.2 as
> specified here:
>
> https://github.com/riscv/riscv-semihosting-spec/releases/tag/0.2
>
> This specification references the ARM semihosting release 2.0 as specified
> here:
>
>
On 05/12/20 00:06, Daniele Buono wrote:
Document how to compile with CFI and how to maintain CFI-safe code
Signed-off-by: Daniele Buono
---
docs/devel/control-flow-integrity.rst | 137 ++
1 file changed, 137 insertions(+)
create mode 100644
11.12.2020 21:39, Vladimir Sementsov-Ogievskiy wrote:
Hi all!
We want 64bit write-zeroes, and for this, convert all io functions to
64bit.
We chose signed type, to be consistent with off_t (which is signed) and
with possibility for signed return type (where negative value means
error).
Please
On Mon, 14 Dec 2020 at 12:36, Leif Lindholm wrote:
>
> Signed-off-by: Leif Lindholm
> ---
> v1->v2:
> - Correct CCSIDR_EL1 field sizes.
Hi -- could you resend the whole series for a v2, please?
The tools (and people) that handle patches get a bit confused
by partial series.
thanks
-- PMM
Disable the run-gdbstub-sha1 test: it provokes an internal error
assertion failure in Ubuntu gdb 8.1.1-0ubuntu1 (Ubuntu gdb
8.1-0ubuntu3.2 was fine) :
timeout 60 /home/petmay01/linaro/qemu-for-merges/tests/guest-debug/run-test.py
--gdb /usr/bin/gdb-multiar
On Sat, Dec 12, 2020 at 12:15:32AM +, Peter Maydell wrote:
> Switch the virtex_ml507 board to directly creating and
> configuring the UIC, rather than doing it via the old
> ppcuic_init() helper function.
>
> This fixes a trivial Coverity-detected memory leak where
> we were leaking the array
罗勇刚(Yonggang Luo) writes:
> On Mon, Dec 14, 2020 at 2:36 AM Philippe Mathieu-Daudé
> wrote:
>>
>> On Wed, Nov 18, 2020 at 4:11 PM Thomas Huth wrote:
>> > On 18/11/2020 15.07, Alex Bennée wrote:
>> > > These seem to trigger timeouts with some regularity.
>> > >
>> > > Signed-off-by: Alex
It is currently impossible to hot-unplug a memory device between
machine reset and CAS.
(qemu) device_del dimm1
Error: Memory hot unplug not supported for this guest
This limitation was introduced in order to provide an explicit
error path for older guests that didn't support hot-plug event
On Mon, Dec 14, 2020 at 6:32 PM Alex Bennée wrote:
>
>
> Bin Meng writes:
>
> > From: Bin Meng
> >
> > U-Boot expects PMU_MISC0 register bit 7 is set (see init_bandgap()
> > in arch/arm/mach-imx/mx6/soc.c) during boot. This bit indicates the
> > bandgap has stabilized.
> >
> > With this change,
On Wed, 28 Oct 2020 at 14:20, Mihai Carabas wrote:
>
> From: Peng Hao
>
> Add pvpanic new type "TYPE_PVPANIC_PCI".
>
> Signed-off-by: Peng Hao
> Signed-off-by: Mihai Carabas
> diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h
> index 0a59a06..ce68c90 100644
> --- a/include/hw/pci/pci.h
On 13/12/20 21:51, Philippe Mathieu-Daudé wrote:
Sort .inc files along with the extension including them.
Signed-off-by: Philippe Mathieu-Daudé
---
scripts/git.orderfile | 3 +++
1 file changed, 3 insertions(+)
diff --git a/scripts/git.orderfile b/scripts/git.orderfile
index
On Sat, 12 Dec 2020 00:24:25 +0100
Paolo Bonzini wrote:
> On 07/12/20 17:43, Igor Mammedov wrote:
> >> mc->default_ram_size = 0;
> >> -mc->default_ram_id = "ram";
> >> +mc->default_ram_id = NULL;
> > probably that will break:
> >
> > QEMU -m X -M none
>
> No, it works.
The 'ch' will be NULL in the following stack:
send_notify_iov()->fuse_send_msg()->virtio_send_msg(), and
this may lead to NULL pointer dereferenced in virtio_send_msg().
But send_notify_iov() was never called, so remove the useless code
about send_notify_iov() to fix this problem.
Signed-off-by:
On Sat, Dec 12, 2020 at 12:15:33AM +, Peter Maydell wrote:
> Switch the bamboo board to directly creating and configuring the UIC,
> rather than doing it via the old ppcuic_init() helper function.
>
> Signed-off-by: Peter Maydell
Applied to ppc-for-6.0.
> ---
> hw/ppc/ppc440_bamboo.c | 38
On Wed, 28 Oct 2020 at 14:20, Mihai Carabas wrote:
>
> From: Philippe Mathieu-Daudé
>
> To ease the MMIO device addition in the next patch, rename:
I guess this should say "PCI device" now...
> - ISA_PVPANIC_DEVICE -> PVPANIC_ISA_DEVICE.
> - PVPanicState -> PVPanicISAState.
> - TYPE_PVPANIC ->
On Fri, 11 Dec 2020 18:31:32 +0100
Thomas Huth wrote:
> We will use this in more spots soon, so it's easier to put this into
> a separate function.
>
> Signed-off-by: Thomas Huth
> ---
> tests/acceptance/machine_s390_ccw_virtio.py | 30 -
> 1 file changed, 17
--[ Original Fuzzing output
./build/qemu-fuzz-i386 --fuzz-target=generic-fuzz-virtio-vga
../fuzz/20201208/crash-da778083c63d2b24d8f7780383b2602a7a156352
qemu-fuzz-i386:
/home/qiuhao/hack/qemu/include/exec/memory_ldst_cached.h.inc:88: void
address_space_stw_le_cached(MemoryRegionCache *,
I push to gitlab anyway to get some CI coverage, so let's make
it my primary tree to avoid workflow duplication.
Signed-off-by: Cornelia Huck
---
MAINTAINERS | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index d48a4e8a8b75..0d559635f0e4
On 11/12/2020 18.17, Philippe Mathieu-Daudé wrote:
> It might be overkill (and frustrating) to rerun all the jobs when
> iterating over a single code unit. As some users are interested
> in only rerunning a specific set of jobs, allow them to use a
> "manual" profile, when jobs are created in the
On 12/14/20 3:37 AM, Huacai Chen wrote:
> Hi, Philippe,
>
> On Mon, Dec 14, 2020 at 7:09 AM Philippe Mathieu-Daudé
> wrote:
>>
>> On 12/13/20 11:17 PM, Philippe Mathieu-Daudé wrote:
>>> On 12/11/20 12:32 PM, Philippe Mathieu-Daudé wrote:
On 12/11/20 3:46 AM, Huacai Chen wrote:
> Hi,
On Sat, Dec 12, 2020 at 12:15:30AM +, Peter Maydell wrote:
> In a following commit we will move the PPC UIC implementation to
> its own file in hw/intc. To prevent checkpatch complaining about that
> code-motion, fix up the minor style issues first.
>
> Signed-off-by: Peter Maydell
Applied
On Wed, 16 Sep 2020 10:51:48 +0100
Stefan Hajnoczi wrote:
> There is currently no way to open(O_RDONLY) and mmap(PROT_READ) when
> creating a memory region from a file. This functionality is needed since
> the underlying host file may not allow writing.
>
> Add a bool readonly argument to
My machine has suddenly started consistently failing 'make check-tcg'
like this, following an Ubuntu update of the gdb package from
"8.1-0ubuntu3.2" to "8.1.1-0ubuntu1":
make[2]: Entering directory
'/home/petmay01/linaro/qemu-for-merges/build/all-linux-static/tests/tcg/aarch64-linux-user'
timeout
On Sat, 12 Dec 2020 08:10:01 +0100
Thomas Huth wrote:
Minor nit: I think that the subject is a bit unwieldy. What about
"tests/acceptance: Test virtio-rng on s390 via /dev/hwrng"
?
> On 11/12/2020 21.30, Wainer dos Santos Moschetta wrote:
> > Hi,
> >
> > On 12/11/20 2:31 PM, Thomas Huth
On 12/12/2020 01.15, Peter Maydell wrote:
> In a following commit we will move the PPC UIC implementation to
> its own file in hw/intc. To prevent checkpatch complaining about that
> code-motion, fix up the minor style issues first.
>
> Signed-off-by: Peter Maydell
> ---
> hw/ppc/ppc4xx_devs.c
Kito Cheng writes:
> Hi Keith:
>
> Thanks for your reply, but it seems like we need some more modification in
> linux-user/riscv/cpu_loop.c to enable that, I guess I should post that in
> mail
> rather than attachment :)
>
> Patch here:
>
> From 2f1eb5825a6dda177d3289106970eab05cb08445 Mon
On Sat, 12 Dec 2020 08:15:13 +0100
Thomas Huth wrote:
> On 11/12/2020 21.10, Willian Rampazzo wrote:
> > On 12/11/20 2:31 PM, Thomas Huth wrote:
> >> Add two more simple tests to check that virtio-rng and virtio-balloon
> >> are at least (very) basically working on s390x.
> >>
> >> Based-on:
On Sun, Dec 13, 2020 at 04:23:23PM +0100, Philippe Mathieu-Daudé wrote:
> I noticed GCC merged your patch,
By the way, the fairly new -mfix-r5900 option (implied with mipsr5900el)
is required for the R5900 hardware short loop erratum[1]. I've made a
simple tool to scan ELF objects for
On 14/12/2020 14.26, Cornelia Huck wrote:
> I push to gitlab anyway to get some CI coverage, so let's make
> it my primary tree to avoid workflow duplication.
>
> Signed-off-by: Cornelia Huck
> ---
> MAINTAINERS | 10 +-
> 1 file changed, 5 insertions(+), 5 deletions(-)
FWIW,
Acked-by:
From: Bin Meng
At present the upstream U-Boot (as of today, v2021.01-rc3) does not
boot on QEMU sabrelite machine.
This fixes several issues to improve emulation fidelity of the i.MX6
sabrelite board. With this series, upstream U-Boot can boot to U-Boot
command shell.
Bin Meng (3):
hw/misc:
From: Bin Meng
Currently when U-Boot boots, it prints "??" for i.MX processor:
CPU: Freescale i.MX?? rev1.0 at 792 MHz
The register that was used to determine the silicon type is
undocumented in the latest IMX6DQRM (Rev. 6, 05/2020), but we
can refer to get_cpu_rev() in
From: Bin Meng
U-Boot expects PMU_MISC0 register bit 7 is set (see init_bandgap()
in arch/arm/mach-imx/mx6/soc.c) during boot. This bit indicates the
bandgap has stabilized.
With this change, the latest upstream U-Boot (v2021.01-rc3) for imx6
sabrelite board (mx6qsabrelite_defconfig), with a
On Mon, 14 Dec 2020 at 09:01, David Gibson wrote:
>
> On Sat, Dec 12, 2020 at 12:15:29AM +, Peter Maydell wrote:
> > This patchseries converts the PPC UIC "Universal Interrupt
> > Controller" to a QOM device. My main reason for doing it is that
> > this fixes a couple of long-standing
On 10/12/20 15:32, Philippe Mathieu-Daudé wrote:
On 12/10/20 2:47 PM, marcandre.lur...@redhat.com wrote:
From: Marc-André Lureau
Since commit efc6c07 ("configure: Add a test for the minimum compiler
version"), QEMU explicitely depends on GCC >= 4.8.
(clang >= 3.4 advertizes itself as GCC >=
On Fri, Dec 11, 2020 at 04:08:25PM +, Daniel P. Berrangé wrote:
> The "XVP" (Xen VNC Proxy) extension defines a mechanism for a VNC client
> to issue power control requests to trigger graceful shutdown, reboot, or
> hard reset.
Looks good. Any other clients are supporting this?
> +
On 14/12/20 12:53, Igor Mammedov wrote:
On Sat, 12 Dec 2020 00:24:25 +0100
Paolo Bonzini wrote:
On 07/12/20 17:43, Igor Mammedov wrote:
mc->default_ram_size = 0;
-mc->default_ram_id = "ram";
+mc->default_ram_id = NULL;
probably that will break:
QEMU -m X -M none
No, it
Hi Thomas,
On 12/14/20 6:44 AM, Thomas Huth wrote:
> On 13/12/2020 22.16, Philippe Mathieu-Daudé wrote:
>> Include the 'ccache' package to speed up compilation.
>>
>> Signed-off-by: Philippe Mathieu-Daudé
>> ---
>> tests/docker/dockerfiles/debian10.docker | 1 +
>> 1 file changed, 1
On Sat, 12 Dec 2020, Peter Maydell wrote:
Currently the PPC UIC ("Universal Interrupt Controller") is implemented
as a non-QOM device in ppc4xx_devs.c. Convert it to a proper QOM device
in hw/intc.
The ppcuic_init() function is retained for the moment with its current
interface; in subsequent
From: Bin Meng
At present, when booting U-Boot on QEMU sabrelite, we see:
Net: Board Net Initialization Failed
No ethernet found.
U-Boot scans PHY at address 4/5/6/7 (see board_eth_init() in the
U-Boot source: board/boundary/nitrogen6x/nitrogen6x.c). On the real
board, the Ethernet PHY
On Mon, 14 Dec 2020 at 00:26, Philippe Mathieu-Daudé wrote:
>
> This is the QEMU equivalent of this Linux commit (but 7 years later):
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=f7025a43a9da2
>
> The MTD subsystem has its own small museum of ancient NANDs
>
Daniel P. Berrangé writes:
> On Fri, Nov 13, 2020 at 07:52:31AM +0100, Markus Armbruster wrote:
>> Commit d2f1d29b95 "migration: add support for a "tls-authz" migration
>> parameter" added MigrationParameters member @tls-authz. Whereas the
>> other members aren't really optional (see commit
On Mon, Nov 23, 2020 at 10:47:32AM +0300, Roman Kagan wrote:
> On Mon, Nov 02, 2020 at 08:37:50AM +0300, Roman Kagan wrote:
> > When the slot is in steady powered-off state and the device is being
> > removed, there's no need to press the attention button. Nor is it
> > mandated by the Standard
Hi,
The issue is in LSC clearing. So, after "link up"(during initialization),
the next LSC event is masked and can't be processed.
Technically, the event should be 'cleared' during ICR read.
On Windows guest, everything works well, mostly because of different
interrupt routines(ICR clears during
On 13/12/20 03:55, Alexander Bulekov wrote:
Hi Daniele,
I think it would be nice to have a separate block for get_option('d_lto').
Unless I missed something, right now --enable-lto --disable-cfi builds
don't actually use lto.
Meson handles b_lto internally, it should work.
Paolo
On 05/12/20 00:06, Daniele Buono wrote:
+option('cfi', type: 'feature', value: 'auto',
+ description: 'Control-Flow Integrity (CFI)')
+option('cfi_debug', type: 'feature', value: 'auto',
+ description: 'Verbose errors in case of CFI violation')
I'm changing these to value:
On 14/12/2020 10.24, Alex Bennée wrote:
>
> 罗勇刚(Yonggang Luo) writes:
>
>> On Mon, Dec 14, 2020 at 2:36 AM Philippe Mathieu-Daudé
>> wrote:
>>>
>>> On Wed, Nov 18, 2020 at 4:11 PM Thomas Huth wrote:
On 18/11/2020 15.07, Alex Bennée wrote:
> These seem to trigger timeouts with some
On Wed, 28 Oct 2020 at 14:23, Mihai Carabas wrote:
>
> From: Peng Hao
>
> Add pvpanic device in arm virt machine config file.
>
> Signed-off-by: Peng Hao
> Signed-off-by: Mihai Carabas
> ---
> default-configs/devices/arm-softmmu.mak | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git
Bin Meng writes:
> From: Bin Meng
>
> At present the upstream U-Boot (as of today, v2021.01-rc3) does not
> boot on QEMU sabrelite machine.
Are there any public build artefacts for u-boot on saberlite that could
be used for an acceptance test?
> This fixes several issues to improve
Bin Meng writes:
> From: Bin Meng
>
> U-Boot expects PMU_MISC0 register bit 7 is set (see init_bandgap()
> in arch/arm/mach-imx/mx6/soc.c) during boot. This bit indicates the
> bandgap has stabilized.
>
> With this change, the latest upstream U-Boot (v2021.01-rc3) for imx6
> sabrelite board
On Fri, 11 Dec 2020 17:05:20 -0500
Eduardo Habkost wrote:
> Every single qdev property setter function manually checks
> dev->realized. We can just check dev->realized inside
> qdev_property_set() instead.
>
> The check is being added as a separate function
> (qdev_prop_allow_set()) because it
On Wed, 16 Sep 2020 10:51:49 +0100
Stefan Hajnoczi wrote:
> Let -object memory-backend-file work on read-only files when the
> readonly=on option is given. This can be used to share the contents of a
> file between multiple guests while preventing them from consuming
> Copy-on-Write memory if
On 11/12/2020 18.17, Philippe Mathieu-Daudé wrote:
> As I am interested in using the runner based on the fedora-i386-cross
> docker image, add a smoke test job to be sure this image is usable,
> and set the JOB_MAINTAINER_NAME/JOB_MAINTAINER_EMAIL variables so
> other developers can contact me in
Signed-off-by: Leif Lindholm
---
v1->v2:
- Correct CCSIDR_EL1 field sizes.
target/arm/cpu.h | 24
1 file changed, 24 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index fadd1a47df..90ba707b64 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@
On Sun, Dec 13, 2020 at 11:56:22PM +0100, Laurent Vivier wrote:
> Le 13/12/2020 à 20:04, Peter Maydell a écrit :
> > On Sun, 13 Dec 2020 at 17:22, Laurent Vivier wrote:
> >>
> >> Le 12/10/2020 à 11:47, Thomas Huth a écrit :
> >>> On 25/08/2020 22.27, Roman Bolshakov wrote:
> QEMU build fails
We are shortly going to have a split rw/rx jit buffer. Depending
on the host, we need to flush the dcache at the rw data pointer and
flush the icache at the rx code pointer.
For now, the two passed pointers are identical, so there is no
effective change in behaviour.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
tcg/tci.c | 60 +++
1 file changed, 34 insertions(+), 26 deletions(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index 262a2b39ce..388c1dbee8 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -163,34 +163,34 @@ static
For darwin, the CTR_EL0 register is not accessible, but there
are system routines that we can use.
For other hosts, copy the single pointer implementation from
libgcc and modify it to support the double pointer interface
we require. This halves the number of cache operations required
when
There is nothing within the translators that ought to be
changing the TranslationBlock data, so make it const.
This does not actually use the read-only copy of the
data structure that exists within the rx region.
Signed-off-by: Richard Henderson
---
include/hw/core/cpu.h | 3 ++-
This produces a small pc-relative displacement within the
generated code to the TB structure that preceeds it.
Signed-off-by: Richard Henderson
---
accel/tcg/cpu-exec.c | 35 ++-
tcg/tcg-op.c | 13 -
2 files changed, 34 insertions(+), 14
There is nothing within the translators that ought to be
changing the TranslationBlock data, so make it const.
This does not actually use the read-only copy of the
data structure that exists within the rx region.
Signed-off-by: Richard Henderson
---
include/exec/gen-icount.h | 4 ++--
Now that all native tcg hosts support splitwx, remove the define.
Replace the one use with a test for CONFIG_TCG_INTERPRETER.
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.h | 1 -
tcg/arm/tcg-target.h | 1 -
tcg/i386/tcg-target.h | 1 -
tcg/mips/tcg-target.h | 1
Signed-off-by: Richard Henderson
---
tcg/arm/tcg-target.h | 2 +-
tcg/arm/tcg-target.c.inc | 37 +
2 files changed, 22 insertions(+), 17 deletions(-)
diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
index 7e04755428..856d6dd4b0 100644
---
On Fri, 11 Dec 2020 17:05:11 -0500
Eduardo Habkost wrote:
> Only softmmu code uses DEFINE_PROP_UUID, and it currently depends
> on error_set_from_qdev_prop_error(). Move it to
> qdev-properties-system.c to get out of our way when refactoring
> the qdev property system.
>
> We can eventually
On 12/8/20 11:54 PM, Richard Henderson wrote:
> On 12/7/20 5:55 PM, Philippe Mathieu-Daudé wrote:
>> Some FPU translation functions / registers can be used by
>> ISA / ASE / extensions out of the big translate.c file.
>>
>> Signed-off-by: Philippe Mathieu-Daudé
>> ---
>>
On Sat, Dec 12, 2020 at 4:15 AM Thomas Huth wrote:
>
> On 11/12/2020 21.10, Willian Rampazzo wrote:
> > On 12/11/20 2:31 PM, Thomas Huth wrote:
> >> Add two more simple tests to check that virtio-rng and virtio-balloon
> >> are at least (very) basically working on s390x.
> >>
> >> Based-on:
gdb_exit() has never needed anything from env and I doubt we are going
to start now.
Signed-off-by: Alex Bennée
---
include/exec/gdbstub.h| 2 +-
bsd-user/syscall.c| 6 +++---
gdbstub.c | 2 +-
linux-user/exit.c | 2 +-
target/arm/arm-semi.c | 2 +-
On Fri 27 Nov 2020 03:44:50 PM CET, Vladimir Sementsov-Ogievskiy wrote:
> Return int status to avoid extra error propagation schemes.
>
> Signed-off-by: Vladimir Sementsov-Ogievskiy
Reviewed-by: Alberto Garcia
Berto
From: Thomas Huth
This check can be done in a much shorter way in meson.build. And while
we're at it, rename the #define to HAVE_BTRFS_H to match the other
HAVE_someheader_H symbols that we already have.
Signed-off-by: Thomas Huth
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard
On Mon, 14 Dec 2020 at 13:37, Peter Maydell wrote:
>
> Disable the run-gdbstub-sha1 test: it provokes an internal error
> assertion failure in Ubuntu gdb 8.1.1-0ubuntu1 (Ubuntu gdb
> 8.1-0ubuntu3.2 was fine) :
>
> timeout 60
> /home/petmay01/linaro/qemu-for-merges/tests/guest-debug/run-test.py
We must change all targets at once, since all must match
the declaration in tcg.c.
Signed-off-by: Richard Henderson
---
include/tcg/tcg.h| 2 +-
tcg/tcg.c| 10 +-
tcg/aarch64/tcg-target.c.inc | 2 +-
tcg/arm/tcg-target.c.inc | 2 +-
Signed-off-by: Richard Henderson
---
tcg/riscv/tcg-target.h | 2 +-
tcg/riscv/tcg-target.c.inc | 41 +-
2 files changed, 24 insertions(+), 19 deletions(-)
diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h
index 785fe37f9b..60b6a1a3fc 100644
Add two helper functions, using a global variable to hold
the displacement. The displacement is currently always 0,
so no change in behaviour.
Begin using the functions in tcg common code only.
Signed-off-by: Richard Henderson
---
accel/tcg/tcg-runtime.h | 2 +-
include/disas/disas.h |
Signed-off-by: Richard Henderson
---
tcg/i386/tcg-target.h | 2 +-
tcg/i386/tcg-target.c.inc | 20 +++-
2 files changed, 12 insertions(+), 10 deletions(-)
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
index 04eefbfb90..2e57e95ac2 100644
---
Now that all native tcg hosts support splitwx,
make this pointer const.
Signed-off-by: Richard Henderson
---
include/tcg/tcg.h| 2 +-
tcg/tcg.c| 2 +-
tcg/aarch64/tcg-target.c.inc | 3 +--
tcg/arm/tcg-target.c.inc | 3 +--
tcg/i386/tcg-target.c.inc| 3 +--
Pass both rx and rw addresses to tb_target_set_jmp_target.
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.h | 2 +-
tcg/arm/tcg-target.h | 2 +-
tcg/i386/tcg-target.h| 6 +++---
tcg/mips/tcg-target.h| 2 +-
tcg/ppc/tcg-target.h | 2 +-
Signed-off-by: Richard Henderson
---
tcg/mips/tcg-target.h | 2 +-
tcg/mips/tcg-target.c.inc | 43 ++-
2 files changed, 25 insertions(+), 20 deletions(-)
diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h
index d6dff897bf..c200ac02ea 100644
---
Alex Bennée writes:
> Keith Packard writes:
>
>> This series adds support for RISC-V Semihosting, version 0.2 as
>> specified here:
>>
>> https://github.com/riscv/riscv-semihosting-spec/releases/tag/0.2
>>
>> This specification references the ARM semihosting release 2.0 as specified
>>
On Fri, 11 Dec 2020 17:05:27 -0500
Eduardo Habkost wrote:
> The function will be moved to common QOM code, as it is not
> specific to TYPE_DEVICE anymore.
>
> Reviewed-by: Stefan Berger
> Signed-off-by: Eduardo Habkost
Reviewed-by: Igor Mammedov
> ---
> Changes v1 -> v2:
> * Rename to
v2: fix build issues and update comments. Also drop the first patch
which is now merged upstream
The two patches introduce a parser for the optional OVMF description
table which is placed just below the reset vector (the format of the
table is described in the patch itself) and also adds a
From: Thomas Huth
This check can be done in a much shorter way in meson.build
Signed-off-by: Thomas Huth
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20201118171052.308191-5-th...@redhat.com>
Signed-off-by: Laurent Vivier
---
configure | 10 --
From: Xinhao Zhang
Fix code style. Don't use '#' flag of printf format ('%#') in
format strings, use '0x' prefix instead
Signed-off-by: Xinhao Zhang
Signed-off-by: Kai Deng
Message-Id: <20201104133709.3326630-1-zhangxinh...@huawei.com>
Signed-off-by: Laurent Vivier
---
hw/xen/xen_pt.c
From: Pan Nengyuan
Missing g_error_free in QEMU_Elf_init() error path. Fix that.
Reported-by: Euler Robot
Signed-off-by: Pan Nengyuan
Reviewed-by: Viktor Prutyanov
Reviewed-by: Li Qiang
Signed-off-by: Chen Qun
Reviewed-by: Thomas Huth
Message-Id:
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