Re: [PATCH 1/7] hw/mips/fuloong2e: Remove define DEBUG_FULOONG2E_INIT

On 12/16/20 3:25 AM, Jiaxun Yang wrote: > Seems useless Indeed, introduced in 051c190bce5 ("MIPS: Initial support of fulong mini pc (machine construction)") but never used. Reviewed-by: Philippe Mathieu-Daudé > Signed-off-by: Jiaxun Yang > --- > hw/mips/fuloong2e.c | 2 -- > 1 file

Re: [RFC v2 09/15] target/riscv: rvb: shift ones

On 12/15/20 8:01 PM, frank.ch...@sifive.com wrote: > +static bool trans_sloi(DisasContext *ctx, arg_sloi *a) > +{ > +REQUIRE_EXT(ctx, RVB); > + > +if (a->shamt >= TARGET_LONG_BITS) { > +return false; > +} As I mentioned vs the previous patch, these checks should be in

Re: [PATCH 3/7] meson: switch minimum meson version to 0.56.0

On Wed, Dec 16, 2020 at 8:24 PM Paolo Bonzini wrote: > Meson 0.56.0 does not need b_staticpic=$pie anymore, and has > stabilized the keyval module. Remove the workaround and use a few > replacements for features deprecated in that release cycle. > > Signed-off-by: Paolo Bonzini > Reviewed-by:

Re: [PATCH 6/7] meson: use dependency to gate block modules

On Wed, Dec 16, 2020 at 8:26 PM Paolo Bonzini wrote: > This will allow converting the dependencies to meson options one by one, > because moving the tests to meson.build will get rid of the symbols > in config-host.mak. > > Signed-off-by: Paolo Bonzini > Reviewed-by: Marc-André Lureau --- >

Re: [PATCH 5/7] meson: use pkg-config method for libudev

On Wed, Dec 16, 2020 at 8:28 PM Paolo Bonzini wrote: > Do not bother asking CMake, this is a pkg-config dependency. > > Signed-off-by: Paolo Bonzini > What was the problem with the default behaviour? Do we need to set pkg-config explicitly on all dependencies? --- > meson.build | 1 + > 1

Re: [PATCH 04/12] qapi/gen: assert that _start_if is not None in _wrap_ifcond

On 12/16/20 3:26 AM, Markus Armbruster wrote: John Snow writes: We already assert this in end_if, but that's opaque to mypy. Do it in _wrap_ifcond instead. Same effect at runtime, but mypy can now infer the type in _wrap_ifcond's body. Signed-off-by: John Snow --- scripts/qapi/gen.py | 2

Re: [PATCH v13 10/19] multi-process: Associate fd of a PCIDevice with its object

Hi On Wed, Dec 16, 2020 at 9:06 PM Jag Raman wrote: > > > > On Dec 16, 2020, at 8:43 AM, Marc-André Lureau < > marcandre.lur...@gmail.com> wrote: > > > > > > > > On Mon, Dec 14, 2020 at 9:15 AM Jagannathan Raman > wrote: > > Associate the file descriptor for a PCIDevice in remote process with

Re: [PATCH v3 01/15] hw/riscv: Expand the is 32-bit check to support more CPUs

On Tue, Dec 15, 2020 at 1:25 PM Richard Henderson wrote: > > On 12/15/20 10:44 AM, Alistair Francis wrote: > > On Tue, Dec 15, 2020 at 1:26 AM Bin Meng wrote: > >> > >> On Tue, Dec 15, 2020 at 4:34 AM Alistair Francis > >> wrote: > >>> > >>> Currently the riscv_is_32_bit() function only

Re: [RFC v2 13/15] target/riscv: rvb: address calculation

On 12/15/20 8:01 PM, frank.ch...@sifive.com wrote: > From: Kito Cheng > > Signed-off-by: Kito Cheng > Signed-off-by: Frank Chang > --- > target/riscv/insn32-64.decode | 3 +++ > target/riscv/insn32.decode | 3 +++ > target/riscv/insn_trans/trans_rvb.c.inc | 23

[PATCH v4 11/16] target/riscv: Specify the XLEN for CPUs

Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Tested-by: Bin Meng Reviewed-by: Richard Henderson Reviewed-by: Palmer Dabbelt Acked-by: Palmer Dabbelt --- target/riscv/cpu.c | 33 +++-- 1 file changed, 23 insertions(+), 10 deletions(-) diff --git

[PATCH v4 14/16] target/riscv: csr: Remove compile time XLEN checks

Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Reviewed-by: Palmer Dabbelt Acked-by: Palmer Dabbelt --- target/riscv/cpu_bits.h | 4 +- target/riscv/csr.c | 176 +--- 2 files changed, 92 insertions(+), 88 deletions(-) diff --git

[PATCH v4 06/16] hw/riscv: virt: Remove compile time XLEN checks

Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Tested-by: Bin Meng Reviewed-by: Palmer Dabbelt Acked-by: Palmer Dabbelt --- hw/riscv/virt.c | 32 +--- 1 file changed, 17 insertions(+), 15 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index

Re: [PATCH v2 2/4] block: Avoid processing BDS twice in bdrv_set_aio_context_ignore()

Am 16.12.2020 um 15:55 hat Sergio Lopez geschrieben: > On Wed, Dec 16, 2020 at 01:35:14PM +0100, Kevin Wolf wrote: > > Am 15.12.2020 um 18:23 hat Sergio Lopez geschrieben: > > > On Tue, Dec 15, 2020 at 04:01:19PM +0100, Kevin Wolf wrote: > > > > Am 15.12.2020 um 14:15 hat Sergio Lopez geschrieben:

Re: [PATCH v4 16/16] hw/riscv: Use the CPU to determine if 32-bit

On 12/16/20 12:23 PM, Alistair Francis wrote: > Instead of using string compares to determine if a RISC-V machine is > using 32-bit or 64-bit CPUs we can use the initalised CPUs. This avoids > us having to maintain a list of CPU names to compare against. > > This commit also fixes the name of the

Re: [PATCH v3 4/5] hw/misc: Add a PWM module for NPCM7XX

On Tue, 15 Dec 2020 at 00:13, Hao Wu wrote: > > The PWM module is part of NPCM7XX module. Each NPCM7XX module has two > identical PWM modules. Each module contains 4 PWM entries. Each PWM has > two outputs: frequency and duty_cycle. Both are computed using inputs > from software side. > > This

Re: [RFC v2 08/15] target/riscv: rvb: single-bit instructions

On 12/15/20 8:01 PM, frank.ch...@sifive.com wrote: > +static bool gen_shifti(DisasContext *ctx, arg_shift *a, > +void(*func)(TCGv, TCGv, TCGv)) > +{ > +TCGv source1 = tcg_temp_new(); > +TCGv source2 = tcg_temp_new(); > + > +gen_get_gpr(source1, a->rs1); > +

[PULL 04/11] configure: add --without-default-features

By default QEMU enables a lot of features if it can probe and find the support libraries. It also enables a bunch of features by default. This patch adds the ability to build --without-default-features which can be paired with a --without-default-devices for a barely functional build. The main

[PULL 01/11] configure: include moxie-softmmu in deprecated_targets_list

We still build it but there is no point including it in the normal builds as it is ushered out of the door. Fixes: 4258c8e221 ("docs/system/deprecated: Mark the 'moxie' CPU as deprecated") Signed-off-by: Alex Bennée Reviewed-by: Thomas Huth Reviewed-by: Wainer dos Santos Moschetta Message-Id:

[PULL 11/11] tests: update for rename of CentOS8 PowerTools repo

From: Daniel P. Berrangé This was intentionally renamed recently to be all lowercase: https://bugs.centos.org/view.php?id=17920 https://wiki.centos.org/Manuals/ReleaseNotes/CentOS8.2011#Yum_repo_file_and_repoid_changes Signed-off-by: Daniel P. Berrangé Reviewed-by: Willian Rampazzo

Re: CXL support in QEMU

On 16/12/2020 17.03, Ben Widawsky wrote: > On 20-12-16 13:42:51, Jonathan Cameron wrote: >> On Wed, 16 Dec 2020 10:53:34 +0100 >> Thomas Huth wrote: >> >>> On 16/12/2020 06.05, Prashant V Agarwal wrote: Hi, Is there a way to know the support plans for CXL protocol in QEMU? I see

Re: [RFC v2 11/15] target/riscv: rvb: generalized reverse

On 12/15/20 8:01 PM, frank.ch...@sifive.com wrote: > +target_ulong HELPER(grevw)(target_ulong rs1, target_ulong rs2) > +{ > +return do_grev(rs1, rs2, 32); > +} > + > +#endif > + > diff --git a/target/riscv/helper.h b/target/riscv/helper.h Stray whitespace at the end of the file. checkpatch or

Re: [PATCH v5 00/11] hvf: Implement Apple Silicon Support

On Fri, Dec 11, 2020 at 04:12:49PM +0100, Alexander Graf wrote: > Now that Apple Silicon is widely available, people are obviously excited > to try and run virtualized workloads on them, such as Linux and Windows. > > This patch set implements a fully functional version to get the ball > going on

Re: [PATCH 05/12] qapi/gen: use './builtin' for the built-in module name

On 12/16/20 3:35 AM, Markus Armbruster wrote: John Snow writes: Use this in preference to 'None', which helps remove some edge cases in the typing. Signed-off-by: John Snow Clearly better. Should've done it this way in commit c2e196a9b4 "qapi: Prepare for system modules other than

[PULL 03/12] hw/rtc/twl92230: Silence warnings about missing fallthrough statements

When compiling with -Werror=implicit-fallthrough, gcc complains about missing fallthrough annotations in this file. Looking at the code, the fallthrough is indeed wanted here, but instead of adding the annotations, it can be done more efficiently by simply calculating the offset with a subtraction

[PULL 05/12] target/i386: silence the compiler warnings in gen_shiftd_rm_T1

From: Chen Qun The current "#ifdef TARGET_X86_64" statement affects the compiler's determination of fall through. When using -Wimplicit-fallthrough in our CFLAGS, the compiler showed warning: target/i386/translate.c: In function ‘gen_shiftd_rm_T1’: target/i386/translate.c:1773:12: warning: this

[PULL 02/12] target/unicore32/translate: Add missing fallthrough annotations

Looking at the way the code is formatted here (there is an empty line after break statements, but none where the break is missing), and the instruction set overview at https://en.wikipedia.org/wiki/Unicore the fallthrough is very likely intended here. So add a fallthrough comment to make the it

[PULL 09/12] target/sparc/win_helper: silence the compiler warnings

From: Chen Qun When using -Wimplicit-fallthrough in our CFLAGS, the compiler showed warning: target/sparc/win_helper.c: In function ‘get_gregset’: target/sparc/win_helper.c:304:9: warning: this statement may fall through [-Wimplicit-fallthrough=] 304 |

[PATCH v4 08/16] hw/riscv: sifive_u: Remove compile time XLEN checks

Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt Acked-by: Palmer Dabbelt --- hw/riscv/sifive_u.c | 55 - 1 file changed, 30 insertions(+), 25 deletions(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index

[PATCH v4 01/16] hw/riscv: Expand the is 32-bit check to support more CPUs

Currently the riscv_is_32_bit() function only supports the generic rv32 CPUs. Extend the function to support the SiFive and LowRISC CPUs as well. Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt Acked-by: Palmer Dabbelt --- hw/riscv/boot.c | 12 +++- 1 file changed, 11

[PATCH v4 09/16] target/riscv: fpu_helper: Match function defs in HELPER macros

Update the function definitions generated in helper.h to match the actual function implementations. Also remove all compile time XLEN checks when building. Signed-off-by: Alistair Francis --- target/riscv/helper.h | 24 target/riscv/fpu_helper.c | 8 2

Re: [RFC v2 15/15] target/riscv: rvb: support and turn on B-extension from command line

On 12/16/20 3:14 AM, Kito Cheng wrote: > Hi Alistair, Frank: > > Should we add the bext_spec option like Vector-ext? I would suggest > adding one to align the behavior between V and B. > But I have no strong opinion for this. > I don't think there's any point in that. The experimental

Re: [PULL 00/11] testing and configure updates

Alex Bennée writes: > The following changes since commit af3f37319cb1e1ca0c42842ecdbd1bcfc64a4b6f: > > Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' > into staging (2020-12-15 21:24:31 +) > > are available in the Git repository at: > >

[PATCH v4 15/16] target/riscv: cpu: Set XLEN independently from target

Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Tested-by: Bin Meng Reviewed-by: Palmer Dabbelt Acked-by: Palmer Dabbelt --- target/riscv/cpu.c | 25 - 1 file changed, 16 insertions(+), 9 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index

Re: [PATCH v2 05/12] target/mips/mips-defs: Use ISA_MIPS32R3 definition to check Release 3

On 12/16/20 10:27 AM, Philippe Mathieu-Daudé wrote: > Use the single ISA_MIPS32R3 definition to check if the Release 3 > ISA is supported, whether the CPU support 32/64-bit. > > For now we keep '32' in the definition name, we will rename it > as ISA_MIPS_R3 in few commits. > > Signed-off-by:

Re: [PATCH v2 07/12] target/mips/mips-defs: Use ISA_MIPS32R6 definition to check Release 6

On 12/16/20 10:27 AM, Philippe Mathieu-Daudé wrote: > Use the single ISA_MIPS32R6 definition to check if the Release 6 > ISA is supported, whether the CPU support 32/64-bit. > > For now we keep '32' in the definition name, we will rename it > as ISA_MIPS_R6 in few commits. > > Signed-off-by:

Re: [PATCH v2 01/12] target/mips/mips-defs: Reorder CPU_MIPS5 definition

On 12/16/20 10:27 AM, Philippe Mathieu-Daudé wrote: > Move CPU_MIPS5 after CPU_MIPS4 :) > > Reviewed-by: Jiaxun Yang > Signed-off-by: Philippe Mathieu-Daudé > --- > target/mips/mips-defs.h | 3 +-- > 1 file changed, 1 insertion(+), 2 deletions(-) Reviewed-by: Richard Henderson r~

Re: [PATCH v2 11/12] target/mips/mips-defs: Rename ISA_MIPS32R5 as ISA_MIPS_R5

On 12/16/20 10:27 AM, Philippe Mathieu-Daudé wrote: > The MIPS ISA release 5 is common to 32/64-bit CPUs. > > To avoid holes in the insn_flags type, update the > definition with the next available bit. > > Signed-off-by: Philippe Mathieu-Daudé > --- > target/mips/mips-defs.h | 4 ++-- >

[PATCH v2 12/12] target/mips/mips-defs: Rename ISA_MIPS32R6 as ISA_MIPS_R6

The MIPS ISA release 6 is common to 32/64-bit CPUs. To avoid holes in the insn_flags type, update the definition with the next available bit. Signed-off-by: Philippe Mathieu-Daudé --- target/mips/internal.h | 4 +- target/mips/mips-defs.h| 4 +- linux-user/elfload.c | 2 +-

[PULL 00/11] testing and configure updates

The following changes since commit af3f37319cb1e1ca0c42842ecdbd1bcfc64a4b6f: Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into staging (2020-12-15 21:24:31 +) are available in the Git repository at: https://github.com/stsquad/qemu.git

Re: [PATCH 1/2] test-char: Destroy chardev correctly at char_file_test_internal()

Eduardo Habkost writes: > commit 1e419ee68fa5 ("chardev: generate an internal id when none > given") changed the reference ownership semantics of > qemu_chardev_new(NULL, ...): now all chardevs created using > qemu_chardev_new() are added to the /chardevs QOM container, and > the caller does

Re: [PATCH 6/7] hw/mips/fuloong2e: Correct cpuclock env

On 12/16/20 3:31 AM, Jiaxun Yang wrote: > It should be 53308. > See clock_set_hz. Missed in 3ca7639ff00 ("hw/mips/fuloong2e: Set CPU frequency to 533 MHz"). > > Signed-off-by: Jiaxun Yang > --- > hw/mips/fuloong2e.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git

Re: [PATCH 2/2] qom: Assert that objects being destroyed have no parent

Eduardo Habkost writes: > QOM reference counting bugs are often hard to detect, but there's > one kind of bug that's easier: if we are freeing an object but is > still attached to a parent, it means the reference count is wrong > (because the parent always hold a reference to their children).

Re: [PATCH v13 10/19] multi-process: Associate fd of a PCIDevice with its object

> On Dec 16, 2020, at 8:43 AM, Marc-André Lureau > wrote: > > > > On Mon, Dec 14, 2020 at 9:15 AM Jagannathan Raman > wrote: > Associate the file descriptor for a PCIDevice in remote process with > DeviceState object. > > Signed-off-by: Elena Ufimtseva > Signed-off-by: John G Johnson

Re: [PATCH v3 0/4] target/s390x: Improve carry computation

On Mon, 14 Dec 2020 16:13:52 -0600 Richard Henderson wrote: > While testing the float128_muladd changes for s390x host, > emulating under x86_64 of course, I noticed that the code > we generate for strings of ALCGR and SLBGR is pretty awful. > > I realized that we were missing a trick: the

[PULL 06/12] hw/intc/arm_gicv3_kvm: silence the compiler warnings

From: Chen Qun When using -Wimplicit-fallthrough in our CFLAGS, the compiler showed warning: hw/intc/arm_gicv3_kvm.c: In function ‘kvm_arm_gicv3_put’: hw/intc/arm_gicv3_kvm.c:484:13: warning: this statement may fall through [-Wimplicit-fallthrough=] kvm_gicc_access(s,

[PULL 11/12] tests/fp: Do not emit implicit-fallthrough warnings in the softfloat tests

The softfloat tests are external repositories, so we do not care about implicit fallthrough warnings in this code. Signed-off-by: Thomas Huth Reviewed-by: Richard Henderson Reviewed-by: Chen Qun Message-Id: <20201211152426.350966-12-th...@redhat.com> Signed-off-by: Thomas Huth ---

[PULL 10/12] tcg/optimize: Add fallthrough annotations

To be able to compile this file with -Werror=implicit-fallthrough, we need to add some fallthrough annotations to the case statements that might fall through. Unfortunately, the typical "/* fallthrough */" comments do not work here as expected since some case labels are wrapped in macros and the

Re: [PATCH v2 05/11] qapi/introspect.py: add preliminary type hint annotations

On Wed, Dec 16, 2020 at 08:51:10AM +0100, Markus Armbruster wrote: [...] > You guys clearly struggled with the tree data structure. Documentation > would have helped[*]. Since you're going to replace it (PATCH 09), > adding it now makes little sense. > > *My* struggle is with the type

Re: [PATCH v3 1/3] docs: generate qemu-storage-daemon-qmp-ref(7) man page

Am 16.12.2020 um 17:21 hat Stefan Hajnoczi geschrieben: > On Tue, Dec 15, 2020 at 05:11:06PM +0100, Kevin Wolf wrote: > > > diff --git a/docs/interop/qemu-storage-daemon-qmp-ref.rst > > > b/docs/interop/qemu-storage-daemon-qmp-ref.rst > > > new file mode 100644 > > > index 00..caf9dad23a

Re: [PATCH V18 3/5] hw/mips: Add Loongson-3 boot parameter helpers

Hi Huacai, On 12/15/20 1:57 PM, Huacai Chen wrote: > Preparing to add Loongson-3 machine support, add Loongson-3's LEFI (a > UEFI-like interface for BIOS-Kernel boot parameters) helpers first. > > Reviewed-by: Philippe Mathieu-Daudé > Signed-off-by: Huacai Chen > Co-developed-by: Jiaxun Yang

[PATCH v4 03/16] riscv: spike: Remove target macro conditionals

Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Reviewed-by: Palmer Dabbelt Acked-by: Palmer Dabbelt --- include/hw/riscv/spike.h | 6 -- hw/riscv/spike.c | 2 +- 2 files changed, 1 insertion(+), 7 deletions(-) diff --git a/include/hw/riscv/spike.h

[PATCH v4 00/16] RISC-V: Start to remove xlen preprocess

The RISC-V QEMU port currently has lot of preprocessor directives that check if we are targetting a 32-bit or 64-bit CPU. This means that the 64-bit RISC-V target can not run 32-bit CPUs. This is different to most other QEMU architectures and doesn't allow us to mix xlens (such as when running

[PATCH v4 07/16] hw/riscv: spike: Remove compile time XLEN checks

Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Reviewed-by: Palmer Dabbelt Acked-by: Palmer Dabbelt --- hw/riscv/spike.c | 45 - 1 file changed, 24 insertions(+), 21 deletions(-) diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index

Re: [RFC v2 14/15] target/riscv: rvb: add/sub with postfix zero-extend

On 12/15/20 8:01 PM, frank.ch...@sifive.com wrote: > From: Kito Cheng > > Signed-off-by: Kito Cheng > Signed-off-by: Frank Chang > --- > target/riscv/insn32-64.decode | 3 +++ > target/riscv/insn_trans/trans_rvb.c.inc | 22 ++ > target/riscv/translate.c

[PATCH v4 12/16] target/riscv: cpu: Remove compile time XLEN checks

Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Reviewed-by: Richard Henderson Reviewed-by: Palmer Dabbelt Acked-by: Palmer Dabbelt --- target/riscv/cpu.c | 19 ++- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c

Re: [PATCH 11/12] qapi/schema: Name the builtin module "" instead of None

On 12/16/20 5:42 AM, Markus Armbruster wrote: John Snow writes: Instead of using None as the built-in module filename, use an empty string instead. PATCH 05's changes the module name of the special system module for built-in stuff from None to './builtin'. The other system modules are

Re: [PATCH v2 09/12] target/mips/mips-defs: Rename ISA_MIPS32R2 as ISA_MIPS_R2

On 12/16/20 10:27 AM, Philippe Mathieu-Daudé wrote: > The MIPS ISA release 2 is common to 32/64-bit CPUs. > > Signed-off-by: Philippe Mathieu-Daudé > --- > target/mips/internal.h | 2 +- > target/mips/mips-defs.h| 6 +- > linux-user/mips/cpu_loop.c | 2 +- >

Re: [PATCH v2 06/12] target/mips/mips-defs: Use ISA_MIPS32R5 definition to check Release 5

On 12/16/20 10:27 AM, Philippe Mathieu-Daudé wrote: > Use the single ISA_MIPS32R5 definition to check if the Release 5 > ISA is supported, whether the CPU support 32/64-bit. > > For now we keep '32' in the definition name, we will rename it > as ISA_MIPS_R5 in few commits. > > Signed-off-by:

Re: [PATCH v2 08/12] target/mips/mips-defs: Rename ISA_MIPS32 as ISA_MIPS_R1

On 12/16/20 10:27 AM, Philippe Mathieu-Daudé wrote: > The MIPS ISA release '1' is common to 32/64-bit CPUs. > > Signed-off-by: Philippe Mathieu-Daudé > --- > target/mips/internal.h | 2 +- > target/mips/mips-defs.h | 4 +-- > target/mips/translate.c | 54

[PATCH 03/11] target/mips/mips-defs: Use ISA_MIPS32R2 definition to check Release 2

Use the single ISA_MIPS32R2 definition to check if the Release 2 ISA is supported, whether the CPU support 32/64-bit. For now we keep '32' in the definition name, we will rename it as ISA_MIPS_R2 in few commits. Signed-off-by: Philippe Mathieu-Daudé --- target/mips/mips-defs.h| 3 +--

[PATCH v3 06/10] vfio: Support for RamDiscardMgr in the vIOMMU case

vIOMMU support works already with RamDiscardMgr as long as guests only map populated memory. Both, populated and discarded memory is mapped into _space_memory, where vfio_get_xlat_addr() will find that memory, to create the vfio mapping. Sane guests will never map discarded memory (e.g.,

Re: [PATCH 3/3] trace: recommend "log" backend for getting started with tracing

On Fri, Dec 11, 2020 at 03:06:17PM +, Peter Maydell wrote: > On Wed, 9 Dec 2020 at 17:42, Stefan Hajnoczi wrote: > > > > The "simple" backend is actually more complicated to use than the "log" > > backend. Update the quickstart documentation to feature the "log" > > backend instead of the

Re: [PATCH v3 0/4] target/s390x: Improve carry computation

On 14.12.20 23:13, Richard Henderson wrote: > While testing the float128_muladd changes for s390x host, > emulating under x86_64 of course, I noticed that the code > we generate for strings of ALCGR and SLBGR is pretty awful. > > I realized that we were missing a trick: the output cc is > based

[Bug 1908416] [NEW] qemu-system-aarch64 can't run Windows 10 for ARM version 2004

Public bug reported: Problem: qemu-system-aarch64 can't run Windows 10 for ARM version 2004 (20H2) or newer Host OS: Windows 10 x64 version 20H2 CPU: Intel Pentium Dual-core T4300 (no vt-x) QEMU : QEMU version 5.1.0 from qemu.org cmdline: qemu-system-aarch64.exe -M virt -cpu cortex-a72

[PATCH 7/7] meson: cleanup Kconfig.host handling

Build the array of command line arguments coming from config_host once for all targets. Add all accelerators to accel/Kconfig so that the command line arguments for accelerators can be computed easily in the existing "foreach sym: accelerators" loop. Signed-off-by: Paolo Bonzini ---

Re: [PATCH 1/3] remove TCG includes from common code

On 12/16/20 2:55 PM, Paolo Bonzini wrote: > Enable removing tcg/$tcg_arch from the include path when TCG is disabled. > Move translate-all.h to include/exec, since stubs exist for the functions > defined therein. > > Signed-off-by: Paolo Bonzini > --- > accel/stubs/tcg-stub.c

Re: [RFC PATCH 0/9] Support for Virtio-fs daemon crash reconnection

Hi On Tue, Dec 15, 2020 at 8:22 PM Jiachen Zhang < zhangjiachen.jay...@bytedance.com> wrote: > Hi, all > > We implement virtio-fs crash reconnection in this patchset. The crash > reconnection of virtiofsd here is completely transparent to guest, no > remount in guest is needed, even the inflight

[PATCH v2 0/3] trace: convert docs to rST and feature "log" backend in quickstart

v2: * Simplify quickstart for the "log" trace backend that is enabled by default [Peter] * Don't show ./configure --enable-trace-backends=log example since it's built by default (changed to --enable-trace-backends=simple,dtrace) [Peter] Convert tracing.txt to rST and add it to the

[PATCH v2 3/3] trace: recommend "log" backend for getting started with tracing

The "simple" backend is actually more complicated to use than the "log" backend. Update the quickstart documentation to feature the "log" backend instead of the "simple" backend. Suggested-by: Peter Maydell Signed-off-by: Stefan Hajnoczi --- docs/devel/tracing.rst | 35

[PATCH 4/7] meson: fix detection of curses with pkgconfig

Signed-off-by: Paolo Bonzini --- meson.build | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/meson.build b/meson.build index 39fc9b7143..ab622ae8bd 100644 --- a/meson.build +++ b/meson.build @@ -500,16 +500,16 @@ if have_system and not get_option('curses').disabled()

[PULL 02/11] gitlab: include aarch64-softmmu and ppc64-softmmu cross-system-build

Otherwise we miss coverage of KVM support in the cross build. To balance it out add arm-softmmu (no kvm, subset of aarch64), cris-softmmu and ppc-softmmu to the exclude list which do get coverage elsewhere. Signed-off-by: Alex Bennée Reviewed-by: Thomas Huth Reviewed-by: Wainer dos Santos

[PULL 06/11] gitlab: move --without-default-devices build from Travis

Signed-off-by: Alex Bennée Reviewed-by: Thomas Huth Reviewed-by: Wainer dos Santos Moschetta Message-Id: <20201210190417.31673-7-alex.ben...@linaro.org> diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index b3bcaacf7b..2134453717 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -514,6 +514,13

[PATCH v2 11/12] target/mips/mips-defs: Rename ISA_MIPS32R5 as ISA_MIPS_R5

The MIPS ISA release 5 is common to 32/64-bit CPUs. To avoid holes in the insn_flags type, update the definition with the next available bit. Signed-off-by: Philippe Mathieu-Daudé --- target/mips/mips-defs.h | 4 ++-- target/mips/translate.c | 2 +- 2 files changed, 3 insertions(+), 3

[PULL 03/11] configure: move gettext detection to meson.build

This will allow meson to honour -Dauto_features=disabled later. Suggested-by: Paolo Bonzini Signed-off-by: Alex Bennée Acked-by: Paolo Bonzini Message-Id: <20201210190417.31673-4-alex.ben...@linaro.org> diff --git a/configure b/configure index d37ec98aa9..f9b1e4fbb0 100755 --- a/configure +++

Re: [PATCH 2/7] meson: update submodule to 0.56.0

On Wed, Dec 16, 2020 at 8:25 PM Paolo Bonzini wrote: > Signed-off-by: Paolo Bonzini > Reviewed-by: Marc-André Lureau --- > configure | 2 +- > meson | 2 +- > 2 files changed, 2 insertions(+), 2 deletions(-) > > diff --git a/configure b/configure > index 6317964997..8d12b715e3 100755 >

[PULL 08/11] tests/tcg: build tests with -Werror

Hopefully this will guard against sloppy code getting into our tests. Suggested-by: Paolo Bonzini Signed-off-by: Alex Bennée Reviewed-by: Thomas Huth Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20201210190417.31673-9-alex.ben...@linaro.org> diff --git a/tests/tcg/Makefile.target

[PULL 07/11] gitlab: add --without-default-features build

Signed-off-by: Alex Bennée Reviewed-by: Thomas Huth Message-Id: <20201210190417.31673-8-alex.ben...@linaro.org> diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 2134453717..229545bc03 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -521,6 +521,13 @@ build-without-default-devices:

Re: [PATCH v2 14/36] block: inline bdrv_child_*() permission functions calls

On Fri 27 Nov 2020 03:45:00 PM CET, Vladimir Sementsov-Ogievskiy wrote: > Each of them has only one caller. Open-coding simplifies further > pemission-update system changes. > > Signed-off-by: Vladimir Sementsov-Ogievskiy Reviewed-by: Alberto Garcia Berto

[PULL 08/12] target/sparc/translate: silence the compiler warnings

From: Chen Qun When using -Wimplicit-fallthrough in our CFLAGS, the compiler showed warning: target/sparc/translate.c: In function ‘gen_st_asi’: target/sparc/translate.c:2320:12: warning: this statement may fall through [-Wimplicit-fallthrough=] 2320 | if (!(dc->def->features &

[PATCH] tcg: Add tcg_gen_bswap_tl alias

The alias is intended to indicate that the bswap is for the entire target_long. This should avoid ifdefs on some targets. Signed-off-by: Richard Henderson --- include/tcg/tcg-op.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h index

[PATCH v4 05/16] hw/riscv: boot: Remove compile time XLEN checks

Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Tested-by: Bin Meng Reviewed-by: Palmer Dabbelt Acked-by: Palmer Dabbelt --- include/hw/riscv/boot.h | 8 +++--- hw/riscv/boot.c | 55 ++--- hw/riscv/sifive_u.c | 2 +- hw/riscv/spike.c

[PATCH v4 10/16] target/riscv: Add a riscv_cpu_is_32bit() helper function

Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Tested-by: Bin Meng Reviewed-by: Palmer Dabbelt Acked-by: Palmer Dabbelt --- target/riscv/cpu.h | 2 ++ target/riscv/cpu.c | 9 + 2 files changed, 11 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index

[PATCH v4 02/16] target/riscv: Add a TYPE_RISCV_CPU_BASE CPU

Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Tested-by: Bin Meng Reviewed-by: Palmer Dabbelt Acked-by: Palmer Dabbelt --- target/riscv/cpu.h | 6 ++ 1 file changed, 6 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index c0a326c843..9c064f3094 100644 ---

[PATCH v4 13/16] target/riscv: cpu_helper: Remove compile time XLEN checks

Signed-off-by: Alistair Francis Reviewed-by: Richard Henderson Reviewed-by: Palmer Dabbelt Acked-by: Palmer Dabbelt --- target/riscv/cpu_helper.c | 12 +++- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index

[PATCH v4 04/16] riscv: virt: Remove target macro conditionals

Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Tested-by: Bin Meng Reviewed-by: Palmer Dabbelt Acked-by: Palmer Dabbelt --- include/hw/riscv/virt.h | 6 -- hw/riscv/virt.c | 2 +- 2 files changed, 1 insertion(+), 7 deletions(-) diff --git a/include/hw/riscv/virt.h

[PATCH v4 16/16] hw/riscv: Use the CPU to determine if 32-bit

Instead of using string compares to determine if a RISC-V machine is using 32-bit or 64-bit CPUs we can use the initalised CPUs. This avoids us having to maintain a list of CPU names to compare against. This commit also fixes the name of the function to match the riscv_cpu_is_32bit() function.

Re: [PATCH 08/12] qapi/schema: make QAPISourceInfo mandatory

On 12/16/20 5:18 AM, Markus Armbruster wrote: John Snow writes: -- events.py had an info to route, was it by choice that it wasn't before? See below. I figure this is intentionally below the -- line, but ... Signed-off-by: John Snow ... this should be above it. Script failure. Or

Re: [PULL 00/11] testing and configure updates

On Wed, 16 Dec 2020 at 18:24, Alex Bennée wrote: > > > Alex Bennée writes: > > > The following changes since commit af3f37319cb1e1ca0c42842ecdbd1bcfc64a4b6f: > > > > Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' > > into staging (2020-12-15 21:24:31 +) > > > >

Re: [PATCH 0/5] i386: simplify Hyper-V enlightenments enablement

On Thu, Nov 19, 2020 at 11:32:16AM +0100, Vitaly Kuznetsov wrote: > This series is a part of the previously sent "[PATCH RFC v3 00/23] i386: > KVM: expand Hyper-V features early": > https://lists.gnu.org/archive/html/qemu-devel/2020-10/msg02443.html > > We're not ready to merge the full patch set

[PATCH v2 06/12] target/mips/mips-defs: Use ISA_MIPS32R5 definition to check Release 5

Use the single ISA_MIPS32R5 definition to check if the Release 5 ISA is supported, whether the CPU support 32/64-bit. For now we keep '32' in the definition name, we will rename it as ISA_MIPS_R5 in few commits. Signed-off-by: Philippe Mathieu-Daudé --- target/mips/mips-defs.h | 3 +-- 1 file

[PATCH v2 10/12] target/mips/mips-defs: Rename ISA_MIPS32R3 as ISA_MIPS_R3

The MIPS ISA release 3 is common to 32/64-bit CPUs. To avoid holes in the insn_flags type, update the definition with the next available bit. Signed-off-by: Philippe Mathieu-Daudé --- target/mips/mips-defs.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git

[PULL 10/11] tests/docker: Remove the remainders of debian9 containers from the Makefile

From: Thomas Huth The Debian 9 containers have been removed a while ago, so we can delete the corresponding entries in the Makefile, too. Fixes: e3755276d1 ("tests/docker: Remove old Debian 9 containers") Signed-off-by: Thomas Huth Reviewed-by: Wainer dos Santos Moschetta Message-Id:

[PULL 09/11] gitlab-CI: Test 32-bit builds with the fedora-i386-cross container

From: Thomas Huth After adding some missing packages, it's possible to check 32-bit builds and tests with the fedora-i386-cross container in the gitlab-CI, too. Unfortunately, the code in subprojects/ ignores the --extra-cflags (on purpose), so the vhost-user part has to be disabled for this.

Re: [PATCH 4/7] meson: fix detection of curses with pkgconfig

On Wed, Dec 16, 2020 at 8:22 PM Paolo Bonzini wrote: > Signed-off-by: Paolo Bonzini > Reviewed-by: Marc-André Lureau --- > meson.build | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/meson.build b/meson.build > index 39fc9b7143..ab622ae8bd 100644 > ---

[PULL 05/11] python: add __repr__ to ConsoleSocket to aid debugging

While attempting to debug some console weirdness I thought it would be worth making it easier to see what it had inside. Signed-off-by: Alex Bennée Reviewed-by: John Snow Reviewed-by: Willian Rampazzo Message-Id: <20201210190417.31673-6-alex.ben...@linaro.org> diff --git

Re: [PATCH] tests: update for rename of CentOS8 PowerTools repo

On 16/12/2020 16:10, Peter Maydell wrote: On Wed, 16 Dec 2020 at 14:21, Daniel P. Berrangé wrote: This was intentionally renamed recently to be all lowercase: https://bugs.centos.org/view.php?id=17920 https://wiki.centos.org/Manuals/ReleaseNotes/CentOS8.2011#Yum_repo_file_and_repoid_changes

Re: [PATCH 03/12] qapi/main: handle theoretical None-return from re.match()

On 12/16/20 3:23 AM, Markus Armbruster wrote: John Snow writes: Mypy cannot understand that this match can never be None, so help it along. Signed-off-by: John Snow --- scripts/qapi/main.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/scripts/qapi/main.py

[PULL 00/12] Compile QEMU with -Wimplicit-fallthrough

Hi! The following changes since commit af3f37319cb1e1ca0c42842ecdbd1bcfc64a4b6f: Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into staging (2020-12-15 21:24:31 +) are available in the Git repository at: https://gitlab.com/huth/qemu.git

[PULL 01/12] disas/libvixl: Fix fall-through annotation for GCC >= 7

For compiling with -Wimplicit-fallthrough we need to fix the fallthrough annotations in the libvixl code. This is based on the following upstream vixl commit by Martyn Capewell: https://git.linaro.org/arm/vixl.git/commit/?id=de326f850f736c3a337 "GCC 7 enables switch/case fallthrough checking,

Re: [PATCH 7/7] meson: cleanup Kconfig.host handling

Hi On Wed, Dec 16, 2020 at 8:26 PM Paolo Bonzini wrote: > Build the array of command line arguments coming from config_host > once for all targets. Add all accelerators to accel/Kconfig so > that the command line arguments for accelerators can be computed > easily in the existing "foreach sym:

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