Am 23.01.21 um 10:41 schrieb Philippe Mathieu-Daudé:
Restrict tci_write_reg16() to 64-bit hosts to fix on 32-bit ones:
[520/1115] Compiling C object libqemu-arm-linux-user.fa.p/tcg_tci.c.o
FAILED: libqemu-arm-linux-user.fa.p/tcg_tci.c.o
tcg/tci.c:132:1: error: 'tci_write_reg16'
From: Bin Meng
This adds the missing SPI support to the `sifive_u` machine in the QEMU
mainline. With this series, upstream U-Boot for the SiFive HiFive Unleashed
board can boot on QEMU `sifive_u` out of the box. This allows users to
develop and test the recommended RISC-V boot flow with a real
From: Bin Meng
Per the "Physical Layer Specification Version 8.00" chapter 7.5.1,
"Command/Response", there is a minimum 8 clock cycles (Ncr) before
the card response shows up on the data out line. However current
implementation jumps directly to the sending response state after
all 6 bytes
From: Bin Meng
This fixes the wrong command index for STOP_TRANSMISSION, the
required command to interrupt the multiple block read command,
in the old codes. It should be CMD12 (0x4c), not CMD13 (0x4d).
Fixes: 775616c3ae8c ("Partial SD card SPI mode support")
Signed-off-by: Bin Meng
---
From: Bin Meng
The single block read (CMD17) codes are the same as the multiple
block read (CMD18). Merge them into one. The same applies to single
block write (CMD24) and multiple block write (CMD25).
Signed-off-by: Bin Meng
Acked-by: Alistair Francis
---
(no changes since v1)
hw/sd/sd.c
From: Bin Meng
All other peripherals' IRQs are in the format of decimal value.
Change SIFIVE_U_GEM_IRQ to be consistent.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
---
(no changes since v1)
include/hw/riscv/sifive_u.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
Upstream patch:
-> https://lists.nongnu.org/archive/html/qemu-devel/2021-01/msg05986.html
** Information type changed from Private Security to Public Security
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
move the call to qemu_init_vcpu inside cpu_common_realizefn,
so it does not need to be done explicitly in each target cpu.
Despite this, the way cpu realize is done continues to be not ideal;
ideally the cpu_list_add would be done in common_cpu,
and in this case we could avoid even more
Signed-off-by: Paolo Bonzini
---
qemu.nsi | 42 --
1 file changed, 4 insertions(+), 38 deletions(-)
diff --git a/qemu.nsi b/qemu.nsi
index 1a0112265b..c3df8c9d3b 100644
--- a/qemu.nsi
+++ b/qemu.nsi
@@ -35,11 +35,6 @@
!define OUTFILE "qemu-setup.exe"
From: Marc-André Lureau
As we want subprojects to share those arguments
Signed-off-by: Marc-André Lureau
Acked-by: Paolo Bonzini
Message-Id: <20210114125605.1227742-3-marcandre.lur...@redhat.com>
Signed-off-by: Paolo Bonzini
---
meson.build | 16
1 file changed, 8
From: Philippe Mathieu-Daudé
When building with GCC 10.2 configured with --extra-cflags=-Os, we get:
softmmu/physmem.c: In function 'address_space_translate_for_iotlb':
softmmu/physmem.c:643:26: error: 'notifier' may be used uninitialized in this
function [-Werror=maybe-uninitialized]
From: Marc-André Lureau
This help fixing static compilation issues.
Signed-off-by: Marc-André Lureau
Acked-by: Paolo Bonzini
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20210114125605.1227742-4-marcandre.lur...@redhat.com>
Signed-off-by: Paolo Bonzini
---
From: Marc-André Lureau
Since meson switch and commit feabc71dfa58 ("configure: do not include
dependency flags in QEMU_CFLAGS and LIBS"), LIBS is unused.
Signed-off-by: Marc-André Lureau
Acked-by: Paolo Bonzini
Message-Id: <20210114125605.1227742-2-marcandre.lur...@redhat.com>
Signed-off-by:
From: Philippe Mathieu-Daudé
have_virtfs_proxy_helper is used from docs/meson.build, and can be
not declared when including it before fsdev/meson.build. This fixes:
../docs/meson.build:54:2: ERROR: Unknown variable "have_virtfs_proxy_helper".
Signed-off-by: Philippe Mathieu-Daudé
Signed-off-by: Paolo Bonzini
Reviewed-by: Gerd Hoffmann
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20210120144235.345983-3-pbonz...@redhat.com>
Signed-off-by: Paolo Bonzini
---
docs/system/deprecated.rst | 5
docs/system/removed-features.rst | 5
monitor/qmp-cmds.c
Restrict tci_write_reg16() to 64-bit hosts to fix on 32-bit ones:
[520/1115] Compiling C object libqemu-arm-linux-user.fa.p/tcg_tci.c.o
FAILED: libqemu-arm-linux-user.fa.p/tcg_tci.c.o
tcg/tci.c:132:1: error: 'tci_write_reg16' defined but not used
[-Werror=unused-function]
From: Bin Meng
This adds the ISSI SPI flash support. The number of dummy cycles in
fast read, fast read dual output and fast read quad output commands
is currently using the default 8. Likewise, the same default value
is used for fast read dual/quad I/O command. Per the datasheet [1],
the number
From: Bin Meng
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
---
(no changes since v1)
docs/system/targets.rst | 19 ---
1 file changed, 12 insertions(+), 7 deletions(-)
diff --git a/docs/system/targets.rst b/docs/system/targets.rst
index 560783644d..564cea9a9b
From: Bin Meng
Per the "Physical Layer Specification Version 8.00" chapter 7.5.2,
"Data Read", there is a minimum 8 clock cycles (Nac) after the card
response and before data block shows up on the data out line. This
applies to both single and multiple block read operations.
Current
From: Eduardo Habkost
Signed-off-by: Eduardo Habkost
[claudio: wrapped in CONFIG_TCG]
Signed-off-by: Claudio Fontana
---
include/hw/core/cpu.h | 20 +++-
accel/tcg/cpu-exec.c | 4 ++--
target/arm/cpu.c | 4 +++-
target/avr/cpu.c | 2 +-
cc->do_interrupt is in theory a TCG callback used in accel/tcg only,
to prepare the emulated architecture to take an interrupt as defined
in the hardware specifications,
but in reality the _do_interrupt style of functions in targets are
also occasionally reused by KVM to prepare the architecture
From: Eduardo Habkost
Signed-off-by: Eduardo Habkost
Signed-off-by: Claudio Fontana
Reviewed-by: Alex Bennée
Reviewed-by: Richard Henderson
---
include/hw/core/cpu.h | 4 ++--
accel/tcg/cpu-exec.c | 4 ++--
target/arm/cpu.c | 2 +-
target/i386/tcg/tcg-cpu.c | 2 +-
move away TCG-only code, make it compile only on TCG.
Signed-off-by: Claudio Fontana
Reviewed-by: Alex Bennée
Reviewed-by: Richard Henderson
[claudio: moved the prototypes from hw/core/cpu.h to exec/cpu-all.h]
---
include/exec/cpu-all.h | 11 +--
include/hw/core/cpu.h | 2 ++
commit 568496c0c0f1 ("cpu: Add callback to check architectural") and
commit 3826121d9298 ("target-arm: Implement checking of fired")
introduced an ARM-specific hack for cpu_check_watchpoint.
Make debug_check_watchpoint optional, and move it to tcg_ops.
Signed-off-by: Claudio Fontana
---
cpu_check_watchpoint, watchpoint_address_matches are TCG-only.
Signed-off-by: Claudio Fontana
---
softmmu/physmem.c | 141 +++---
1 file changed, 72 insertions(+), 69 deletions(-)
diff --git a/softmmu/physmem.c b/softmmu/physmem.c
index
The possible choices for panic, reset and watchdog actions are inconsistent.
"-action panic=poweroff" should be renamed to "-action panic=shutdown"
on the command line. This is because "-action panic=poweroff" and
"-action watchdog=poweroff" have slightly different semantics, the first
does an
From: Yang Weijiang
QEMU option -cpu max(max_features) means "Enables all features supported by
the accelerator in the current host", this looks true for all the features
except guest max physical address width, so add this patch to enable it.
Signed-off-by: Yang Weijiang
Message-Id:
From: Marc-André Lureau
git cherry-diff:
Commits on bacb71f1c3ed5f40e393afd8be81bedfba13a401 branch that is not on
8f43a99191afb47ca3f3c6972f6306209f367ece branch
+ 1021b0dc38d39f1dc95a296fe3e05a24a087cdc6 disable_dns option
+ 0f94ceec752592e4ac632a24e3c64a97dd09bf4c limit vnameserver_addr to
From: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20210121095616.1471869-8-phi...@redhat.com>
Signed-off-by: Paolo Bonzini
---
meson.build | 32 ++--
1 file changed, 18 insertions(+), 14 deletions(-)
diff --git a/meson.build
From: Philippe Mathieu-Daudé
Globally declare in the main meson.build:
- the list of EDK2 targets,
- whether the EDK2 blobs have to be installed.
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20210114174509.2944817-2-phi...@redhat.com>
Signed-off-by: Paolo Bonzini
---
meson.build
Patchew URL:
https://patchew.org/QEMU/20210123143128.1167797-1-pbonz...@redhat.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20210123143128.1167797-1-pbonz...@redhat.com
Subject: [PULL 00/31] Misc patches for
22.01.2021 19:16, Kevin Wolf wrote:
Am 16.01.2021 um 14:44 hat Vladimir Sementsov-Ogievskiy geschrieben:
Hi all!
These series has 3 goals:
- get rid of group file (to forget about rebase and in-list conflicts)
- introduce human-readable names for tests
- rewrite check into python
v7:
From: Bin Meng
This adds the SiFive SPI controller model for the FU540 SoC.
The direct memory-mapped SPI flash mode is unsupported.
Signed-off-by: Bin Meng
---
Changes in v2:
- Log guest error when trying to write reserved registers
- Log guest error when trying to access out-of-bounds
From: Bin Meng
QEMU coding convention prefers spaces over tabs.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
---
Changes in v2:
- Correct the "coding" typo in the commit message
include/hw/sd/sd.h | 42 +-
1 file changed, 21 insertions(+),
From: Bin Meng
commit f6fb1f9b319f ("sdcard: Correct CRC16 offset in sd_function_switch()")
changed the 16-bit CRC to be stored at offset 64. In fact, this CRC
calculation is completely wrong. From the original codes, it wants
to calculate the CRC16 of the first 64 bytes of sd->data[], however
From: Bin Meng
With all these fixes and improvements, there is no way for the
VMStateDescription to keep backward compatibility. We will have
to bump up version ids.
The s->mode check in the post_load() hook is also updated.
Signed-off-by: Bin Meng
---
Changes in v2:
- new patch: bump up
From: Bin Meng
This adds the QSPI0 controller to the SoC, and connects an ISSI
25WP256 flash to it. The generation of corresponding device tree
source fragment is also added.
Since the direct memory-mapped mode is not supported by the SiFive
SPI model, the property does not populate the second
On 1/22/21 9:44 PM, Philippe Mathieu-Daudé wrote:
> Suggested-by: Paolo Bonzini
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> Cc: Richard Henderson
> Cc: Alex Bennée
> Cc: Emilio G. Cota
> ---
> tests/meson.build | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git
Signed-off-by: Claudio Fontana
Reviewed-by: Alex Bennée
Reviewed-by: Richard Henderson
---
include/hw/core/cpu.h | 4 ++--
accel/tcg/cpu-exec.c| 4 ++--
target/alpha/cpu.c | 2 +-
target/arm/cpu.c| 4 ++--
target/arm/cpu_tcg.c|
The following changes since commit fef80ea073c4862bc9eaddb6ddb0ed970b8ad7c4:
Merge remote-tracking branch 'remotes/ericb/tags/pull-nbd-2021-01-20' into
staging (2021-01-21 10:44:28 +)
are available in the Git repository at:
https://gitlab.com/bonzini/qemu.git tags/for-upstream
for you
From: Gan Qixin
When compiling qemu-fuzz-i386 on aarch64 host, clang reported the following
error:
../util/cacheflush.c:38:44: error: value size does not match register size
specified by the constraint and modifier [-Werror,-Wasm-operand-widths]
asm volatile("mrs\t%0, ctr_el0" :
From: Joshua Watt
There are two cases that need to be accounted for when compiling QEMU
for MinGW32:
1) A standalone distribution, where QEMU is self contained and
extracted by the user, such as a user would download from the QEMU
website. In this case, all the QEMU executable files
From: Prasad J Pandit
While processing ATAPI cmd_read/cmd_read_cd commands,
Logical Block Address (LBA) maybe invalid OR closer to the last block,
leading to an OOB access issues. Add range check to avoid it.
Fixes: CVE-2020-29443
Reported-by: Wenxiang Qian
Suggested-by: Paolo Bonzini
Right now, help options are parsed normally and then checked
specially in opt_validate, but only if coming from
qemu_opts_parse_noisily. has_help_option does the check on its own.
opt_validate() has two callers: qemu_opt_set(), which passes null and is
therefore unaffected, and opts_do_parse(),
The HMP command \"change vnc TARGET\" is messy:
- it takes an ugly shortcut to determine if the option has an "id",
with incorrect results if "id=" is not preceded by an unescaped
comma.
- it deletes the existing QemuOpts and does not try to rollback
if the parsing fails (which is not causing
Looking at all merge-lists QemuOptsList, here is how they access their
QemuOpts:
reopen_opts in qemu-io-cmds.c ("qemu-img reopen -o")
qemu_opts_find(_opts, NULL)
empty_opts in qemu-io.c ("qemu-io open -o")
qemu_opts_find(_opts, NULL)
qemu_rtc_opts ("-rtc")
Am 23.01.21 um 09:59 schrieb Wataru Ashihara:
Actually I use TCI also on macOS. Like the use case quoted by Philippe,
there're even other reasons to use TCI:
1. Learning TCG ops.
2. Debugging QEMU with gdb. e.g. diagnose codegen or stepping into
helper functions from
make it consistently SOFTMMU-only.
Signed-off-by: Claudio Fontana
Reviewed-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
include/hw/core/cpu.h | 22 +-
target/alpha/cpu.c | 2 +-
target/arm/cpu.c
On 1/22/21 9:44 PM, Philippe Mathieu-Daudé wrote:
> The trace_events_subdirs array is split in two different
> locations, merge it as one.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> Cc: Stefan Hajnoczi
> ---
> meson.build | 28 +---
> 1 file changed, 13
Make CONFIG_TCG_INTERPRETER a Meson option, and enable TCI (though with
a warning) if the host CPU is unsupported, making it more similar to
other --enable-* options.
Remove TCG-specific include paths from !CONFIG_TCG builds.
Signed-off-by: Paolo Bonzini
---
configure | 11 +++
Signed-off-by: Paolo Bonzini
---
Makefile | 2 --
configure | 84 ++-
meson.build | 10 --
meson_options.txt | 2 ++
qga/meson.build | 55 +++
5 files changed, 61 insertions(+), 92 deletions(-)
From: Prasad J Pandit
While processing ioport command in 'fdctrl_write_dor', device
controller may select a drive which is not initialised with a
block device. This may result in a NULL pointer dereference.
Add checks to avoid it.
Fixes: CVE-2021-20196
Reported-by: Gaoning Pan
Buglink:
From: Bin Meng
Per the SD spec, a valid data block is suffixed with a 16-bit CRC
generated by the standard CCITT polynomial x16+x12+x5+1. This part
is currently missing in the ssi-sd state machine. Without it, all
data block transfer fails in guest software because the expected
CRC16 is missing
From: Bin Meng
At present the single/multiple block write in SPI mode is blocked
by sd_normal_command(). Remove the limitation.
Signed-off-by: Bin Meng
Acked-by: Alistair Francis
---
(no changes since v1)
hw/sd/sd.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/hw/sd/sd.c
From: Bin Meng
In the case of a multiple block read operation every transferred
block has its suffix of CRC16. Update the state machine logic to
handle multiple block read.
Signed-off-by: Bin Meng
Acked-by: Alistair Francis
---
Changes in v2:
- Fix 2 typos in the commit message
- Add a
From: Bin Meng
This updates the flash information table to include various ISSI
flashes that are supported by upstream U-Boot and Linux kernel.
Signed-off-by: Bin Meng
Acked-by: Alistair Francis
---
(no changes since v1)
hw/block/m25p80.c | 13 +
1 file changed, 13
From: Bin Meng
Add 2 more states for the block write operation. The SPI host needs
to send a data start token to start the transfer, and the data block
written to the card will be acknowledged by a data response token.
Signed-off-by: Bin Meng
Acked-by: Alistair Francis
---
Changes in v2:
-
On Thu, Jan 21, 2021 at 08:47:52AM -1000, Richard Henderson wrote:
> From: Roman Bolshakov
>
> Pages can't be both write and executable at the same time on Apple
> Silicon. macOS provides public API to switch write protection [1] for
> JIT applications, like TCG.
>
> 1.
>
commit 40612000599e ("arm: Correctly handle watchpoints for BE32 CPUs")
introduced this ARM-specific, TCG-specific hack to adjust the address,
before checking it with cpu_check_watchpoint.
Make adjust_watchpoint_address optional and move it to tcg_ops.
Signed-off-by: Claudio Fontana
---
Signed-off-by: Claudio Fontana
Reviewed-by: Alex Bennée
[claudio: rebased on Richard's splitwx work]
Signed-off-by: Claudio Fontana
---
include/hw/boards.h| 2 +-
include/{sysemu => qemu}/accel.h | 14 +
include/sysemu/hvf.h | 2 +-
this improves over the workaround in commit
5af415b7d5fd ("cpu: move cc->transaction_failed to tcg_ops")
by moving the tcg cpu operations into a separate file, which is
only included by target-specific code.
The context is that code in ss_common and ss_specific modules
might see different data
On 1/23/21 11:26 AM, Stefan Weil wrote:
> Am 23.01.21 um 09:59 schrieb Wataru Ashihara:
>
>> Actually I use TCI also on macOS. Like the use case quoted by Philippe,
>> there're even other reasons to use TCI:
>>
>> 1. Learning TCG ops.
>> 2. Debugging QEMU with gdb. e.g. diagnose codegen or
On Sat, 23 Jan 2021 at 03:18, Joelle van Dyne wrote:
On Fri, Jan 22, 2021 at 3:17 PM Peter Maydell wrote:
>> Can we do the "does system() exist?" check in meson.build ?
>> config_host_data.set('HAVE_SYSTEM_FUNCTION', cc.has_function('system'))
> Unfortunately, this doesn't work for iOS, which
From: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20210121095616.1471869-5-phi...@redhat.com>
Signed-off-by: Paolo Bonzini
---
meson.build | 66 ++---
1 file changed, 37 insertions(+), 29 deletions(-)
diff --git
From: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20210121095616.1471869-3-phi...@redhat.com>
Signed-off-by: Paolo Bonzini
---
meson.build | 30 ++
1 file changed, 18 insertions(+), 12 deletions(-)
diff --git a/meson.build
Options such as "server" or "nowait", that are commonly found in -chardev,
are sugar for "server=on" and "wait=off". This is quite surprising and
also does not have any notion of typing attached. It is even possible to
do "-device e1000,noid" and get a device with "id=off".
Deprecate it and
Signed-off-by: Paolo Bonzini
---
tests/acceptance/vnc.py | 18 ++
1 file changed, 6 insertions(+), 12 deletions(-)
diff --git a/tests/acceptance/vnc.py b/tests/acceptance/vnc.py
index 3f40bc2be1..22656bbcc2 100644
--- a/tests/acceptance/vnc.py
+++ b/tests/acceptance/vnc.py
@@
From: Philippe Mathieu-Daudé
Display block layer information altogether,
when it is relevant.
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20210121095616.1471869-7-phi...@redhat.com>
Signed-off-by: Paolo Bonzini
---
meson.build | 43 +--
1 file
Anyone to merge this?
Thanks,
Laurent
Le 20/12/2020 à 17:35, Laurent Vivier a écrit :
> In the kernel, virtio_gpu_init() uses virtio_get_shm_region()
> since
> commit 6076a9711dc5 ("drm/virtio: implement blob resources: probe for host
> visible region")
> but vm_get_shm_region() unconditionally
Is there someone to merge this?
Thanks,
Laurent
Le 20/12/2020 à 12:26, Laurent Vivier a écrit :
> After a migration the clock offset is updated, but we also
> need to re-arm the alarm if needed.
>
> Signed-off-by: Laurent Vivier
> Reviewed-by: Alistair Francis
> ---
> hw/rtc/goldfish_rtc.c |
From: Bin Meng
At present the codes use hardcoded numbers (0xff/0xfe) for the dummy
value and block start token. Replace them with macros.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
---
Changes in v2:
- Move multiple write token definitions out of this patch
hw/sd/ssi-sd.c | 26
Hello, this is version 13 of the cleanup, PART 2.
v12 -> v13: rebased on latest master.
v11 -> v12: reordered patches and improved tcg_ops
* reordered all TcgCpuOperations stuff so it is at the beginning
* added patches for ARM-specific tcg ops
debug_check_watchpoint and
for now only TCG is allowed as an accelerator for riscv,
so remove the CONFIG_TCG use.
Signed-off-by: Claudio Fontana
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index
From: Eduardo Habkost
Signed-off-by: Eduardo Habkost
[claudio: wrapped in CONFIG_TCG]
Signed-off-by: Claudio Fontana
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alex Bennée
Reviewed-by: Richard Henderson
---
include/hw/core/cpu.h | 21 -
From: Eduardo Habkost
The TCG-specific CPU methods will be moved to a separate struct,
to make it easier to move accel-specific code outside generic CPU
code in the future. Start by moving tcg_initialize().
The new CPUClass.tcg_opts field may eventually become a pointer,
but keep it an
i386 is the first user of AccelCPUClass, allowing to split
cpu.c into:
cpu.ccpuid and common x86 cpu functionality
host-cpu.c host x86 cpu functions and "host" cpu type
kvm/kvm-cpu.cKVM x86 AccelCPUClass
hvf/hvf-cpu.cHVF x86 AccelCPUClass
tcg/tcg-cpu.cTCG x86
avoid open coding the accesses to cpu->accel_cpu interfaces,
and instead introduce:
accel_cpu_instance_init,
accel_cpu_realizefn
to be used by the targets/ initfn code,
and by cpu_exec_realizefn respectively.
Add warnings about the use of target-specific headers.
Signed-off-by: Claudio Fontana
On Sat, 23 Jan 2021 at 05:03, Joelle van Dyne wrote:
>
> macOS 11/iOS 14 added preadv/pwritev APIs. Due to weak linking, configure
> will succeed with CONFIG_PREADV even when targeting a lower OS version.
> We therefore need to check at run time if we can actually use these APIs.
If you make the
From: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20210121095616.1471869-4-phi...@redhat.com>
Signed-off-by: Paolo Bonzini
---
meson.build | 54 +
1 file changed, 30 insertions(+), 24 deletions(-)
diff --git
22.01.2021 19:08, Kevin Wolf wrote:
Am 16.01.2021 um 14:44 hat Vladimir Sementsov-Ogievskiy geschrieben:
Just use classes introduced in previous three commits. Behavior
difference is described in these three commits.
Drop group file, as it becomes unused.
Drop common.env: now check is in
On 2021/01/21 22:27, Philippe Mathieu-Daudé wrote:
> On 1/21/21 1:02 PM, Daniel P. Berrangé wrote:
>> On Thu, Jan 21, 2021 at 12:48:21PM +0100, Philippe Mathieu-Daudé wrote:
>>> On 1/21/21 12:21 PM, Daniel P. Berrangé wrote:
On Thu, Jan 21, 2021 at 12:18:18PM +0100, Philippe Mathieu-Daudé
From: Bin Meng
After the card is put into SPI mode, CRC check for all commands
including CMD0 will be done according to CMD59 setting. But this
command is currently unimplemented. Simply allow the decoding of
CMD59, but the CRC remains unchecked.
Signed-off-by: Bin Meng
Reviewed-by: Pragnesh
From: Bin Meng
For a multiple block write operation, each block begins with a multi
write start token. Unlike the SD mode that the multiple block write
ends when receiving a STOP_TRAN command (CMD12), a special stop tran
token is used to signal the card.
Emulating this by manually sending a
From: Bin Meng
Add RISC-V system emulator documentation for generic information.
`Board-specific documentation` and `RISC-V CPU features` are only
a placeholder and will be added in the future.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
---
(no changes since v1)
From: Bin Meng
Import CRC16 calculation routines from Linux kernel v5.10:
include/linux/crc-ccitt.h
lib/crc-ccitt.c
to QEMU:
include/qemu/crc-ccitt.h
util/crc-ccitt.c
Signed-off-by: Bin Meng
Acked-by: Alistair Francis
---
(no changes since v1)
include/qemu/crc-ccitt.h | 33
From: Bin Meng
At present there is a data_ready() callback for the SD data read
path. Let's add a receive_ready() for the SD data write path.
Signed-off-by: Bin Meng
Acked-by: Alistair Francis
Reviewed-by: Philippe Mathieu-Daudé
---
(no changes since v1)
include/hw/sd/sd.h | 2 ++
Signed-off-by: Claudio Fontana
Reviewed-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
[claudio: replaced !CONFIG_USER_ONLY with CONFIG_SOFTMMU in cpu.h]
this is working around a dangerous issue of different parts of the code
seeing the struct
add a new optional interface to CPUClass,
which allows accelerators to extend the CPUClass
with additional accelerator-specific initializations.
Add the field before tcg_ops, and mark tcg_ops as
needing to be last in the struct until we rework this
further in a later patch.
Signed-off-by:
move the call to accel_cpu->cpu_realizefn to the general
cpu_exec_realizefn from target/i386, so it does not need to be
called for every target explicitly as we enable more targets.
Signed-off-by: Claudio Fontana
---
cpu.c | 6 ++
target/i386/cpu.c | 20 +++-
2
also centralize the registration of the cpus.c module
accelerator operations in accel/accel-softmmu.c
Consequently, rename all tcg-cpus.c, kvm-cpus.c etc to
tcg-accel-ops.c, kvm-accel-ops.c etc, also matching the
object type names.
Signed-off-by: Claudio Fontana
---
accel/accel-softmmu.h
From: Bin Meng
This adds detailed documentation for RISC-V `sifive_u` machine,
including the following information:
- Supported devices
- Hardware configuration information
- Boot options
- Machine-specific options
- Running Linux kernel
- Running VxWorks kernel
- Running U-Boot, and with an
From: Bin Meng
This adds the QSPI2 controller to the SoC, and connects an SD
card to it. The generation of corresponding device tree source
fragment is also added.
Specify machine property `msel` to 11 to boot the same upstream
U-Boot SPL and payload image for the SiFive HiFive Unleashed board.
From: Eduardo Habkost
Signed-off-by: Eduardo Habkost
[claudio: wrapped in CONFIG_TCG]
Signed-off-by: Claudio Fontana
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alex Bennée
Reviewed-by: Richard Henderson
---
include/hw/core/cpu.h | 12 ++--
accel/tcg/cpu-exec.c
On Sat, 23 Jan 2021 at 00:06, Laszlo Ersek wrote:
> On 01/22/21 11:14, Peter Maydell wrote:
> > I think (but have not checked) that that means we will build and
> > link the object file into the user-mode binaries if you happen
> > to build them in the same run as system-mode binaries,
>
> I did
Use qemu_opts_parse_noisily now that HMP does not call
vnc_parse anymore.
Signed-off-by: Paolo Bonzini
Reviewed-by: Eric Blake
Reviewed-by: Gerd Hoffmann
Message-Id: <20210120144235.345983-4-pbonz...@redhat.com>
Signed-off-by: Paolo Bonzini
---
include/ui/console.h | 2 +-
softmmu/vl.c
From: Philippe Mathieu-Daudé
The --enable-bzip2/--disable-bzip2 configure arguments are
somehow misleading, they check for the bzip2 library, not
the bzip2 program.
We need the bzip2 program to install the EDK2 firmware blobs
(see commit 623ef637a2e "configure: Check bzip2 is available").
From: Philippe Mathieu-Daudé
Display accelerators and selected targets altogether,
avoid to display unuseful information when not relevant.
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20210121095616.1471869-6-phi...@redhat.com>
Signed-off-by: Paolo Bonzini
---
meson.build | 38
From: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20210121095616.1471869-2-phi...@redhat.com>
Signed-off-by: Paolo Bonzini
---
meson.build | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/meson.build b/meson.build
index
From: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20210121095616.1471869-9-phi...@redhat.com>
Signed-off-by: Paolo Bonzini
---
meson.build | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/meson.build b/meson.build
index abd2c05a82..bd6ad06d58
22.01.2021 19:54, Eric Blake wrote:
On 12/11/20 12:39 PM, Vladimir Sementsov-Ogievskiy wrote:
We are generally moving to int64_t for both offset and bytes parameters
on all io paths.
Main motivation is realization of 64-bit write_zeroes operation for
fast zeroing large disk chunks, up to the
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