Signed-off-by: Cédric Le Goater
---
include/hw/pci-host/pnv_phb4.h | 2 ++
hw/pci-host/pnv_phb4_pec.c | 2 ++
hw/ppc/pnv.c | 4 ++--
3 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/include/hw/pci-host/pnv_phb4.h b/include/hw/pci-host/pnv_phb4.h
index
PHB3s ared SysBus devices and should be allowed to be dynamically
created.
Signed-off-by: Cédric Le Goater
---
hw/pci-host/pnv_phb3.c | 9 +
hw/ppc/pnv.c | 2 ++
2 files changed, 11 insertions(+)
diff --git a/hw/pci-host/pnv_phb3.c b/hw/pci-host/pnv_phb3.c
index
Use the num_stacks class attribute to compute the PHB index depending
on the PEC index :
* PEC0 provides 1 PHB (PHB0)
* PEC1 provides 2 PHBs (PHB1 and PHB2)
* PEC2 provides 3 PHBs (PHB3, PHB4 and PHB5)
Signed-off-by: Cédric Le Goater
---
hw/pci-host/pnv_phb4_pec.c | 16
The return value of virtio_blk_handle_vq() is no longer used. Get rid of
it. This is a step towards unifying the dataplane and non-dataplane
virtqueue handler functions.
Prepare virtio_blk_handle_output() to be used by both dataplane and
non-dataplane by making the condition for starting
The current default PCI group being used can technically collide with a
real group ID passed from a hostdev. Let's instead use a group ID that comes
from a special pool that is architected to be reserved for simulated devices.
Fixes: 28dc86a072 ("s390x/pci: use a PCI Group structure")
Instead use the values from clp info, they will either be the hard-coded
values or what came from the host driver via vfio.
Fixes: 9670ee752727 ("s390x/pci: use a PCI Function structure")
Signed-off-by: Matthew Rosato
---
hw/s390x/s390-pci-inst.c | 9 +
1 file changed, 5 insertions(+),
From: Hyman Huang(黄勇)
Implement dirtyrate calculation periodically basing on
dirty-ring and throttle vCPU until it reachs the quota
dirty page rate given by user.
Introduce qmp commands "vcpu-dirty-limit", "query-vcpu-dirty-limit"
to enable, disable, query dirty page limit for virtual CPU.
On Thu, Dec 02 2021, Alex Bennée wrote:
> This reverts commit 7852a77f598635a67a222b6c1463c8b46098aed2.
>
> The check is bogus as it ends up finding itself and falling over.
>
> Signed-off-by: Alex Bennée
> Resolves: https://gitlab.com/qemu-project/qemu.git/-/issues/733
> ---
>
On 12/2/21 11:42, Cédric Le Goater wrote:
This is not useful and will be in the way for support of user created
PHB4 devices.
Signed-off-by: Cédric Le Goater
---
Reviewed-by: Daniel Henrique Barboza
hw/pci-host/pnv_phb4_pec.c | 6 +-
hw/ppc/pnv.c | 2 --
2 files
The default addresses to load the kernel, fdt, initrd of AMCC boards
in U-Boot v2015.10 are :
"kernel_addr_r=100\0"
"fdt_addr_r=180\0"
"ramdisk_addr_r=190\0"
The taihu is one of these boards, the ref405ep is not but we don't
have much information on it and
On 02.12.21 18:11, Matthew Rosato wrote:
> On 12/2/21 11:43 AM, David Hildenbrand wrote:
>> On 02.12.21 17:41, Matthew Rosato wrote:
>>> The current default PCI group being used can technically collide with a
>>> real group ID passed from a hostdev. Let's instead use a group ID that
>>> comes
Following the guidelines in tests/qtest/bios-tables-test.c, this
is step 6.
Below is the disassembly of tests/data/acpi/pc/ERST.acpierst.
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20180508 (64-bit version)
* Copyright (c) 2000 - 2018 Intel Corporation
*
*
They have been there since 2007 without any board using them, most
were protected by a TODO define. Drop support.
Signed-off-by: Cédric Le Goater
---
target/ppc/cpu-models.h | 19 --
target/ppc/cpu-qom.h | 4 -
target/ppc/cpu-models.c | 34 ---
target/ppc/cpu_init.c| 512
This change exposes ACPI ERST support for x86 guests.
Signed-off-by: Eric DeVolder
---
hw/i386/acpi-build.c | 15 +++
hw/i386/acpi-microvm.c | 15 +++
include/hw/acpi/erst.h | 5 +
3 files changed, 35 insertions(+)
diff --git a/hw/i386/acpi-build.c
On 02/12/2021 20.14, Cédric Le Goater wrote:
The default addresses to load the kernel, fdt, initrd of AMCC boards
in U-Boot v2015.10 are :
"kernel_addr_r=100\0"
"fdt_addr_r=180\0"
"ramdisk_addr_r=190\0"
The taihu is one of these boards, the ref405ep is not
Unlike i386, m68k get_thread_area has no arguments.
Signed-off-by: Richard Henderson
---
linux-user/strace.list | 5 +
1 file changed, 5 insertions(+)
diff --git a/linux-user/strace.list b/linux-user/strace.list
index 278596acd1..72e17b1acf 100644
--- a/linux-user/strace.list
+++
On 11/23/21 01:14, Christian Borntraeger wrote:
>
> Am 22.11.21 um 23:33 schrieb Collin Walling:
>> DIAGNOSE 0318 is invoked only once during IPL. As such, the
>> diag318 info will only change once initially and during resets.
>> Let's only sync the register to convey the info to KVM if and
>>
Replace an if ladder with a switch for clarity.
Signed-off-by: Richard Henderson
---
target/m68k/op_helper.c | 45 +
1 file changed, 28 insertions(+), 17 deletions(-)
diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c
index
On Thu, 2021-12-02 at 11:41 -0500, Matthew Rosato wrote:
> Instead use the values from clp info, they will either be the hard-
> coded
> values or what came from the host driver via vfio.
>
> Fixes: 9670ee752727 ("s390x/pci: use a PCI Function structure")
> Signed-off-by: Matthew Rosato
On Thu, 2021-12-02 at 11:41 -0500, Matthew Rosato wrote:
> The current default PCI group being used can technically collide with
> a
> real group ID passed from a hostdev. Let's instead use a group ID
> that comes
> from a special pool that is architected to be reserved for simulated
> devices.
>
On Thu, 2021-12-02 at 11:41 -0500, Matthew Rosato wrote:
> The DTSM is a mask that specifies which I/O Address Translation
> designation
> types are supported. A linux guest today does not look at this field
> but
> could in the future; let's advertise what QEMU actually supports.
>
>
This builds the ACPI ERST table to inform OSPM how to communicate
with the acpi-erst device.
Signed-off-by: Eric DeVolder
---
hw/acpi/erst.c | 241 +
1 file changed, 241 insertions(+)
diff --git a/hw/acpi/erst.c b/hw/acpi/erst.c
index
According to the M68040 Users Manual, section 8.4.3,
Six word stack frame (format 2), Trace (and others) is
supposed to record the next insn in PC and the address
of the trapping instruction in ADDRESS.
Create gen_raise_exception_format2 to record the trapping
pc in env->mmu.ar. Update
According to the M68040 Users Manual, section 8.4.3,
Six word stack frame (format 2), Zero Div (and others)
is supposed to record the next insn in PC and the
address of the trapping instruction in ADDRESS.
While the N, Z and V flags are documented to be undefine on DIV0,
the C flag is documented
Signed-off-by: Richard Henderson
---
target/m68k/translate.c | 30 ++
1 file changed, 30 insertions(+)
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index cfe292c929..641f95ff8a 100644
--- a/target/m68k/translate.c
+++ b/target/m68k/translate.c
@@
According to the M68040 Users Manual, section 8.4.3, Four word
stack frame (format 0), includes Illegal Instruction. Use the
correct frame format, which does not use the ADDR argument.
Signed-off-by: Richard Henderson
---
target/m68k/op_helper.c | 3 +--
1 file changed, 1 insertion(+), 2
This change introduces the public defintions for ACPI ERST.
Signed-off-by: Eric DeVolder
Reviewed-by: Ani Sinha
---
include/hw/acpi/erst.h | 19 +++
1 file changed, 19 insertions(+)
create mode 100644 include/hw/acpi/erst.h
diff --git a/include/hw/acpi/erst.h
On 12/1/21 10:17 PM, John Snow wrote:
The following changes since commit 682aa69b1f4dd5f2905a94066fa4c853adc33251:
Update version for v6.2.0-rc3 release (2021-12-01 07:20:06 +0100)
are available in the Git repository at:
https://gitlab.com/jsnow/qemu.git tags/ide-pull-request
for you
Use the new function instead of setting up a target_siginfo_t
and calling queue_signal. Fill in the missing PC for SIGTRAP.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
linux-user/m68k/cpu_loop.c | 24
1 file changed, 4 insertions(+), 20 deletions(-)
Signed-off-by: Richard Henderson
---
target/m68k/translate.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index e5338b50ad..cfe292c929 100644
--- a/target/m68k/translate.c
+++ b/target/m68k/translate.c
@@ -4916,6 +4916,14 @@
Le 02/12/2021 à 20:19, Cédric Le Goater a écrit :
> On 12/2/21 20:17, Thomas Huth wrote:
>> On 02/12/2021 20.14, Cédric Le Goater wrote:
>>> The default addresses to load the kernel, fdt, initrd of AMCC boards
>>> in U-Boot v2015.10 are :
>>>
>>> "kernel_addr_r=100\0"
>>>
The only value this variable holds is now env->pc.
Signed-off-by: Richard Henderson
---
target/m68k/op_helper.c | 15 ++-
1 file changed, 6 insertions(+), 9 deletions(-)
diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c
index 71176eb3d8..afbbb8b4ca 100644
---
Rather than adjust the PC in all of the consumers, raise
the exception with the correct PC in the first place.
Signed-off-by: Richard Henderson
---
linux-user/m68k/cpu_loop.c | 1 -
target/m68k/op_helper.c| 9 -
target/m68k/translate.c| 2 +-
3 files changed, 1 insertion(+), 11
Test various trap instructions: chk, div, trap, trapv, trapcc, ftrapcc,
and the signals and addresses that we expect from them.
Signed-off-by: Richard Henderson
---
tests/tcg/m68k/trap.c | 129 +
tests/tcg/m68k/Makefile.target | 3 +
2 files changed,
Signed-off-by: Richard Henderson
---
target/m68k/cpu.h | 2 ++
linux-user/m68k/cpu_loop.c | 1 +
target/m68k/cpu.c | 1 +
target/m68k/op_helper.c| 2 +-
target/m68k/translate.c| 41 ++
5 files changed, 46 insertions(+), 1
On 12/2/21 11:11 AM, Cédric Le Goater wrote:
They have been there since 2007 without any board using them, most
were protected by a TODO define. Drop support.
Signed-off-by: Cédric Le Goater
---
target/ppc/cpu-models.h | 19 --
target/ppc/cpu-qom.h | 4 -
target/ppc/cpu-models.c |
On 12/2/21 20:17, Thomas Huth wrote:
On 02/12/2021 20.14, Cédric Le Goater wrote:
The default addresses to load the kernel, fdt, initrd of AMCC boards
in U-Boot v2015.10 are :
"kernel_addr_r=100\0"
"fdt_addr_r=180\0"
"ramdisk_addr_r=190\0"
The taihu is one of these
Supercedes: <20211130103752.72099-1-richard.hender...@linaro.org>
Reviewing v1, Laurent rightly noticed that there were changes
required in m68k_interrupt_all. Matching sysemu, there were
changes needed in the linux-user cpu_loop.
In the process, I found a number of other trap related bugs,
and
These are raised by guest instructions, and should not
fall through into the default abort case.
Signed-off-by: Richard Henderson
---
linux-user/m68k/cpu_loop.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/linux-user/m68k/cpu_loop.c b/linux-user/m68k/cpu_loop.c
index
Errors are not all negative numbers, but only the top 4k.
Signed-off-by: Richard Henderson
---
linux-user/strace.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/linux-user/strace.c b/linux-user/strace.c
index 2cdbf030ba..f235118fb6 100644
--- a/linux-user/strace.c
+++
According to the M68040 Users Manual, section 8.4.3,
Six word stack frame (format 2), CHK, CHK2 (and others)
are supposed to record the next insn in PC and the
address of the trapping instruction in ADDRESS.
Create a raise_exception_format2 function to centralize recording
of the trapping pc in
On Thu, 2021-12-02 at 11:41 -0500, Matthew Rosato wrote:
> We may have gotten a measurement update interval from the underlying
> host
> via vfio -- Use it to set the interval via which we update the
> function
> measurement block.
>
> Fixes: 28dc86a072 ("s390x/pci: use a PCI Group structure")
>
v2:
- Cleaned up unused return values in nvme and virtio-blk [Stefano]
- Documented try_poll_mode() ready_list argument [Stefano]
- Unified virtio-blk/scsi dataplane and non-dataplane virtqueue handlers
[Stefano]
The first patch improves AioContext's adaptive polling execution time
measurement.
* Juan Quintela (quint...@redhat.com) wrote:
> "Dr. David Alan Gilbert" wrote:
> > * Juan Quintela (quint...@redhat.com) wrote:
> >> "Dr. David Alan Gilbert" wrote:
> >> > * Juan Quintela (quint...@redhat.com) wrote:
> >> >> This patch adds counters and similar. Logic will be added on the
> >>
On Thu, Dec 02, 2021 at 04:49:29PM +, Alex Bennée wrote:
> This reverts commit 7852a77f598635a67a222b6c1463c8b46098aed2.
>
> The check is bogus as it ends up finding itself and falling over.
>
> Signed-off-by: Alex Bennée
> Resolves: https://gitlab.com/qemu-project/qemu.git/-/issues/733
>
From: Hyman Huang(黄勇)
v8:
- rebase on master
- polish the error message and remove the "unlikely" compilation syntax
according to the advice given by Markus.
- keep the dirty tracking enabled during "dirtylimit-calc" lifecycle
so that the overhead can be reduced according to the advice given
On 12/2/21 17:49, Alex Bennée wrote:
> This reverts commit 7852a77f598635a67a222b6c1463c8b46098aed2.
>
> The check is bogus as it ends up finding itself and falling over.
>
> Signed-off-by: Alex Bennée
> Resolves: https://gitlab.com/qemu-project/qemu.git/-/issues/733
This link gives 404. The
This change provides a qtest that locates and then does a simple
interrogation of the ERST feature within the guest.
Signed-off-by: Eric DeVolder
---
tests/qtest/erst-test.c | 167
tests/qtest/meson.build | 2 +
2 files changed, 169
Adaptive polling measures the execution time of the polling check plus
handlers called when a polled event becomes ready. Handlers can take a
significant amount of time, making it look like polling was running for
a long time when in fact the event handler was running for a long time.
For
Not sure if this is related, but builds are failing with:
FAILED: libblockdev.fa.p/block_export_fuse.c.o
cc -m64 -mcx16 -Ilibblockdev.fa.p -I. -I.. -Iqapi -Itrace -Iui -Iui/shader
-I/usr/include/fuse3 -I/usr/include/p11-kit-1 -I/usr/include/glib-2.0
-I/usr/lib64/glib-2.0/include
On 12/2/21 11:42, Cédric Le Goater wrote:
The powernv machine uses the object hierarchy to populate the device
tree and each device should be parented to the chip it belongs to.
This is not the case for user created devices which are parented to
the container "/unattached".
Make sure a PHB3
On 12/2/21 11:42, Cédric Le Goater wrote:
This change will help us providing support for user created PHB4
devices.
Signed-off-by: Cédric Le Goater
---
Reviewed-by: Daniel Henrique Barboza
hw/pci-host/pnv_phb4_pec.c | 36
hw/ppc/pnv.c
On 12/2/21 11:42, Cédric Le Goater wrote:
PHB4 devices and PCI devices can now be added to the powernv9 machine
using:
-device pnv-phb4-pec,chip-id=0,index=0
-device nec-usb-xhci,bus=pci.0,addr=0x0
In case of user created devices, a lookup on 'chip-id' is required to
assign the owning
On 12/2/21 11:42, Cédric Le Goater wrote:
Signed-off-by: Cédric Le Goater
---
Reviewed-by: Daniel Henrique Barboza
include/hw/pci-host/pnv_phb4.h | 2 ++
hw/pci-host/pnv_phb4_pec.c | 2 ++
hw/ppc/pnv.c | 4 ++--
3 files changed, 6 insertions(+), 2 deletions(-)
This change implements the test suite checks for the ERST table.
Signed-off-by: Eric DeVolder
---
tests/qtest/bios-tables-test.c | 56 ++
1 file changed, 56 insertions(+)
diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
index
On Wed, 1 Dec 2021 at 17:19, Stefan Hajnoczi wrote:
>
> Compiler optimizations can cache TLS values across coroutine yield
> points, resulting in stale values from the previous thread when a
> coroutine is re-entered by a new thread.
>
> Serge Guelton developed an __attribute__((noinline))
This change will help us providing support for user created PHB4
devices.
Signed-off-by: Cédric Le Goater
---
hw/pci-host/pnv_phb4_pec.c | 36
hw/ppc/pnv.c | 31 +--
2 files changed, 33 insertions(+), 34 deletions(-)
The difference between ->handle_output() and ->handle_aio_output() was
that ->handle_aio_output() returned a bool return value indicating
progress. This was needed by the old polling API but now that the bool
return value is gone, the two functions can be unified.
Signed-off-by: Stefan Hajnoczi
* Juan Quintela (quint...@redhat.com) wrote:
> "Dr. David Alan Gilbert" wrote:
> > * Juan Quintela (quint...@redhat.com) wrote:
> >> This patch adds counters and similar. Logic will be added on the
> >> following patch.
> >>
> >> Signed-off-by: Juan Quintela
> >> ---
> >> migration/multifd.h
Sorry... I missed copy maintainers and qemu-stable. This should be
considered a regression.
-- Forwarded message -
From: Mark Mielke
Date: Thu, Dec 2, 2021 at 11:26 AM
Subject: [PATCH] virtio-blk: Fix clean up of host notifiers for single
MR transaction.
To:
The code that
This reverts commit 7852a77f598635a67a222b6c1463c8b46098aed2.
The check is bogus as it ends up finding itself and falling over.
Signed-off-by: Alex Bennée
Resolves: https://gitlab.com/qemu-project/qemu.git/-/issues/733
---
hw/display/vga-isa.c | 10 --
1 file changed, 10 deletions(-)
"Dr. David Alan Gilbert" wrote:
> * Juan Quintela (quint...@redhat.com) wrote:
>> "Dr. David Alan Gilbert" wrote:
>> > * Juan Quintela (quint...@redhat.com) wrote:
>> >> "Dr. David Alan Gilbert" wrote:
>> >> > * Juan Quintela (quint...@redhat.com) wrote:
>> >> >> This patch adds counters and
The code that introduced "virtio-blk: Configure all host notifiers in
a single MR transaction" introduced a second loop variable to perform
cleanup in second loop, but mistakenly still refers to the first
loop variable within the second loop body.
Fixes: d0267da61489 ("virtio-blk: Configure all
On 12/2/21 11:42, Cédric Le Goater wrote:
PHB3s ared SysBus devices and should be allowed to be dynamically
created.
Signed-off-by: Cédric Le Goater
---
Reviewed-by: Daniel Henrique Barboza
hw/pci-host/pnv_phb3.c | 9 +
hw/ppc/pnv.c | 2 ++
2 files changed, 11
* Juan Quintela (quint...@redhat.com) wrote:
> "Dr. David Alan Gilbert" wrote:
> > * Juan Quintela (quint...@redhat.com) wrote:
> >> So we use multifd to transmit zero pages.
> >>
> >> Signed-off-by: Juan Quintela
> >> ---
> >> migration/ram.c | 22 +++---
> >> 1 file changed,
This is not useful and will be in the way for support of user created
PHB4 devices.
Signed-off-by: Cédric Le Goater
---
hw/pci-host/pnv_phb4_pec.c | 6 +-
hw/ppc/pnv.c | 2 --
2 files changed, 1 insertion(+), 7 deletions(-)
diff --git a/hw/pci-host/pnv_phb4_pec.c
Each PEC devices of the POWER9 chip has a predefined number of stacks,
equivalent of a root port complex:
PEC0 -> 1 stack
PEC1 -> 2 stacks
PEC2 -> 3 stacks
Introduce a class attribute to hold these values and remove the
"num-stacks" property.
Signed-off-by: Cédric Le Goater
---
On Thu, 2 Dec 2021 at 14:44, Peter Maydell wrote:
> My compiler-developer colleagues present the following case where
> 'noinline' is not sufficient for the compiler to definitely
> use different values of the address-of-the-TLS-var across an
> intervening function call:
>
> __thread int i;
>
>
On 12/2/21 04:23, Thomas Huth wrote:
> On 01/12/2021 19.45, Collin Walling wrote:
>> Polite ping. I may have missed if this patch was picked already. Thanks!
>
> I've already queued it to my s390x-next branch:
>
> https://gitlab.com/thuth/qemu/-/commits/s390x-next/
>
> It just came in very
huang...@chinatelecom.cn writes:
> From: Hyman Huang(黄勇)
>
> Implement dirtyrate calculation periodically basing on
> dirty-ring and throttle vCPU until it reachs the quota
> dirty page rate given by user.
>
> Introduce qmp commands set-dirty-limit/cancel-dirty-limit to
> set/cancel dirty page
On 12/2/21 11:42, Cédric Le Goater wrote:
It is never used.
Signed-off-by: Cédric Le Goater
---
Reviewed-by: Daniel Henrique Barboza
hw/ppc/pnv.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index bd768dcc28ad..988b305398b2 100644
--- a/hw/ppc/pnv.c
On 12/2/21 11:42, Cédric Le Goater wrote:
All POWER8 machines have a maximum of 3 PHB3 devices. Adapt the
PNV8_CHIP_PHB3_MAX definition for consistency.
I suggest "3 PHB3 devices per chip" for clarity.
Signed-off-by: Cédric Le Goater
---
Reviewed-by: Daniel Henrique Barboza
"Dr. David Alan Gilbert" wrote:
> * Juan Quintela (quint...@redhat.com) wrote:
>> So we use multifd to transmit zero pages.
>>
>> Signed-off-by: Juan Quintela
>> ---
>> migration/ram.c | 22 +++---
>> 1 file changed, 11 insertions(+), 11 deletions(-)
>>
>> diff --git
On 12/2/21 12:08, Alex Bennée wrote:
> Philippe Mathieu-Daudé writes:
>> On 11/29/21 13:58, Alex Bennée wrote:
>>>
>>> Juro Bystricky writes:
>>>
Fix compiler warnings. The warnings can result in a broken build.
This patch fixes warnings such as:
>>>
>>> Queued to
On 12/2/21 11:42, Cédric Le Goater wrote:
Use the num_stacks class attribute to compute the PHB index depending
on the PEC index :
* PEC0 provides 1 PHB (PHB0)
* PEC1 provides 2 PHBs (PHB1 and PHB2)
* PEC2 provides 3 PHBs (PHB3, PHB4 and PHB5)
Signed-off-by: Cédric Le Goater
---
This implements a PCI device for ACPI ERST. This implements the
non-NVRAM "mode" of operation for ERST as it is supported by
Linux and Windows.
Signed-off-by: Eric DeVolder
---
hw/acpi/Kconfig | 6 +
hw/acpi/erst.c | 836 +++
Following the guidelines in tests/qtest/bios-tables-test.c, this
change adds empty placeholder files per step 1 for the new ERST
table, and excludes resulting changed files in bios-tables-test-allowed-diff.h
per step 2.
Signed-off-by: Eric DeVolder
Acked-by: Igor Mammedov
---
Information on the implementation of the ACPI ERST support.
Signed-off-by: Eric DeVolder
Acked-by: Ani Sinha
---
docs/specs/acpi_erst.rst | 200 +++
1 file changed, 200 insertions(+)
create mode 100644 docs/specs/acpi_erst.rst
diff --git
On Mittwoch, 1. Dezember 2021 23:46:43 CET Will Cohen wrote:
> On Wed, Nov 24, 2021 at 9:23 AM Christian Schoenebeck <
>
> qemu_...@crudebyte.com> wrote:
> > On Montag, 22. November 2021 01:49:05 CET Will Cohen wrote:
> > > From: Keno Fischer
> > >
> > > Signed-off-by: Keno Fischer
> > >
"Dr. David Alan Gilbert" wrote:
> * Juan Quintela (quint...@redhat.com) wrote:
>> "Dr. David Alan Gilbert" wrote:
>> > * Juan Quintela (quint...@redhat.com) wrote:
>> >> This patch adds counters and similar. Logic will be added on the
>> >> following patch.
>> >>
>> >> Signed-off-by: Juan
* Juan Quintela (quint...@redhat.com) wrote:
> This implements the zero page dection and handling.
>
> Signed-off-by: Juan Quintela
> ---
> migration/multifd.c | 33 +++--
> 1 file changed, 31 insertions(+), 2 deletions(-)
>
> diff --git a/migration/multifd.c
On 02.12.21 17:41, Matthew Rosato wrote:
> The current default PCI group being used can technically collide with a
> real group ID passed from a hostdev. Let's instead use a group ID that comes
> from a special pool that is architected to be reserved for simulated devices.
>
> Fixes: 28dc86a072
The DTSM is a mask that specifies which I/O Address Translation designation
types are supported. A linux guest today does not look at this field but
could in the future; let's advertise what QEMU actually supports.
Signed-off-by: Matthew Rosato
---
hw/s390x/s390-pci-bus.c | 1 +
On 12/2/21 11:43 AM, David Hildenbrand wrote:
On 02.12.21 17:41, Matthew Rosato wrote:
The current default PCI group being used can technically collide with a
real group ID passed from a hostdev. Let's instead use a group ID that comes
from a special pool that is architected to be reserved for
* Juan Quintela (quint...@redhat.com) wrote:
> So we use multifd to transmit zero pages.
>
> Signed-off-by: Juan Quintela
> ---
> migration/ram.c | 22 +++---
> 1 file changed, 11 insertions(+), 11 deletions(-)
>
> diff --git a/migration/ram.c b/migration/ram.c
> index
On 12/2/21 11:42, Cédric Le Goater wrote:
Next changes will make use of it.
Signed-off-by: Cédric Le Goater
---
Reviewed-by: Daniel Henrique Barboza
include/hw/pci-host/pnv_phb4.h | 2 ++
hw/pci-host/pnv_phb4_pec.c | 2 ++
hw/ppc/pnv.c | 2 ++
3 files
On 12/2/21 18:27, Daniel Henrique Barboza wrote:
On 12/2/21 11:42, Cédric Le Goater wrote:
All POWER8 machines have a maximum of 3 PHB3 devices. Adapt the
PNV8_CHIP_PHB3_MAX definition for consistency.
I suggest "3 PHB3 devices per chip" for clarity.
Fixed.
Thanks,
C.
On 12/2/21 11:51, Jiaxun Yang wrote:
> 在2021年11月30日十一月 下午9:52，Philippe Mathieu-Daudé写道：
>> On 11/30/21 22:17, Jiaxun Yang wrote:
>>> bl_gen_write_ulong uses sd for both 32 and 64 bit CPU,
>>> while sd is illegal on 32 bit CPUs.
>>>
>>> Replace sd with sw on 32bit CPUs.
>>>
>>> Fixes: 3ebbf86
On 11/30/21 22:17, Jiaxun Yang wrote:
> Two problems caught when I was trying to add CI job for various
> configurations.
>
> Jiaxun Yang (2):
> hw/mips: bootloader: Fix write_ulong
> hw/mips/boston: Fix elf_load error detection
Thanks, queued to mips-fixes.
Now that virtio-blk and virtio-scsi are ready, get rid of
the handle_aio_output() callback. It's no longer needed.
Signed-off-by: Stefan Hajnoczi
---
include/hw/virtio/virtio.h | 4 +--
hw/block/dataplane/virtio-blk.c | 16 ++
hw/scsi/virtio-scsi-dataplane.c | 54
"Dr. David Alan Gilbert" wrote:
> * Juan Quintela (quint...@redhat.com) wrote:
>> This implements the zero page dection and handling.
>>
>> Signed-off-by: Juan Quintela
>> ---
>> migration/multifd.c | 33 +++--
>> 1 file changed, 31 insertions(+), 2 deletions(-)
>>
On 12/2/21 11:42, Cédric Le Goater wrote:
POWER9 processor comes with 3 PHB4 PECs (PCI Express Controller) and
each PEC can have several PHBs :
* PEC0 provides 1 PHB (PHB0)
* PEC1 provides 2 PHBs (PHB1 and PHB2)
* PEC2 provides 3 PHBs (PHB3, PHB4 and PHB5)
A num_pecs class
On 02/12/2021 17:14, Cornelia Huck wrote:
On Thu, Dec 02 2021, Alex Bennée wrote:
This reverts commit 7852a77f598635a67a222b6c1463c8b46098aed2.
The check is bogus as it ends up finding itself and falling over.
Signed-off-by: Alex Bennée
Resolves:
This patchset introduces support for the ACPI Error Record
Serialization Table, ERST.
For background and implementation information, please see
docs/specs/acpi_erst.rst, which is patch 2/10.
Suggested-by: Konrad Wilk
Signed-off-by: Eric DeVolder
---
v9: 2dec2021
- Addressed feedback from Ani
This change reserves the PCI device_id for the new ACPI ERST
device.
Signed-off-by: Eric DeVolder
Acked-by: Igor Mammedov
Acked-by: Ani Sinha
---
include/hw/pci/pci.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h
index e7cdf2d..d3734b9 100644
* Peter Maydell:
> On Thu, 2 Dec 2021 at 14:44, Peter Maydell wrote:
>> My compiler-developer colleagues present the following case where
>> 'noinline' is not sufficient for the compiler to definitely
>> use different values of the address-of-the-TLS-var across an
>> intervening function call:
PHB4 devices and PCI devices can now be added to the powernv9 machine
using:
-device pnv-phb4-pec,chip-id=0,index=0
-device nec-usb-xhci,bus=pci.0,addr=0x0
In case of user created devices, a lookup on 'chip-id' is required to
assign the owning chip.
To be noted, that the PEC PHB4 devices
The virtqueue host notifier API
virtio_queue_aio_set_host_notifier_handler() polls the virtqueue for new
buffers. AioContext previously required a bool progress return value
indicating whether an event was handled or not. This is no longer
necessary because the AioContext polling API has been
Prepare virtio_scsi_handle_cmd() to be used by both dataplane and
non-dataplane by making the condition for starting ioeventfd more
specific. This way it won't trigger when dataplane has already been
started.
Signed-off-by: Stefan Hajnoczi
---
hw/scsi/virtio-scsi.c | 2 +-
1 file changed, 1
On Thu, Dec 02, 2021 at 03:49:08PM +, Richard W.M. Jones wrote:
>
> Not sure if this is related, but builds are failing with:
>
> FAILED: libblockdev.fa.p/block_export_fuse.c.o
> cc -m64 -mcx16 -Ilibblockdev.fa.p -I. -I.. -Iqapi -Itrace -Iui -Iui/shader
> -I/usr/include/fuse3
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