On 12/18/21 20:42, Richard Henderson wrote:
> Bitwise operations are easy to fold, because the operation is
> identical regardess of element size. But add and sub need
Typo "regardless".
> extra element size info that is not currently propagated.
>
> Fixes: 2f9f08ba43d
> Signed-off-by: Richard
On 12/18/21 20:42, Richard Henderson wrote:
> We've had placeholders for these opcodes for a while,
> and should have support on ppc, s390x and avx512 hosts.
>
> Signed-off-by: Richard Henderson
> ---
> include/tcg/tcg-opc.h| 3 +++
> include/tcg/tcg.h| 3 +++
>
From: Philippe Mathieu-Daudé
Without the previous commit, this test triggers:
$ make check-qtest-x86_64
[...]
Running test qtest-x86_64/fuzz-megasas-test
qemu-system-x86_64: softmmu/physmem.c:3229: address_space_unmap: Assertion
`mr != NULL' failed.
Broken pipe
ERROR
Hi Alexandre,
sndio is the native API used by OpenBSD, although it has been ported to
other *BSD's and Linux (packages for Ubuntu, Debian, Void, Arch, etc.).
Signed-off-by: Brad Smith
Signed-off-by: Alexandre Ratchov
---
Thank you for the reviews and all the comments. Here's a second diff
COLO-compare use the glib function g_queue_find_custom to dump
another VM's networking packet to compare. But this function always
start find from the queue->head(here is the newest packet), It will
reduce the success rate of comparison. So this patch reversed
the order of the queues for
Make the comments consistent with the REGULAR_PACKET_CHECK_MS.
Signed-off-by: Zhang Chen
---
net/colo-compare.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/net/colo-compare.c b/net/colo-compare.c
index 216de5a12b..62554b5b3c 100644
--- a/net/colo-compare.c
+++
CC'ing Alistair and Andreas that were involved in original fix 1c3dfb506ea3 ("linux-user/signal:
Decode waitid si_code")
Thanks,
Laurent
Le 23/10/2021 à 21:59, Matthias Schiffer a écrit :
When converting a siginfo_t from waitid(), the interpretation of si_status
depends on the value of
Le 15/12/2021 à 11:55, Philippe Mathieu-Daudé a écrit :
Ping? (patch reviewed)
On 11/6/21 12:39, Philippe Mathieu-Daudé wrote:
cpu_loop() never exits, so mark it with QEMU_NORETURN.
Reviewed-by: Richard Henderson
Reviewed-By: Warner Losh
Reviewed-by: Bin Meng
Signed-off-by: Philippe
Le 11/12/2021 à 03:27, Tonis Tiigi a écrit :
Signed-off-by: Tonis Tiigi
---
linux-user/syscall.c | 55 +++
linux-user/syscall_defs.h | 15 +++
2 files changed, 70 insertions(+)
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index
When the guest resolution changes and the UI is in full screen,
do not update the size hints. The gfx.scale_x and gfx.scale_y
variables are still wrong as they will be only recomputed on
gd_draw_event.
Just keep the window in fullscreen mode instead.
Signed-off-by: Jindřich Makovička
---
Make pc-bios/meson.build use the files in the source tree as inputs
to bzip2.
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
configure | 1 -
pc-bios/meson.build | 2 +-
2 files changed, 1 insertion(+), 2 deletions(-)
diff --git a/configure b/configure
index
$ARCH and the HOST_* symbols are only used by the QEMU build; configure
uses $cpu instead. Remove it from config-host.mak.
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
configure | 21 -
meson.build | 26 +-
2 files changed, 21
From: Philippe Mathieu-Daudé
If we detect an overflow on the SGL buffer, do not
keep processing the command: discard it. TARGET_FAILURE
sense code will be returned (MFI_STAT_SCSI_DONE_WITH_ERROR).
Reported-by: Alexander Bulekov
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/521
"if (tcg_enabled())" allows elision of the code inside it; we only need
the prototype to exist, so that the code compile even for the --disable-tcg
case.
Signed-off-by: Paolo Bonzini
---
cpu.c | 5 -
include/exec/cpu-all.h | 2 --
2 files changed, 7 deletions(-)
diff --git
targetos is already mostly the same as Meson host_machine.system(),
just in CamelCase. Adjust Windows, which is different, and switch to
lowercase to match Meson.
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
configure | 58
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
configure | 67 ++-
1 file changed, 32 insertions(+), 35 deletions(-)
diff --git a/configure b/configure
index f0a82dd8f5..77ccc15b73 100755
--- a/configure
+++ b/configure
@@
From: Philippe Mathieu-Daudé
If the 'i8042' property is not set, mouse events handled by
vmmouse_mouse_event() end calling i8042_isa_mouse_fake_event()
with a NULL argument, resulting in ps2_mouse_fake_event() being
called with invalid PS2MouseState pointer. Fix by requiring
the 'i8042' property
From: Philippe Mathieu-Daudé
Commit 739e95f5741 ("scsi: Replace scsi_bus_new() with
scsi_bus_init(), scsi_bus_init_named()") forgot to rename
scsi_bus_init() in the function documentation string.
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20211122104744.1051554-1-f4...@amsat.org>
# QEMU_LOG=unimp ip a
Unknown host QEMU_IFLA type: 22
Signed-off-by: Laurent Vivier
---
linux-user/fd-trans.c | 174 ++
1 file changed, 174 insertions(+)
diff --git a/linux-user/fd-trans.c b/linux-user/fd-trans.c
index 14c19a90b2b0..36e4a4c2aae8
Le 11/12/2021 à 03:27, Tonis Tiigi a écrit :
There seems to be difference in syscall and libc definition of these
methods and therefore musl does not implement them (1e21e78bf7). Call
syscall directly to ensure the behavior of the libc of user application,
not the libc that was used to build
Meson is planning to change the default of the "check" argument to
run_command (from false to true). Be explicit and include it in
all invocations.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Paolo Bonzini
---
docs/meson.build | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
The only difference between the two, as far as either configure or
Meson are concerned, is in the multilib flags passed to the compiler.
For QEMU, this fixes the handling of TYPE_OLDDEVT in
include/exec/user/thunk.h and enables testing of dirty ring buffer,
because both are using HOST_X86_64.
Avoid confusion between the ARCH variable of configure/config-host.mak
and the same-named variable of meson.build.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
meson.build | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
The only difference between the two, as far as either configure or
Meson are concerned, is the default endianness of the compiler.
For tests/tcg, specify the endianness explicitly on the command line;
for configure, do the same so that it is possible to have --cpu=ppc64le
on a bigendian system or
Well, the original fix 1c3dfb506ea3 did clearly improve things for me, but it
wasn't
complete yet. At some point I gave up on finding a minimal reproducer for my
remaining
problems (futex-related hangs in a complex python+bash app).
So, this *may* be the missing piece.
Will test, but that
The at24 eeproms are 2 byte devices that return 0xff when they are read
from with a partial (1-byte) address written. This distinction was
found comparing model behavior to real hardware testing.
Tested: `i2ctransfer -f -y 45 w1@85 0 r1` returns 0xff instead of next
byte
Signed-off-by: Patrick
This makes more sense, since target detection can affect CPU detection
on Solaris.
Signed-off-by: Paolo Bonzini
---
configure | 115 ++
1 file changed, 55 insertions(+), 60 deletions(-)
diff --git a/configure b/configure
index
DIRS is used to create the directory in which the LINKS symbolic links
reside, or to create directories for object files. The former can
be done directly in the symlinking loop, while the latter is done
by Meson already, so DIRS is not necessary.
Reviewed-by: Peter Maydell
Reviewed-by: Alex
The test was disabled when CONFIG_EPOLL_CREATE1 was moved out
of config-host.mak. Fix the condition.
Signed-off-by: Paolo Bonzini
---
tests/unit/meson.build | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/unit/meson.build b/tests/unit/meson.build
index
Add IFLA_PHYS_PORT_ID, IFLA_PARENT_DEV_NAME, IFLA_PARENT_DEV_BUS_NAME
# QEMU_LOG=unimp ip a
Unknown host QEMU_IFLA type: 56
Unknown host QEMU_IFLA type: 57
Unknown host QEMU_IFLA type: 34
Signed-off-by: Laurent Vivier
---
linux-user/fd-trans.c | 6 ++
1 file changed, 6
add IFLA_BRPORT_MCAST_EHT_HOSTS_LIMIT and IFLA_BRPORT_MCAST_EHT_HOSTS_CNT
# QEMU_LOG=unimp ip a
Unknown QEMU_IFLA_BRPORT type 37
Unknown QEMU_IFLA_BRPORT type 38
Signed-off-by: Laurent Vivier
---
linux-user/fd-trans.c | 4
1 file changed, 4 insertions(+)
diff --git
Le 16/11/2021 à 22:09, Philippe Mathieu-Daudé a écrit :
Linux Hexagon port doesn't define a specific 'struct stat'
but uses the generic one (see Linux commit 6103ec56c65c [*]
"asm-generic: add generic ABI headers" which predates the
introduction of the Hexagon port).
Remove the target specific
The following changes since commit 90978e15bc9a23c208b25bf7ea697a5d0925562b:
Merge tag 'trivial-branch-for-7.0-pull-request' of
https://gitlab.com/laurent_vivier/qemu into staging (2021-12-17 13:15:38 -0800)
are available in the Git repository at:
https://gitlab.com/bonzini/qemu.git
Hi Team,
I am working on a Virtio-GPU device (backend) for one of our customer
projects - we are using the Virtio-GPU driver (frontend) to drive our
device. Our device code has been written using Qemu virtio-gpu device code
as a reference. Our device is setting the resolution to 1024x768 as a
On 12/19/21 6:16 AM, Paolo Bonzini wrote:
The following changes since commit 90978e15bc9a23c208b25bf7ea697a5d0925562b:
Merge tag 'trivial-branch-for-7.0-pull-request' of
https://gitlab.com/laurent_vivier/qemu into staging (2021-12-17 13:15:38 -0800)
are available in the Git repository at:
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Message-Id: <20211210075704.23951-6-frank.ch...@sifive.com>
Signed-off-by: Alistair Francis
---
target/riscv/cpu_bits.h | 1 +
target/riscv/csr.c | 2 +-
From: Frank Chang
Replace ETYPE from signed int to unsigned int to prevent index overflow
issue, which would lead to wrong index address.
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Message-Id: <20211210075704.23951-23-frank.ch...@sifive.com>
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Message-Id: <20211210075704.23951-34-frank.ch...@sifive.com>
Signed-off-by: Alistair Francis
---
target/riscv/insn32.decode | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
From: Frank Chang
NaN-boxed the scalar floating-point register based on RVV 1.0's rules.
Signed-off-by: Frank Chang
Acked-by: Alistair Francis
Message-Id: <20211210075704.23951-39-frank.ch...@sifive.com>
Signed-off-by: Alistair Francis
---
target/riscv/internals.h| 5
From: Frank Chang
If the frm field contains an invalid rounding mode (101-111),
attempting to execute any vector floating-point instruction, even
those that do not depend on the rounding mode, will raise an illegal
instruction exception.
Call gen_set_rm() with DYN rounding mode to check and
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
Message-Id: <20211210075704.23951-73-frank.ch...@sifive.com>
Signed-off-by: Alistair Francis
---
target/riscv/insn32.decode | 2 ++
target/riscv/insn_trans/trans_rvv.c.inc | 27 +
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Message-Id: <20211210075704.23951-54-frank.ch...@sifive.com>
Signed-off-by: Alistair Francis
---
target/riscv/vector_helper.c| 12 ++--
target/riscv/insn_trans/trans_rvv.c.inc | 12 +---
2
From: Frank Chang
Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions is
moved to Section 11.4 in RVV v1.0 spec. Update the comment, no
functional changes.
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
Message-Id: <20211210075704.23951-77-frank.ch...@sifive.com>
From: Frank Chang
Implement the floating-point reciprocal square-root estimate to 7 bits
instruction.
Signed-off-by: Frank Chang
Acked-by: Alistair Francis
Message-Id: <20211210075704.23951-70-frank.ch...@sifive.com>
Signed-off-by: Alistair Francis
---
target/riscv/helper.h
On 2021/12/18 21:04, Philippe Mathieu-Daudé wrote:
qdev_connect_gpio_out_named() is described as qdev_connect_gpio_out(),
and referring to itself in an endless loop, which is confusing. Fix.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/qdev-core.h | 5 +++--
1 file changed, 3
From: Kito Cheng
Signed-off-by: Kito Cheng
Signed-off-by: Chih-Min Chao
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Acked-by: Alistair Francis
Message-id: 20211210074329.5775-4-frank.ch...@sifive.com
Signed-off-by: Alistair Francis
---
target/riscv/helper.h
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Message-Id: <20211210075704.23951-20-frank.ch...@sifive.com>
Signed-off-by: Alistair Francis
---
target/riscv/vector_helper.c| 14 +-
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Message-Id: <20211210075704.23951-10-frank.ch...@sifive.com>
Signed-off-by: Alistair Francis
---
target/riscv/cpu_bits.h | 7 +++
target/riscv/csr.c
From: Frank Chang
* Remove "vmv.s.x: dothing if rs1 == 0" constraint.
* Add vmv.x.s instruction.
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Acked-by: Alistair Francis
Message-Id: <20211210075704.23951-37-frank.ch...@sifive.com>
Signed-off-by: Alistair Francis
---
From: Frank Chang
Add the following instructions:
* vmv1r.v
* vmv2r.v
* vmv4r.v
* vmv8r.v
Signed-off-by: Frank Chang
Acked-by: Alistair Francis
Message-Id: <20211210075704.23951-40-frank.ch...@sifive.com>
Signed-off-by: Alistair Francis
---
target/riscv/insn32.decode | 4
From: Frank Chang
Implement the floating-point reciprocal estimate to 7 bits instruction.
Signed-off-by: Frank Chang
Acked-by: Alistair Francis
Message-Id: <20211210075704.23951-71-frank.ch...@sifive.com>
Signed-off-by: Alistair Francis
---
target/riscv/helper.h | 4 +
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Message-Id: <20211210075704.23951-50-frank.ch...@sifive.com>
Signed-off-by: Alistair Francis
---
target/riscv/vector_helper.c| 4
target/riscv/insn_trans/trans_rvv.c.inc | 3 ++-
2 files changed, 2
From: Frank Chang
Add the following instructions:
* vzext.vf2
* vzext.vf4
* vzext.vf8
* vsext.vf2
* vsext.vf4
* vsext.vf8
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Message-Id: <20211210075704.23951-41-frank.ch...@sifive.com>
Signed-off-by: Alistair Francis
---
On Thu, Dec 16, 2021 at 6:18 PM Philippe Mathieu-Daudé wrote:
>
> On 12/16/21 06:58, Anup Patel wrote:
> > On Thu, Dec 16, 2021 at 10:27 AM Alistair Francis
> > wrote:
> >>
> >> From: Alistair Francis
> >>
> >> Linux supports up to 32 cores for both 32-bit and 64-bit RISC-V, so
> >> let's set
From: Frank Chang
Add supports of Vector unit-stride mask load/store instructions
(vlm.v, vsm.v), which has:
evl (effective vector length) = ceil(env->vl / 8).
The new instructions operate the same as unmasked byte loads and stores.
Add evl parameter to reuse vext_ldst_us().
Signed-off-by:
On 2021/12/18 21:04, Philippe Mathieu-Daudé wrote:
qdev_init_gpio_out_named() is described as qdev_init_gpio_out(),
and referring to itself in an endless loop, which is confusing. Fix.
Reported-by: Yanan Wang
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/qdev-core.h | 2 +-
1 file
From: Alistair Francis
The following changes since commit 212a33d3b0c65ae2583bb1d06cb140cd0890894c:
Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging
(2021-12-19 16:36:10 -0800)
are available in the Git repository at:
g...@github.com:alistair23/qemu.git
From: Kito Cheng
Signed-off-by: Kito Cheng
Signed-off-by: Chih-Min Chao
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Message-id: 20211210074329.5775-2-frank.ch...@sifive.com
Signed-off-by: Alistair Francis
---
target/riscv/cpu.h| 1 +
From: Kito Cheng
Signed-off-by: Kito Cheng
Signed-off-by: Chih-Min Chao
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Message-id: 20211210074329.5775-6-frank.ch...@sifive.com
Signed-off-by: Alistair Francis
---
target/riscv/helper.h
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
Message-id: 20211210074329.5775-9-frank.ch...@sifive.com
Signed-off-by: Alistair Francis
---
target/riscv/cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index
From: Frank Chang
* Add fp16 nan-box check generator function, if a 16-bit input is not
properly nanboxed, then the input is replaced with the default qnan.
* Add do_nanbox() helper function to utilize gen_check_nanbox_X() to
generate the NaN-boxed floating-point values based on SEW setting.
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
Message-Id: <20211210075704.23951-21-frank.ch...@sifive.com>
Signed-off-by: Alistair Francis
---
target/riscv/helper.h | 129 ++--
target/riscv/insn32.decode | 43 ++-
From: Frank Chang
As in RVV 1.0 design, MLEN is hardcoded with value 1 (Section 4.5).
Thus, remove all MLEN related calculations.
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Message-Id: <20211210075704.23951-13-frank.ch...@sifive.com>
From: Frank Chang
Update check functions with RVV 1.0 rules.
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
Message-Id: <20211210075704.23951-16-frank.ch...@sifive.com>
Signed-off-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvv.c.inc | 715 +---
1
From: Frank Chang
Vector AMOs are removed from standard vector extensions. Will be added
later as separate Zvamo extension, but will need a different encoding
from earlier proposal.
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
Message-Id:
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Message-Id: <20211210075704.23951-29-frank.ch...@sifive.com>
Signed-off-by: Alistair Francis
---
target/riscv/insn32.decode | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Message-Id: <20211210075704.23951-31-frank.ch...@sifive.com>
Signed-off-by: Alistair Francis
---
target/riscv/helper.h | 2 +-
target/riscv/insn32.decode
From: Frank Chang
For some vector instructions (e.g. vmv.s.x), the element is loaded with
sign-extended.
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Message-Id: <20211210075704.23951-35-frank.ch...@sifive.com>
Signed-off-by: Alistair Francis
---
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Message-Id: <20211210075704.23951-49-frank.ch...@sifive.com>
Signed-off-by: Alistair Francis
---
target/riscv/vector_helper.c | 9 -
1 file changed, 9 deletions(-)
diff --git a/target/riscv/vector_helper.c
From: Frank Chang
Add the following instructions:
* vaaddu.vv
* vaaddu.vx
* vasubu.vv
* vasubu.vx
Remove the following instructions:
* vadd.vi
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Message-Id: <20211210075704.23951-42-frank.ch...@sifive.com>
Signed-off-by: Alistair
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Message-Id: <20211210075704.23951-61-frank.ch...@sifive.com>
Signed-off-by: Alistair Francis
---
target/riscv/internals.h| 9 +
target/riscv/fpu_helper.c | 12 ++--
From: Kito Cheng
Signed-off-by: Kito Cheng
Signed-off-by: Chih-Min Chao
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Message-id: 20211210074329.5775-3-frank.ch...@sifive.com
Signed-off-by: Alistair Francis
---
target/riscv/helper.h
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Message-Id: <20211210075704.23951-4-frank.ch...@sifive.com>
Signed-off-by: Alistair Francis
---
target/riscv/cpu.h| 2 ++
target/riscv/cpu_bits.h |
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Message-Id: <20211210075704.23951-5-frank.ch...@sifive.com>
Signed-off-by: Alistair Francis
---
target/riscv/csr.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/csr.c
From: Frank Chang
Immediate value in translator function is extended not only
zero-extended and sign-extended but with more modes to be applicable
with multiple formats of vector instructions.
* IMM_ZX: Zero-extended
* IMM_SX: Sign-extended
* IMM_TRUNC_SEW: Truncate to log(SEW)
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Message-Id: <20211210075704.23951-24-frank.ch...@sifive.com>
Signed-off-by: Alistair Francis
---
target/riscv/helper.h | 26 ++---
target/riscv/insn32.decode
From: Frank Chang
* Only do carry-in or borrow-in if is masked (vm=0).
* Remove clear function from helper functions as the tail elements
are unchanged in RVV 1.0.
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
Message-Id: <20211210075704.23951-44-frank.ch...@sifive.com>
From: Frank Chang
Update vext_get_vlmax() and MAXSZ() to take fractional LMUL into
calculation for RVV 1.0.
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Message-Id: <20211210075704.23951-27-frank.ch...@sifive.com>
Signed-off-by: Alistair Francis
From: Hsiangkai Wang
Signed-off-by: Hsiangkai Wang
Signed-off-by: Greentime Hu
Signed-off-by: Frank Chang
Acked-by: Alistair Francis
Message-Id: <20211210075704.23951-69-frank.ch...@sifive.com>
Signed-off-by: Alistair Francis
---
target/riscv/cpu.h | 1 +
target/riscv/cpu.c | 2
From: Frank Chang
* Sign-extend vmselu.vi and vmsgtu.vi immediate values.
* Remove "set tail elements to zeros" as tail elements can be unchanged
for either VTA to have undisturbed or agnostic setting.
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Message-Id:
From: Frank Chang
log(SEW) truncate vssra.vi immediate value.
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Message-Id: <20211210075704.23951-56-frank.ch...@sifive.com>
Signed-off-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvv.c.inc | 4 ++--
1 file changed, 2
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Message-Id: <20211210075704.23951-55-frank.ch...@sifive.com>
Signed-off-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvv.c.inc | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git
From: Frank Chang
Signed-off-by: Frank Chang
Acked-by: Alistair Francis
Message-Id: <20211210075704.23951-65-frank.ch...@sifive.com>
Signed-off-by: Alistair Francis
---
target/riscv/helper.h | 22 -
target/riscv/insn32.decode | 15 ---
From: Frank Chang
Add the following instructions:
* vfslide1up.vf
* vfslide1down.vf
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
Message-Id: <20211210075704.23951-52-frank.ch...@sifive.com>
Signed-off-by: Alistair Francis
---
target/riscv/helper.h | 7 ++
From: Vineet Gupta
The bitmanip extension has now been ratified [1] and upstream tooling
(gcc/binutils) support it too, so move them out of experimental and also
enable by default (for better test exposure/coverage)
[1] https://wiki.riscv.org/display/TECH/Recently+Ratified+Extensions
From: Frank Chang
NaN-boxed the scalar floating-point register based on RVV 1.0's rules.
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
Message-Id: <20211210075704.23951-38-frank.ch...@sifive.com>
Signed-off-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvv.c.inc | 16
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
Message-Id: <20211210075704.23951-66-frank.ch...@sifive.com>
Signed-off-by: Alistair Francis
---
target/riscv/cpu.h | 2 +-
target/riscv/vector_helper.c| 2 +-
On Fri, Dec 17, 2021 at 4:35 PM Stefan Hajnoczi wrote:
>
> On Fri, Dec 17, 2021 at 12:26:53PM +0800, Jason Wang wrote:
>
> Dave: You created the VIRTIO vmstate infrastructure in QEMU. Please see
> the bottom of this email about moving to a standard VIRTIO device
> save/load format defined by the
From: Frank Chang
Add the following instructions:
* vlre.v
* vsr.v
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
Message-Id: <20211210075704.23951-25-frank.ch...@sifive.com>
Signed-off-by: Alistair Francis
---
target/riscv/helper.h | 21
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
Message-Id: <20211210075704.23951-22-frank.ch...@sifive.com>
Signed-off-by: Alistair Francis
---
target/riscv/helper.h | 67 +++
target/riscv/insn32.decode | 21 +++--
From: Frank Chang
* Add vrgatherei16.vv instruction.
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
Message-Id: <20211210075704.23951-36-frank.ch...@sifive.com>
Signed-off-by: Alistair Francis
---
target/riscv/helper.h | 4
target/riscv/insn32.decode
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
Message-Id: <20211210075704.23951-26-frank.ch...@sifive.com>
Signed-off-by: Alistair Francis
---
target/riscv/vector_helper.c| 99 ++---
target/riscv/insn_trans/trans_rvv.c.inc | 32
From: Frank Chang
* Remove clear function from helper functions as the tail elements
are unchanged in RVV 1.0.
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Message-Id: <20211210075704.23951-51-frank.ch...@sifive.com>
Signed-off-by: Alistair Francis
---
From: Frank Chang
Truncate vsll.vi, vsrl.vi, vsra.vi's immediate values to lg2(SEW) bits.
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Message-Id: <20211210075704.23951-43-frank.ch...@sifive.com>
Signed-off-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvv.c.inc | 6
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Message-Id: <20211210075704.23951-28-frank.ch...@sifive.com>
Signed-off-by: Alistair Francis
---
target/riscv/insn32.decode | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Message-Id: <20211210075704.23951-30-frank.ch...@sifive.com>
Signed-off-by: Alistair Francis
---
target/riscv/helper.h | 2 +-
target/riscv/insn32.decode
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Message-Id: <20211210075704.23951-46-frank.ch...@sifive.com>
Signed-off-by: Alistair Francis
---
target/riscv/insn32.decode | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Message-Id: <20211210075704.23951-53-frank.ch...@sifive.com>
Signed-off-by: Alistair Francis
---
target/riscv/helper.h | 24 ++--
target/riscv/insn32.decode | 12 +++---
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Message-Id: <20211210075704.23951-60-frank.ch...@sifive.com>
Signed-off-by: Alistair Francis
---
target/riscv/vector_helper.c | 24
1 file changed, 12 insertions(+), 12 deletions(-)
diff
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Message-Id: <20211210075704.23951-57-frank.ch...@sifive.com>
Signed-off-by: Alistair Francis
---
target/riscv/helper.h | 22 ---
target/riscv/insn32.decode | 7 -
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