On 1/7/22 10:56 AM, matheus.fe...@eldorado.org.br wrote:
From: Luis Pires
New macros that add FLAGS and FLAGS2 checking were added for
both TRANS and TRANS64.
Signed-off-by: Luis Pires
[ferst: - TRANS_FLAGS2 instead of TRANS_FLAGS_E
- Use the new macros in load/store vector insns ]
In the case that size1 was zero, because of the explicit
'end1 > addr' check, the range check would fail and the error
message would read as shown below. The correct comparison
is 'end1 >= addr' (or 'addr <= end1').
EDU: DMA range 0x4-0x3 out of bounds (0x4-0x3)!
At the opposite
In the case that size1 was zero, because of the explicit
'end1 > addr' check, the range check would fail and the error
message would read as shown below. The correct comparison
is 'end1 >= addr' (or 'addr <= end1').
EDU: DMA range 0x4-0x3 out of bounds (0x4-0x3)!
At the opposite
Hi,
On 1/7/22 15:59, gaosong wrote:
Hi Richard.
On 2022/1/7 下午1:01, Richard Henderson wrote:
On 1/6/22 1:41 AM, Song Gao wrote:
Based-on:<20220106074740.1754661-1-gaos...@loongson.cn>
Hi all,
This series only support linux-user emulation.
More about LoongArch at:https://github.com/loongson/
Hi,
Spice clients that are running directly on the host system have
pratcially unlimited bandwidth so to reduce latency allow the user to
configure the buffer_length to a lower value if desired.
While virt-viewer can not take advantage of this, the PureSpice [1]
library used by Looking Glass
Spice clients that are running directly on the host system have
pratcially unlimited bandwidth so to reduce latency allow the user to
configure the buffer_length to a lower value if desired.
While virt-viewer can not take advantage of this, the PureSpice [1]
library used by Looking Glass [2] is
Hi,
From: Cindy Lu
Add support for configure interrupt, The process is used kvm_irqfd_assign
to set the gsi to kernel. When the configure notifier was signal by
host, qemu will inject a msix interrupt to guest
Signed-off-by: Cindy Lu
Message-Id: <20211104164827.21911-11-l...@redhat.com>
Le 08/01/2022 à 19:04, Mark Cave-Ayland a écrit :
Commit a9431a03f7 ("target/m68k: add M68K_FEATURE_UNALIGNED_DATA feature") added
a new feature for processors from the 68020 onwards which do not require data
accesses to be word aligned.
Unfortunately the original commit missed an additional
On 1/8/22 16:09, Ard Biesheuvel wrote:
> When running under KVM, we may decide to run the CPU in 32-bit mode, by
> setting the 'aarch64=off' CPU option. In this case, we need to switch to
> the 32-bit version of the GDB stub too, so that GDB has the correct view
> of the CPU state. Without this,
'wp_groups' holds a bitmap, rename it as 'wp_group_bmap'.
'wpgrps_size' is the bitmap size (in bits), rename it as
'wp_group_bits'.
Patch created mechanically using:
$ sed -i -e s/wp_groups/wp_group_bmap/ \
-e s/wpgrps_size/wp_group_bits/ hw/sd/sd.c
Signed-off-by: Philippe
at:
https://github.com/philmd/qemu.git tags/sdmmc-20220108
for you to fetch changes up to b66f73a0cb312c81470433dfd5275d2824bb89de:
hw/sd: Add SDHC support for SD card SPI-mode (2022-01-04 08:50:28 +0100)
SD/MMC patches queue
From: Frank Chang
In SPI-mode, SD card's OCR register: Card Capacity Status (CCS) bit
is not set to 1 correclty when the assigned SD image size is larger
than 2GB (SDHC). This will cause the SD card to be indentified as SDSC
incorrectly. CCS bit should be set to 1 if we are using SDHC.
Also, as
The following changes since commit 7d4ae4d4978079d564d3b6354c90a949130409fe:
Merge tag 'pull-request-2022-01-05' of https://gitlab.com/thuth/qemu into
staging (2022-01-05 08:47:18 -0800)
are available in the Git repository at:
g...@gitlab.com:bsdimp/qemu.git tags/bsd-user-arm-pull-request
Move the current inline functions into sigal.c. This will increate the
flexibility of implementation in the future.
Signed-off-by: Warner Losh
Reviewed-by: Richard Henderson
---
bsd-user/x86_64/signal.c | 56 +++-
bsd-user/x86_64/target_arch_signal.h | 43
Signed-off-by: Warner Losh
Reviewed-by: Richard Henderson
---
bsd-user/i386/target_arch_signal.h | 9 +
1 file changed, 1 insertion(+), 8 deletions(-)
diff --git a/bsd-user/i386/target_arch_signal.h
b/bsd-user/i386/target_arch_signal.h
index e262667bdab..bf7263c4f8d 100644
---
Implement the system call dispatch. This implements all three kinds of
system call: direct and the two indirect variants. It handles all the
special cases for thumb as well.
Signed-off-by: Stacey Son
Signed-off-by: Kyle Evans
Signed-off-by: Warner Losh
Reviewed-by: Kyle Evans
Reviewed-by:
Now that all architecutres define TARGET_[MU]CONTEXT_SIZE, enforce
requiring them and always check the sizeof target_{u,m}context_t
sizes.
Signed-off-by: Warner Losh
Reviewed-by: Richard Henderson
---
bsd-user/freebsd/target_os_ucontext.h | 2 --
1 file changed, 2 deletions(-)
diff --git
Implement get_elf_hwcap to get the first word of hardware capabilities.
Signed-off-by: Kyle Evans
Signed-off-by: Stacey Son
Signed-off-by: Warner Losh
Reviewed-by: Kyle Evans
Reviewed-by: Richard Henderson
---
bsd-user/arm/target_arch_elf.h | 72 +-
1 file
Update ucontext to implement sigreturn.
Signed-off-by: Stacey Son
Signed-off-by: Warner Losh
Reviewed-by: Richard Henderson
---
bsd-user/arm/signal.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/bsd-user/arm/signal.c b/bsd-user/arm/signal.c
index fb6228db6cf..1478f008d13
Copy of the signal trampoline code for arm, as well as setup_sigtramp to
write it to the stack.
Signed-off-by: Stacey Son
Signed-off-by: Warner Losh
Reviewed-by: Kyle Evans
Reviewed-by: Richard Henderson
---
bsd-user/arm/target_arch_sigtramp.h | 49 +
1 file
CC: Paolo Bonzini
Signed-off-by: Warner Losh
Acked-by: Kyle Evans
Reviewed-by: Richard Henderson
---
configs/targets/arm-bsd-user.mak | 2 ++
1 file changed, 2 insertions(+)
create mode 100644 configs/targets/arm-bsd-user.mak
diff --git a/configs/targets/arm-bsd-user.mak
- We write a very minimal softmmu harness.
- This is a very simple smoke test with no need to run a full Linux/kernel.
- The Makefile.softmmu-target record the rule to run.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
tests/tcg/loongarch64/Makefile.softmmu-target | 33 +++
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
configs/targets/loongarch64-softmmu.mak | 1 +
gdb-xml/loongarch-base64.xml| 43 +++
gdb-xml/loongarch-fpu64.xml | 57 +++
target/loongarch/cpu.c | 7 ++
This patch introduces basic TLB interfaces.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
target/loongarch/cpu-param.h | 2 +-
target/loongarch/cpu.c| 32
target/loongarch/cpu.h| 45 -
target/loongarch/internals.h | 10 ++
target/loongarch/machine.c
This includes:
-CACOP
-LDDIR
-LDPTE
-ERTN
-DBCL
-IDLE
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
target/loongarch/cpu.h | 2 +
target/loongarch/disas.c | 17
target/loongarch/helper.h| 4 +
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
hw/loongarch/Kconfig | 4
hw/loongarch/fw_cfg.c| 33 ++
hw/loongarch/fw_cfg.h| 15 ++
hw/loongarch/loongson3.c | 35
Add tree nodes for 3A5000 device tree.
- cpu nodes;
- fw_cfg nodes;
- pcie nodes.
The lastest loongarch bios have supported fdt.
- https://github.com/loongson/edk2
- https://github.com/loongson/edk2-platforms
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
hw/loongarch/loongson3.c
This patch realize the PCH-PIC interrupt controller.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
hw/intc/Kconfig | 4 +
hw/intc/loongarch_pch_pic.c | 428
hw/intc/meson.build | 1 +
hw/intc/trace-events
Get the machine context from the CPU state.
Signed-off-by: Stacey Son
Signed-off-by: Kyle Evans
Signed-off-by: Warner Losh
Reviewed-by: Richard Henderson
---
bsd-user/arm/signal.c | 51 +++
1 file changed, 51 insertions(+)
diff --git
Implement the extended HW capabilities for HWCAP2.
Signed-off-by: Kyle Evans
Signed-off-by: Warner Losh
Reviewed-by: Kyle Evans
Reviewed-by: Richard Henderson
---
bsd-user/arm/target_arch_elf.h | 22 ++
1 file changed, 22 insertions(+)
diff --git
Implement EXCP_PREFETCH_ABORT AND EXCP_DATA_ABORT. Both of these data
exceptions cause a SIGSEGV.
Signed-off-by: Kyle Evans
Signed-off-by: Olivier Houchard
Signed-off-by: Stacey Son
Signed-off-by: Warner Losh
Reviewed-by: Kyle Evans
Reviewed-by: Richard Henderson
---
This series patch add softmmu support for LoongArch.
Base on the linux-user emulation support V14 patch.
* https://patchew.org/QEMU/20220106094200.1801206-1-gaos...@loongson.cn/
The latest kernel:
* https://github.com/loongson/linux/tree/loongarch-next
The latest uefi:
*
This includes:
- TLBSRCH
- TLBRD
- TLBWR
- TLBFILL
- TLBCLR
- TLBFLUSH
- INVTLB
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 17 +
target/loongarch/helper.h| 12 +
target/loongarch/insn_trans/trans_core.c.inc |
This includes:
- CSRRD
- CSRWR
- CSRXCHG
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
target/loongarch/cpu.h | 88 +
target/loongarch/csr_helper.c| 112 +
target/loongarch/disas.c | 15 +++
This patch realize the IPI interrupt controller.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
hw/intc/Kconfig | 3 +
hw/intc/loongarch_ipi.c | 164
hw/intc/meson.build | 1 +
hw/intc/trace-events|
This patch add ls7a rtc device support.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
hw/loongarch/Kconfig | 1 +
hw/loongarch/loongson3.c | 4 +
hw/rtc/Kconfig | 3 +
hw/rtc/ls7a_rtc.c | 322 +
On 1/8/22 07:36, Richard Henderson wrote:
> In tcg_out_qemu_ld/st, we already check for guest_base matching int16_t.
> Mirror that when setting up TCG_GUEST_BASE_REG in the prologue.
>
> Signed-off-by: Richard Henderson
> ---
> tcg/mips/tcg-target.c.inc | 2 +-
> 1 file changed, 1 insertion(+),
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
hw/loongarch/loongson3.c | 81
include/hw/loongarch/loongarch.h | 5 ++
2 files changed, 86 insertions(+)
diff --git a/hw/loongarch/loongson3.c b/hw/loongarch/loongson3.c
index
This patch add the irq hierarchy for the virt board.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
hw/loongarch/loongson3.c | 85 ++
include/hw/pci-host/ls7a.h | 13 ++
2 files changed, 98 insertions(+)
diff --git a/hw/loongarch/loongson3.c
+ object_property_set_int(OBJECT(phb), "index",
+ phb->phb_id, _abort);
+
+ pnv_phb4_set_stack_phb_props(stack, phb);
+
+ /* Assign the phb to the stack */
+ stack->phb = phb;
The stack object should check the validity of the stack->phb
target_arch_cpu.h is for CPU loop definitions. Create the file and
define target_cpu_init and target_cpu_reset for arm.
Signed-off-by: Olivier Houchard
Signed-off-by: Stacey Son
Signed-off-by: Warner Losh
Reviewed-by: Kyle Evans
Reviewed-by: Richard Henderson
---
In FreeBSD, sigcontext was retired in favor of ucontext/mcontext.
Remove vestigial target_sigcontext.
Signed-off-by: Warner Losh
Reviewed-by: Richard Henderson
---
bsd-user/i386/target_arch_signal.h | 4
1 file changed, 4 deletions(-)
diff --git a/bsd-user/i386/target_arch_signal.h
Implement the register copying routines to extract registers from the
cpu for core dump generation.
Signed-off-by: Stacey Son
Signed-off-by: Warner Losh
Reviewed-by: Kyle Evans
Reviewed-by: Richard Henderson
---
bsd-user/arm/target_arch_reg.h | 60 ++
1 file
Add a boiler plate CPU loop that does nothing except return an error for
all traps.
Signed-off-by: Sean Bruno
Signed-off-by: Stacey Son
Signed-off-by: Warner Losh
Reviewed-by: Kyle Evans
Reviewed-by: Richard Henderson
---
bsd-user/arm/target_arch_cpu.h | 22 ++
1 file
Move the (now stubbed out) inlines into bsd-user/i386/signal.c.
Signed-off-by: Warner Losh
Reviewed-by: Richard Henderson
---
bsd-user/i386/signal.c | 56 +-
bsd-user/i386/target_arch_signal.h | 43 +--
2 files changed, 63
Implement set_sigtramp_args to setup the arguments to the sigtramp
calls.
Signed-off-by: Stacey Son
Signed-off-by: Warner Losh
Reviewed-by: Richard Henderson
---
bsd-user/arm/signal.c | 60 +++
1 file changed, 60 insertions(+)
create mode 100644
Target specific TLS routines to get and set the TLS values.
Signed-off-by: Kyle Evans
Signed-off-by: Stacey Son
Signed-off-by: Warner Losh
Reviewed-by: Kyle Evans
Reviewed-by: Richard Henderson
---
bsd-user/arm/target_arch.h | 28
bsd-user/arm/target_arch_cpu.c
Implement EXCP_UDEF, EXCP_DEBUG, EXCP_INTERRUPT, EXCP_ATOMIC and
EXCP_YIELD. The first two generate a signal to the emulated
binary. EXCP_ATOMIC handles atomic operations. The remainder are fancy
nops.
Signed-off-by: Stacey Son
Signed-off-by: Mikaël Urankar
Signed-off-by: Kyle Evans
This includes:
- IOCSR{RD/WR}.{B/H/W/D}
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
target/loongarch/cpu.c | 8 ++
target/loongarch/cpu.h | 4 +
target/loongarch/disas.c | 8 ++
target/loongarch/helper.h
This patch introduce qmp_query_cpu_definitions interface.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
Reviewed-by: Richard Henderson
---
qapi/machine-target.json | 6 --
target/loongarch/cpu.c | 26 ++
2 files changed, 30 insertions(+), 2 deletions(-)
Loongson-3A5000 support 14 interrupts from 64 - 77(Timer->75 IPI->76)
Loongson-3A5000 and ls7a form a legacy model and extended model irq
hierarchy.Tcg mode emulate a simplified extended model which
has no Legacy I/O Interrupt Controller(LIOINTC) and LPC.
e.g:
|+-++-+
1.This patch Add loongarch interrupt and exception handle.
2.Rename the user excp to the exccode from the csr defintions.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
linux-user/loongarch64/cpu_loop.c | 8 +-
target/loongarch/cpu.c| 252
Emulate a 3A5000 board use the new loongarch instruction.
3A5000 belongs to the Loongson3 series processors.
The board consists of a 3A5000 cpu model and the 7A1000
bridge. The host 3A5000 board is really complicated and
contains many functions.Now for the tcg softmmu mode
only part functions are
This patch realize the EIOINTC interrupt controller.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
hw/intc/Kconfig| 3 +
hw/intc/loongarch_extioi.c | 376 +
hw/intc/meson.build| 1 +
hw/intc/trace-events
The preferred name for the 32-bit arm is now armv7. Update the name to
reflect that. In addition, add Stacey's copyright to this file and
update the include guards to the new convention.
Signed-off-by: Stacey Son
Signed-off-by: Warner Losh
Reviewed-by: Kyle Evans
Reviewed-by: Richard Henderson
In tcg_out_qemu_ld/st, we already check for guest_base matching int16_t.
Mirror that when setting up TCG_GUEST_BASE_REG in the prologue.
Signed-off-by: Richard Henderson
---
tcg/mips/tcg-target.c.inc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tcg/mips/tcg-target.c.inc
As part of upstreaming, the include guards have been made more
consistent. Update this file to use the new guards.
Signed-off-by: Warner Losh
Reviewed-by: Kyle Evans
Reviewed-by: Richard Henderson
---
bsd-user/arm/target_arch_sysarch.h | 6 +++---
1 file changed, 3 insertions(+), 3
Emit all 32-bit signed constants, which can be loaded in two insns.
Signed-off-by: Richard Henderson
---
tcg/mips/tcg-target.c.inc | 35 ---
1 file changed, 24 insertions(+), 11 deletions(-)
diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
Signed-off-by: Warner Losh
Reviewed-by: Richard Henderson
---
bsd-user/x86_64/target_arch_signal.h | 9 +
1 file changed, 1 insertion(+), 8 deletions(-)
diff --git a/bsd-user/x86_64/target_arch_signal.h
b/bsd-user/x86_64/target_arch_signal.h
index 55f742b0a8c..e84aff948c5 100644
---
Signed-off-by: Stacey Son
Signed-off-by: Kyle Evans
Signed-off-by: Warner Losh
Reviewed-by: Richard Henderson
---
bsd-user/arm/target_arch_signal.h | 28
1 file changed, 28 insertions(+)
diff --git a/bsd-user/arm/target_arch_signal.h
Implement target_thread_init (to create a thread) and target_set_upcall
(to switch to a thread) for arm.
Signed-off-by: Stacey Son
Signed-off-by: Kyle Evans
Signed-off-by: Warner Losh
Reviewed-by: Kyle Evans
---
bsd-user/arm/target_arch_thread.h | 82 +++
1 file
Implement target_cpu_clone_regs to clone the resister state on a fork.
Signed-off-by: Stacey Son
Signed-off-by: Warner Losh
Reviewed-by: Kyle Evans
Reviewed-by: Richard Henderson
---
bsd-user/arm/target_arch_cpu.h | 8
1 file changed, 8 insertions(+)
diff --git
Move the machine context to the CPU state.
Signed-off-by: Stacey Son
Signed-off-by: Kyle Evans
Signed-off-by: Warner Losh
Reviewed-by: Richard Henderson
---
bsd-user/arm/signal.c | 76 +++
1 file changed, 76 insertions(+)
diff --git
1.Define All the CSR registers and its field.
2.Set some default csr values.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
target/loongarch/cpu-csr.h | 236 +
target/loongarch/cpu.c | 35 ++
target/loongarch/cpu.h | 57 +
3
This patch introduce vmstate_loongarch_cpu
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
Reviewed-by: Richard Henderson
---
target/loongarch/cpu.c | 3 ++
target/loongarch/internals.h | 4 ++
target/loongarch/machine.c | 84
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
hw/loongarch/Kconfig | 1 +
hw/loongarch/loongson3.c | 40
include/hw/loongarch/loongarch.h | 1 +
3 files changed, 42 insertions(+)
diff --git a/hw/loongarch/Kconfig
This is a model of the PCIe Host Bridge found on a Loongson-5000
processor. It includes a interrupt controller, some interface for
pci and nonpci devices. Mainly emulate part of it that is not
exactly the same as the host and only use part devices for
tcg mode. It support for MSI and MSIX
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
target/loongarch/constant_timer.c | 63 +++
target/loongarch/cpu.c| 9 +
target/loongarch/cpu.h| 10 +
target/loongarch/meson.build | 1 +
4 files changed, 83
This includes:
-RDTIME{L/H}.W
-RDTIME.D
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
target/loongarch/helper.h | 1 +
target/loongarch/insn_trans/trans_extra.c.inc | 32 +++
target/loongarch/op_helper.c | 6
Hi,Mark:
Sorry for the late reply. I just saw the mail after I send the v4 patch. I
sorted the mail into different folders from
the qemu-devel, so I didn't see the mail in time. Sorry again.
Xiaojuan
On 12/23/2021 06:21 PM, Mark Cave-Ayland wrote:
> On 22/12/2021 02:38, yangxiaojuan wrote:
>
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
softmmu/qdev-monitor.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/softmmu/qdev-monitor.c b/softmmu/qdev-monitor.c
index 01f3834db5..49491d74a1 100644
--- a/softmmu/qdev-monitor.c
+++ b/softmmu/qdev-monitor.c
@@
FreeBSD has a MI ucontext structure that contains the MD mcontext
machine state and other things that are machine independent. Create an
include file for all the ucontext stuff. It needs to be included in the
arch specific files after target_mcontext is defined. This is largely
copied from
Various parameters describing the layout of the ARM address space. In
addition, define routines to get the stack pointer and to set the second
return value.
Signed-off-by: Stacey Son
Signed-off-by: Kyle Evans
Signed-off-by: Warner Losh
Reviewed-by: Kyle Evans
Reviewed-by: Richard Henderson
Switch to the CPUArchState typedef and move target-provided prototypes
to target_os_ucontext.h.
Signed-off-by: Warner Losh
Reviewed-by: Richard Henderson
---
bsd-user/freebsd/target_os_ucontext.h | 11 +++
bsd-user/i386/target_arch_signal.h| 9 -
Define the native sizes of mcontext_t and ucontext_t so that the tests
in target_os_ucontext.h ensure the size of arm's version of these
structures is correct.
Signed-off-by: Warner Losh
Reviewed-by: Richard Henderson
---
bsd-user/arm/target_arch_signal.h | 3 +++
1 file changed, 3
Basic set of defines needed for arm ELF file activation.
Signed-off-by: Stacey Son
Signed-off-by: Warner Losh
Reviewed-by: Kyle Evans
Reviewed-by: Richard Henderson
---
bsd-user/arm/target_arch_elf.h | 36 ++
1 file changed, 36 insertions(+)
create mode
Defines for registers and stack layout related to signals.
Signed-off-by: Stacey Son
Signed-off-by: Warner Losh
Reviewed-by: Kyle Evans
Reviewed-by: Richard Henderson
---
bsd-user/arm/target_arch_signal.h | 57 +++
1 file changed, 57 insertions(+)
create mode
Mainly introduce how to run the softmmu
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
target/loongarch/README | 25 +
1 file changed, 25 insertions(+)
diff --git a/target/loongarch/README b/target/loongarch/README
index d5780c5918..337ba55f33 100644
---
1.Add uart,virtio-net,vga and usb for 3A5000.
2.Add irq set and map for the pci host. Non pci device
use irq 0-16, pci device use 16-64.
3.Add some unimplented device to emulate guest unused
memory space.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
hw/loongarch/Kconfig | 7
This patch realize PCH-MSI interrupt controller.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
hw/intc/Kconfig | 5 ++
hw/intc/loongarch_pch_msi.c | 75 +
hw/intc/meson.build | 1 +
hw/intc/trace-events
Add a simple acpi model for LoongArch cpu
More complex functions will be added later
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
hw/acpi/Kconfig | 4 +
hw/acpi/ls7a.c | 374 ++
hw/acpi/meson.build | 1 +
When running under KVM, we may decide to run the CPU in 32-bit mode, by
setting the 'aarch64=off' CPU option. In this case, we need to switch to
the 32-bit version of the GDB stub too, so that GDB has the correct view
of the CPU state. Without this, GDB debugging does not work at all, and
errors
On Wed, Jan 5, 2022 at 9:01 AM Frank Chang wrote:
>
> Anup Patel 於 2021年12月30日 週四 下午8:53寫道：
>>
>> From: Anup Patel
>>
>> The AIA specification defines IMSIC interface CSRs for easy access
>> to the per-HART IMSIC registers without using indirect xiselect and
>> xireg CSRs. This patch implements
On Fri, Jan 7, 2022 at 2:23 PM Frank Chang wrote:
>
> Anup Patel 於 2021年12月30日 週四 下午8:55寫道：
>>
>> From: Anup Patel
>>
>> The RISC-V AIA (Advanced Interrupt Architecture) defines a new
>> interrupt controller for wired interrupts called APLIC (Advanced
>> Platform Level Interrupt Controller).
Le 08/01/2022 à 17:41, Mark Cave-Ayland a écrit :
The macfb VRAM memory region was configured with coalescing rather than dirty
memory logging enabled, causing some areas of the screen not to redraw after
a full screen update.
Signed-off-by: Mark Cave-Ayland
Fixes: 8ac919a065 ("hw/m68k: add
On Sat, Jan 8, 2022 at 12:05 PM Frank Chang wrote:
>
> Anup Patel 於 2021年12月30日 週四 下午8:55寫道：
>>
>> From: Anup Patel
>>
>> The RISC-V AIA (Advanced Interrupt Architecture) defines a new
>> interrupt controller for wired interrupts called APLIC (Advanced
>> Platform Level Interrupt Controller).
On 1/8/22 08:11, Cédric Le Goater wrote:
+ object_property_set_int(OBJECT(phb), "index",
+ phb->phb_id, _abort);
+
+ pnv_phb4_set_stack_phb_props(stack, phb);
+
+ /* Assign the phb to the stack */
+ stack->phb = phb;
The stack
On 2022-01-07 20:23, Richard Henderson wrote:
On 1/7/22 7:01 AM, Marc Zyngier wrote:
@@ -1380,17 +1380,10 @@ void arm_cpu_finalize_features(ARMCPU *cpu,
Error **errp)
return;
}
-/*
- * KVM does not support modifications to this feature.
- * We
Signed-off-by: Dmitry Petrov
---
ui/gtk.c | 54 ++
1 file changed, 42 insertions(+), 12 deletions(-)
diff --git a/ui/gtk.c b/ui/gtk.c
index 6a1f65d518..a8567b9ddc 100644
--- a/ui/gtk.c
+++ b/ui/gtk.c
@@ -968,33 +968,63 @@ static gboolean
This change adds support for horizontal scroll to ps/2 mouse device
code. The code is implemented to match the logic of linux kernel
which is used as a reference.
Signed-off-by: Dmitry Petrov
---
hw/input/ps2.c | 57 +++---
qapi/ui.json | 2 +-
2
Hi Daniel,
Thanks for the link! I've sent a v4 patch with a cover letter that includes
it as well
as the latest comments by Marc-André to v2 of the patch.
Kind regards, Dmitry
On Tue, 4 Jan 2022 at 13:30, Daniel P. Berrangé wrote:
> On Wed, Dec 22, 2021 at 02:06:43AM +0100, Dmitry Petrov
Signed-off-by: Dmitry Petrov
---
ui/sdl2.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/ui/sdl2.c b/ui/sdl2.c
index 0bd30504cf..46a252d7d9 100644
--- a/ui/sdl2.c
+++ b/ui/sdl2.c
@@ -33,6 +33,7 @@
#include "sysemu/runstate-action.h"
#include "sysemu/sysemu.h"
#include
This patchset adds implements passing horizontal scroll
events from the host system to guest systems via ps/2
mouse device.
This is useful during testing horizontal scroll behaviour
in guest operating systems as well as using it in case it
provides any benefits for a particular application.
The
Signed-off-by: Dmitry Petrov
---
ui/cocoa.m | 18 --
1 file changed, 12 insertions(+), 6 deletions(-)
diff --git a/ui/cocoa.m b/ui/cocoa.m
index 69745c483b..ac18e14ce0 100644
--- a/ui/cocoa.m
+++ b/ui/cocoa.m
@@ -970,21 +970,27 @@ QemuCocoaView *cocoaView;
*/
This code seems to be used by vmport hack, passing these values allows
to implement horizontal scroll support even when using vmport.
In case it's not supported horizontal scroll will act as a vertical one.
Signed-off-by: Dmitry Petrov
---
ui/input-legacy.c | 15 +++
1 file changed,
The macfb VRAM memory region was configured with coalescing rather than dirty
memory logging enabled, causing some areas of the screen not to redraw after
a full screen update.
Signed-off-by: Mark Cave-Ayland
Fixes: 8ac919a065 ("hw/m68k: add Nubus macfb video card")
---
hw/display/macfb.c | 2
Le 07/01/2022 à 22:32, Richard Henderson a écrit :
Changes from v4:
* Rebase on master.
All patches are reviewed.
Series applied to my linux-user-for-7.0 branch.
Thanks,
Laurent
r~
Richard Henderson (24):
linux-user/alpha: Set TRAP_UNK for bugchk and unknown gentrap
repository at:
g...@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20220108
for you to fetch changes up to 48eaeb56debf91817dea00a2cd9c1f6c986eb531:
target/riscv: Implement the stval/mtval illegal instruction (2022-01-08
15:46:10 +1000
Le 06/01/2022 à 23:57, Richard Henderson a écrit :
The kernel does not special-case arg2 != NULL, so
neither should we.
Signed-off-by: Richard Henderson
---
linux-user/syscall.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
Le 08/01/2022 à 18:10, Laurent Vivier a écrit :
Le 06/01/2022 à 23:57, Richard Henderson a écrit :
The kernel does not special-case arg2 != NULL, so
neither should we.
Signed-off-by: Richard Henderson
---
linux-user/syscall.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
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