[PATCH] sgx: Move sgx object from /machine/unattached to /machine

When Libvirt start, it get the vcpu's unavailable-features from /machine/unattached/device[0] path by qom-get command, but in SGX guest, since the sgx-epc virtual device is initialized before VCPU creation(virtual sgx need set the virtual EPC info in the cpuid). This /machine/unattached/device[0]

[PATCH v5 12/13] target/riscv: Support virtual time context synchronization

Add virtual time context description to vmstate_kvmtimer. After cpu being loaded, virtual time context is updated to KVM. Signed-off-by: Yifei Jiang Signed-off-by: Mingwang Li Reviewed-by: Anup Patel Reviewed-by: Alistair Francis --- target/riscv/machine.c | 30 ++

[PATCH v5 03/13] target/riscv: Implement function kvm_arch_init_vcpu

Get isa info from kvm while kvm init. Signed-off-by: Yifei Jiang Signed-off-by: Mingwang Li Reviewed-by: Alistair Francis Reviewed-by: Anup Patel --- target/riscv/kvm.c | 34 +- 1 file changed, 33 insertions(+), 1 deletion(-) diff --git a/target/riscv/kvm.c

[PATCH v5 08/13] target/riscv: Handle KVM_EXIT_RISCV_SBI exit

Use char-fe to handle console sbi call, which implement early console io while apply 'earlycon=sbi' into kernel parameters. Signed-off-by: Yifei Jiang Signed-off-by: Mingwang Li Reviewed-by: Anup Patel Reviewed-by: Alistair Francis --- target/riscv/kvm.c | 42

[PATCH v5 13/13] target/riscv: enable riscv kvm accel

Add riscv kvm support in meson.build file. Signed-off-by: Yifei Jiang Signed-off-by: Mingwang Li --- meson.build | 2 ++ 1 file changed, 2 insertions(+) diff --git a/meson.build b/meson.build index c1b1db1e28..06a5476254 100644 --- a/meson.build +++ b/meson.build @@ -90,6 +90,8 @@ elif cpu in

Re: [PATCH v10 0/7] Add vmnet.framework based network backend

On Wed, Jan 12, 2022 at 10:50:04AM +0300, Roman Bolshakov wrote: > On Wed, Jan 12, 2022 at 12:14:15AM +0300, Vladislav Yaroshchuk wrote: > > macOS provides networking API for VMs called 'vmnet.framework': > > https://developer.apple.com/documentation/vmnet > > > > We can provide its support as

[PATCH v5 10/13] target/riscv: Add kvm_riscv_get/put_regs_timer

Add kvm_riscv_get/put_regs_timer to synchronize virtual time context from KVM. To set register of RISCV_TIMER_REG(state) will occur a error from KVM on kvm_timer_state == 0. It's better to adapt in KVM, but it doesn't matter that adaping in QEMU. Signed-off-by: Yifei Jiang Signed-off-by:

[PULL V2 06/13] net/filter: Optimize filter_send to coroutine

From: Rao Lei This patch is to improve the logic of QEMU main thread sleep code in qemu_chr_write_buffer() where it can be blocked and can't run other coroutines during COLO IO stress test. Our approach is to put filter_send() in a coroutine. In this way, filter_send() will call

[PULL V2 12/13] net/vmnet: update qemu-options.hx

From: Vladislav Yaroshchuk Signed-off-by: Vladislav Yaroshchuk Signed-off-by: Jason Wang --- qemu-options.hx | 25 + 1 file changed, 25 insertions(+) diff --git a/qemu-options.hx b/qemu-options.hx index ec90505..81dd34f 100644 --- a/qemu-options.hx +++

Re: [PATCH 1/2] block/rbd: fix handling of holes in .bdrv_co_block_status

On Mon, Jan 10, 2022 at 12:42 PM Peter Lieven wrote: > > the assumption that we can't hit a hole if we do not diff against a snapshot > was wrong. > > We can see a hole in an image if we diff against base if there exists an > older snapshot > of the image and we have discarded blocks in the

[PATCH v5 02/13] target/riscv: Add target/riscv/kvm.c to place the public kvm interface

Add target/riscv/kvm.c to place kvm_arch_* function needed by kvm/kvm-all.c. Signed-off-by: Yifei Jiang Signed-off-by: Mingwang Li Reviewed-by: Alistair Francis Reviewed-by: Anup Patel --- target/riscv/kvm.c | 133 +++ target/riscv/meson.build | 1

[PATCH v2 2/2] tests/qtest: Add test for Aspeed HACE accumulative mode

This add two addition test cases for accumulative mode under sg enabled. The input vector was manually craft with "abc" + bit 1 + padding zeros + L. The padding length depends on algorithm, i.e. SHA512 (1024 bit), SHA256 (512 bit). The result was calculated by command line sha512sum/sha256sum

[PATCH v5 09/13] target/riscv: Add host cpu type

'host' type cpu is set isa to RV32 or RV64 simply, more isa info will obtain from KVM in kvm_arch_init_vcpu() Signed-off-by: Yifei Jiang Signed-off-by: Mingwang Li Reviewed-by: Alistair Francis Reviewed-by: Anup Patel --- target/riscv/cpu.c | 15 +++ target/riscv/cpu.h | 1 + 2

[PATCH v5 05/13] target/riscv: Implement kvm_arch_put_registers

Put GPR CSR and FP registers to kvm by KVM_SET_ONE_REG ioctl Signed-off-by: Yifei Jiang Signed-off-by: Mingwang Li Reviewed-by: Alistair Francis Reviewed-by: Anup Patel --- target/riscv/kvm.c | 104 - 1 file changed, 103 insertions(+), 1

[PULL V2 01/13] hw/net/vmxnet3: Log guest-triggerable errors using LOG_GUEST_ERROR

From: Philippe Mathieu-Daudé The "Interrupt Cause" register (VMXNET3_REG_ICR) is read-only. Write accesses are ignored. Log them with as LOG_GUEST_ERROR instead of aborting: [R +0.239743] writeq 0xe0002031 0x46291a5a55460800 ERROR:hw/net/vmxnet3.c:1819:vmxnet3_io_bar1_write: code should not

[PULL V2 00/13] Net patches

The following changes since commit 64c01c7da449bcafc614b27ecf1325bb08031c84: Merge remote-tracking branch 'remotes/philmd/tags/sdmmc-20220108' into staging (2022-01-11 11:39:31 +) are available in the git repository at: https://github.com/jasowang/qemu.git tags/net-pull-request for

[PULL V2 11/13] net/vmnet: implement bridged mode (vmnet-bridged)

From: Vladislav Yaroshchuk Signed-off-by: Vladislav Yaroshchuk Signed-off-by: Jason Wang --- net/vmnet-bridged.m | 98 + 1 file changed, 92 insertions(+), 6 deletions(-) diff --git a/net/vmnet-bridged.m b/net/vmnet-bridged.m index

Re: [PATCH v2 3/5] target/s390x: Fix cc_calc_sla_64() missing overflows

On 12.01.22 05:39, Ilya Leoshkevich wrote: > An overflow occurs for SLAG when at least one shifted bit is not equal > to sign bit. Therefore, we need to check that `shift + 1` bits are > neither all 0s nor all 1s. The current code checks only `shift` bits, > missing some overflows. Right,

Re: [PATCH v3 01/10] stubs: Restrict fw_cfg to system emulation

On 11.01.22 19:43, Philippe Mathieu-Daudé wrote: > fw_cfg_arch_key_name() stub is only required for sysemu. > > Signed-off-by: Philippe Mathieu-Daudé > --- > stubs/meson.build | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/stubs/meson.build b/stubs/meson.build > index

RE: [PATCH v4 05/12] target/riscv: Implement kvm_arch_put_registers

> -Original Message- > From: Alistair Francis [mailto:alistai...@gmail.com] > Sent: Tuesday, January 11, 2022 7:07 AM > To: Jiangyifei > Cc: qemu-devel@nongnu.org Developers ; open > list:RISC-V ; kvm-ri...@lists.infradead.org; open > list:Overall ; libvir-l...@redhat.com; Anup Patel > ;

RE: [PATCH v4 02/12] target/riscv: Add target/riscv/kvm.c to place the public kvm interface

> -Original Message- > From: Alistair Francis [mailto:alistai...@gmail.com] > Sent: Tuesday, January 11, 2022 7:10 AM > To: Jiangyifei > Cc: qemu-devel@nongnu.org Developers ; open > list:RISC-V ; kvm-ri...@lists.infradead.org; open > list:Overall ; libvir-l...@redhat.com; Anup Patel > ;

[PULL V2 03/13] net: Fix uninitialized data usage

From: Peter Foley e.g. 1109 15:16:20.151506 Uninitialized bytes in ioctl_common_pre at offset 0 inside [0x7ffc516af9b8, 4) 1109 15:16:20.151659 ==588974==WARNING: MemorySanitizer: use-of-uninitialized-value 1109 15:16:20.312923 #0 0x5639b88acb21 in tap_probe_vnet_hdr_len

[PATCH v2 0/2] Supporting AST2600 HACE engine accumulative mode

This patch series implements ast2600 hace engine with accumulative mode and unit test against to it. Changes in v2: - Coding style - Add accumulative mode description in comment - Add unit test cases Troy Lee (2): hw/misc: Supporting AST2600 HACE accumulative mode tests/qtest: Add test for

[PATCH v5 04/13] target/riscv: Implement kvm_arch_get_registers

Get GPR CSR and FP registers from kvm by KVM_GET_ONE_REG ioctl. Signed-off-by: Yifei Jiang Signed-off-by: Mingwang Li Reviewed-by: Alistair Francis Reviewed-by: Anup Patel --- target/riscv/kvm.c | 112 - 1 file changed, 111 insertions(+), 1

Re: [PATCH v2 1/2] hw/misc: Supporting AST2600 HACE accumulative mode

[ Adding Klaus ] Sorry I forgot to add Klaus to the CC list. On Wed, Jan 12, 2022 at 4:10 PM Troy Lee wrote: > > Accumulative mode will supply a initial state and append padding bit at > the end of hash stream. However, the crypto library will padding those > bit automatically, so ripped it

[PATCH v5 06/13] target/riscv: Support start kernel directly by KVM

Get kernel and fdt start address in virt.c, and pass them to KVM when cpu reset. Add kvm_riscv.h to place riscv specific interface. In addition, PLIC is created without M-mode PLIC contexts when KVM is enabled. Signed-off-by: Yifei Jiang Signed-off-by: Mingwang Li Reviewed-by: Alistair Francis

[PATCH v5 11/13] target/riscv: Implement virtual time adjusting with vm state changing

We hope that virtual time adjusts with vm state changing. When a vm is stopped, guest virtual time should stop counting and kvm_timer should be stopped. When the vm is resumed, guest virtual time should continue to count and kvm_timer should be restored. Signed-off-by: Yifei Jiang Signed-off-by:

[PULL V2 05/13] net/colo-compare.c: Update the default value comments

From: Zhang Chen Make the comments consistent with the REGULAR_PACKET_CHECK_MS. Signed-off-by: Zhang Chen Signed-off-by: Jason Wang --- net/colo-compare.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/net/colo-compare.c b/net/colo-compare.c index 216de5a..62554b5 100644

[PULL V2 07/13] net/vmnet: add vmnet dependency and customizable option

From: Vladislav Yaroshchuk vmnet.framework dependency is added with 'vmnet' option to enable or disable it. Default value is 'auto'. vmnet features to be used are available since macOS 11.0, corresponding probe is created into meson.build. Signed-off-by: Vladislav Yaroshchuk Signed-off-by:

Re: [PATCH v2 1/5] target/s390x: Fix SLDA sign bit index

On 12.01.22 05:39, Ilya Leoshkevich wrote: > David Hildenbrand noticed that sign bit index for SLDA is wrong: since > SLDA operates on 64-bit values, it should be 63, not 31. Maybe just replace the "David ... noticed" by a Reported-by (below). > > Fixes: a79ba3398a0a ("target-s390: Convert

[PULL V2 04/13] net/colo-compare.c: Optimize compare order for performance

From: Zhang Chen COLO-compare use the glib function g_queue_find_custom to dump another VM's networking packet to compare. But this function always start find from the queue->head(here is the newest packet), It will reduce the success rate of comparison. So this patch reversed the order of the

[PULL V2 02/13] net/tap: Set return code on failure

From: Peter Foley Match the other error handling in this function. Fixes: e7b347d0bf6 ("net: detect errors from probing vnet hdr flag for TAP devices") Reviewed-by: Patrick Venture Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Peter Foley Signed-off-by: Jason Wang --- net/tap.c | 1

Re: [PATCH v2 2/5] target/s390x: Fix SRDA CC calculation

On 12.01.22 05:39, Ilya Leoshkevich wrote: > SRDA uses r1_D32 for binding the first operand and s64 for setting CC. > cout_s64() relies on o->out being the shift result, however, > wout_r1_D32() clobbers it. > > Fix by using a temporary. > > Fixes: a79ba3398a0a ("target-s390: Convert SHIFT

[PULL V2 10/13] net/vmnet: implement host mode (vmnet-host)

From: Vladislav Yaroshchuk Signed-off-by: Vladislav Yaroshchuk Signed-off-by: Jason Wang --- net/vmnet-host.c | 93 1 file changed, 87 insertions(+), 6 deletions(-) diff --git a/net/vmnet-host.c b/net/vmnet-host.c index

Re: [PATCH v2 4/5] target/s390x: Fix shifting 32-bit values for more than 31 bits

> > +static uint32_t cc_calc_sla_32(uint32_t src, int shift) > +{ > +return cc_calc_sla_64(((uint64_t)src) << 32, shift); > +} > + Nice trick. What about doing the shift in op_sla if s->insn->data == 31 and unifying to a single CC_OP_SLA ? > static uint32_t cc_calc_flogr(uint64_t dst) >

Re: [PATCH v3 09/10] hw/dma: Move ScatterGatherEntry / QEMUSGList declarations around

On 11.01.22 19:43, Philippe Mathieu-Daudé wrote: > In the next commit we will use the dma_addr_t type in the QEMUSGList > structure. Since currently dma_addr_t is defined after QEMUSGList, > move the declarations to have dma_addr_t defined first. This is a > pure code-movement patch. Oh, that was

Re: [PULL 0/4] Python patches

On Mon, 10 Jan 2022 at 23:25, John Snow wrote: > > The following changes since commit de3f5223fa4cf8bfc5e3fe1fd495ddf468edcdf7: > > Merge remote-tracking branch > 'remotes/vivier/tags/m68k-for-7.0-pull-request' into staging (2022-01-10 > 14:43:03 +) > > are available in the Git repository

[PATCH v5 01/13] update-linux-headers: Add asm-riscv/kvm.h

Add asm-riscv/kvm.h for RISC-V KVM. Signed-off-by: Yifei Jiang Signed-off-by: Mingwang Li Acked-by: Alistair Francis Reviewed-by: Anup Patel --- linux-headers/asm-riscv/kvm.h | 128 ++ 1 file changed, 128 insertions(+) create mode 100644

[PATCH v2 1/2] hw/misc: Supporting AST2600 HACE accumulative mode

Accumulative mode will supply a initial state and append padding bit at the end of hash stream. However, the crypto library will padding those bit automatically, so ripped it off from iov array. The aspeed ast2600 acculumative mode is described in datasheet ast2600v10.pdf section 25.6.4: 1.

RE: [PATCH v4 06/12] target/riscv: Support start kernel directly by KVM

> -Original Message- > From: Alistair Francis [mailto:alistai...@gmail.com] > Sent: Tuesday, January 11, 2022 8:28 AM > To: Jiangyifei > Cc: qemu-devel@nongnu.org Developers ; open > list:RISC-V ; kvm-ri...@lists.infradead.org; open > list:Overall ; libvir-l...@redhat.com; Anup Patel > ;

Re: [PATCH v2 2/2] tests/qtest: Add test for Aspeed HACE accumulative mode

[ Adding Klaus ] On Wed, Jan 12, 2022 at 4:09 PM Troy Lee wrote: > > This add two addition test cases for accumulative mode under sg enabled. > > The input vector was manually craft with "abc" + bit 1 + padding zeros + L. > The padding length depends on algorithm, i.e. SHA512 (1024 bit), >

Re: [PATCH 1/1] ppc/pnv: use stack->pci_regs[] in pnv_pec_stk_pci_xscom_write()

On 11/01/2022 21:01, Daniel Henrique Barboza wrote: pnv_pec_stk_pci_xscom_write() is pnv_pec_stk_pci_xscom_ops write callback. It writes values into regs in the stack->nest_regs[] array. The pnv_pec_stk_pci_xscom_read read callback, on the other hand, returns values of the stack->pci_regs[].

[PULL V2 08/13] net/vmnet: add vmnet backends to qapi/net

From: Vladislav Yaroshchuk Create separate netdevs for each vmnet operating mode: - vmnet-host - vmnet-shared - vmnet-bridged Signed-off-by: Vladislav Yaroshchuk Signed-off-by: Jason Wang --- net/clients.h | 11 + net/meson.build | 7 +++ net/net.c | 10

[PULL V2 13/13] net/vmnet: update MAINTAINERS list

From: Vladislav Yaroshchuk Signed-off-by: Vladislav Yaroshchuk Signed-off-by: Jason Wang --- MAINTAINERS | 5 + 1 file changed, 5 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index c98a61c..638d129 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2641,6 +2641,11 @@ W:

[PULL V2 09/13] net/vmnet: implement shared mode (vmnet-shared)

From: Vladislav Yaroshchuk Interaction with vmnet.framework in different modes differs only on configuration stage, so we can create common `send`, `receive`, etc. procedures and reuse them. vmnet.framework supports iov, but writing more than one iov into vmnet interface fails with

[PATCH] hw/usb/dev-wacom: add missing HID descriptor

Linux need to fill up the HID descriptor in order to let the driver be emulated. The descriptor was downloaded from [1]. The patch was tested with evtest tool on top of qemu 5.2.0 with linux kernel 4.19.208. [1] https://github.com/linuxwacom/wacom-hid-descriptors/tree/master/Wacom%20PenPartner

Re: [PATCH v2 5/5] tests/tcg/s390x: Test shift instructions

On 12.01.22 05:39, Ilya Leoshkevich wrote: > Add a test for each shift instruction in order to to prevent > regressions. > > Signed-off-by: Ilya Leoshkevich > --- > tests/tcg/s390x/Makefile.target | 1 + > tests/tcg/s390x/shift.c | 258 > 2 files

[PATCH v5 07/13] target/riscv: Support setting external interrupt by KVM

When KVM is enabled, set the S-mode external interrupt through kvm_riscv_set_irq function. Signed-off-by: Yifei Jiang Signed-off-by: Mingwang Li Reviewed-by: Alistair Francis Reviewed-by: Anup Patel --- target/riscv/cpu.c | 6 +- target/riscv/kvm-stub.c | 5 +

[PATCH v5 00/13] Add riscv kvm accel support

This series adds both riscv32 and riscv64 kvm support, and implements migration based on riscv. Because of RISC-V KVM has been merged into the Linux master, so this series are changed from RFC to patch. Several steps to use this: 1. Build emulation $ ./configure --target-list=riscv64-softmmu $

Re: [PATCH v3 02/10] hw/nvram: Restrict fw_cfg QOM interface to sysemu and tools

On 11.01.22 19:43, Philippe Mathieu-Daudé wrote: > From: Philippe Mathieu-Daudé > > fw_cfg QOM interface is required by system emulation and > qemu-storage-daemon. User-mode emulation doesn't need it. > > Signed-off-by: Philippe Mathieu-Daudé > Signed-off-by: Philippe Mathieu-Daudé > --- >

Re: [PATCH v14 02/26] target/loongarch: Add core definition

Hi, On 2022/1/9 下午5:25, WANG Xuerui wrote: +    data = FIELD_DP32(data, CPUCFG16, L1_DPRE, 1); +    data = FIELD_DP32(data, CPUCFG16, L2_IUPRE, 1); +    data = FIELD_DP32(data, CPUCFG16, L2_IUUNIFY, 1); +    data = FIELD_DP32(data, CPUCFG16, L2_IUPRIV, 1); +    data = FIELD_DP32(data, CPUCFG16,

[PULL 05/31] ci: explicitly skip I/O tests on alpine

From: Daniel P. Berrangé The block I/O tests don't work on Alpine because their alternative libc impl emits different strings for errnos, which breaks the expected output matching. e.g. === IO: pattern 102 wrote 512/512 bytes at offset 512 512 bytes, X ops; XX:XX:XX.X (XXX YYY/sec and XXX

[PULL 03/31] meson: require liburing >= 0.3

From: Daniel P. Berrangé openSUSE Leap 15.2 ships with liburing == 0.2 against which QEMU fails to build. ../util/fdmon-io_uring.c: In function ‘fdmon_io_uring_need_wait’: ../util/fdmon-io_uring.c:305:9: error: implicit declaration of function ‘io_uring_sq_ready’; did you mean

[PULL 15/31] tests/docker: updates to alpine package list

From: Daniel P. Berrangé Cleanup the package lists by removing some entries that we don't need to directly reference binutils: implied by the compiler toolchain coreutils: not required by QEMU build mesa-egl mesa-gbm: implied by mesa-dev ninja: alias for samurai package shadow: not

[PULL 26/31] linux-user: don't adjust base of found hole

The pgb_find_hole function goes to the trouble of taking account of both mmap_min_addr and any offset we've applied to decide the starting address of a potential hole. This is especially important for emulating 32bit ARM in a 32bit build as we have applied the offset to ensure there will be space

[PULL 23/31] docs/devel: update C standard to C11

Since 8a9d3d5640 (configure: Use -std=gnu11) we have allowed C11 code so lets reflect that in the style guide. Signed-off-by: Alex Bennée Reviewed-by: Daniel P. Berrangé Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-Id:

Re: [PATCH] MAINTAINERS: Improve the PowerPC machines section

On 1/5/22 11:48, Thomas Huth wrote: Add some documentation files to the corresponding machine sections and mention the machine names in the section titles where it is not so obvious (e.g. that "taihu" is a 405 machine). Signed-off-by: Thomas Huth --- MAINTAINERS | 12 1 file

[PULL 00/34] ppc queue

-20220112 for you to fetch changes up to f83460bb203a49dd1693bf8b664d2a935a5be621: ppc/pnv: use stack->pci_regs[] in pnv_pec_stk_pci_xscom_write() (2022-01-12 11:28:27 +0100) ppc 7.0 queue: * New SLOF for PPC970 and POWER5+ (Ale

[PULL 03/34] spapr: Fix support of POWER5+ processors

POWER5+ (ISA v2.03) processors are supported by the pseries machine but they do not have Altivec instructions. Do not advertise support for it in the DT. To be noted that this test is in contradiction with the assert in cap_vsx_apply(). Signed-off-by: Cédric Le Goater Tested-by: Fabiano Rosas

[PULL 26/34] pnv_phb4.c: change TYPE_PNV_PHB4_ROOT_BUS name

From: Daniel Henrique Barboza Similar to what was happening with pnv-phb3 buses, TYPE_PNV_PHB4_ROOT_BUS set to "pnv-phb4-root-bus" is a bit too long for a default root bus name. The usual default name for theses buses in QEMU are 'pcie', but we want to make a distinction between pnv-phb4 buses

[PULL 11/34] target/ppc: Add HV support to ppc_interrupts_little_endian

From: Fabiano Rosas The ppc_interrupts_little_endian function could be used for interrupts delivered in Hypervisor mode, so add support for powernv8 and powernv9 to it. Also drop the comment because it is inaccurate, all CPUs that can run little endian can have interrupts in little endian. The

[PATCH v11 4/7] net/vmnet: implement host mode (vmnet-host)

Signed-off-by: Vladislav Yaroshchuk --- net/vmnet-host.c | 96 +--- 1 file changed, 90 insertions(+), 6 deletions(-) diff --git a/net/vmnet-host.c b/net/vmnet-host.c index 4a5ef99dc7..eee4daf74b 100644 --- a/net/vmnet-host.c +++ b/net/vmnet-host.c @@

Re: [PATCH v6 07/23] target/riscv: Add defines for AIA CSRs

Anup Patel 於 2021年12月30日 週四 下午8:52寫道： > From: Anup Patel > > The RISC-V AIA specification extends RISC-V local interrupts and > introduces new CSRs. This patch adds defines for the new AIA CSRs. > > Signed-off-by: Anup Patel > Signed-off-by: Anup Patel > Reviewed-by: Alistair Francis > --- >

Re: [PATCH v6 08/23] target/riscv: Allow AIA device emulation to set ireg rmw callback

Anup Patel 於 2021年12月30日 週四 下午8:36寫道： > From: Anup Patel > > The AIA device emulation (such as AIA IMSIC) should be able to set > (or provide) AIA ireg read-modify-write callback for each privilege > level of a RISC-V HART. > > Signed-off-by: Anup Patel > Signed-off-by: Anup Patel >

Re: [RFC PATCH v3 22/27] hw/loongarch: Add some devices support for 3A5000.

On 12/23/2021 06:52 PM, Mark Cave-Ayland wrote: > On 22/12/2021 08:26, yangxiaojuan wrote: > >> Hi, Mark >> >> On 12/18/2021 06:02 PM, Mark Cave-Ayland wrote: >>> On 04/12/2021 12:07, Xiaojuan Yang wrote: >>> 1.Add uart,virtio-net,vga and usb for 3A5000. 2.Add irq set and map for the

Re: [PATCH 2/2] block/rbd: workaround for ceph issue #53784

On Mon, Jan 10, 2022 at 12:43 PM Peter Lieven wrote: > > librbd had a bug until early 2022 that affected all versions of ceph that > supported fast-diff. This bug results in reporting of incorrect offsets > if the offset parameter to rbd_diff_iterate2 is not object aligned. > Work around this bug

[PULL 11/31] tests/docker: auto-generate ubuntu2004.docker with lcitool

From: Daniel P. Berrangé This commit is best examined using the "-b" option to diff. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Daniel P. Berrangé Signed-off-by: Alex Bennée Message-Id: <20211215141949.3512719-12-berra...@redhat.com> Message-Id:

[PATCH 1/2] hw/virtio: add boilerplate for vhost-user-gpio device

This creates the QEMU side of the vhost-user-gpio device which connects to the remote daemon. It is based of vhost-user-i2c code. Signed-off-by: Viresh Kumar --- hw/virtio/Kconfig | 5 + hw/virtio/meson.build | 1 + hw/virtio/vhost-user-gpio.c | 343

[PULL 31/31] linux-user: Remove the deprecated ppc64abi32 target

From: Thomas Huth It's likely broken, and nobody cared for picking it up again during the deprecation phase, so let's remove this now. Since this is the last entry in deprecated_targets_list, remove the related code in the configure script, too. Signed-off-by: Thomas Huth Reviewed-by: Richard

[PULL 29/34] ppc/pnv: set phb4 properties in stk_realize()

From: Daniel Henrique Barboza Moving all phb4 properties setup to stk_realize() keeps this logic in a single place instead of having it scattered between stk_realize() and pec_realize(). 'phb->index' can be retrieved using stack->stack_no and pnv_phb4_pec_get_phb_id(), deprecating the use of

[PULL 02/34] target/ppc: Add popcntb instruction to POWER5+ processors

popcntb instruction was added in ISA v2.02. Add support for POWER5+ processors since they implement ISA v2.03. PPC970 CPUs implement v2.01 and do not support popcntb. Signed-off-by: Cédric Le Goater Reviewed-by: Fabiano Rosas Message-Id: <20220105095142.3990430-2-...@kaod.org> Signed-off-by:

[PULL 23/34] ppc/pnv: Complete user created PHB3 devices

PHB3s ared SysBus devices and should be allowed to be dynamically created. Reviewed-by: Daniel Henrique Barboza Signed-off-by: Cédric Le Goater Message-Id: <20220105212338.49899-9-danielhb...@gmail.com> Signed-off-by: Cédric Le Goater --- hw/pci-host/pnv_phb3.c | 9 + hw/ppc/pnv.c

[PULL 22/34] ppc/pnv: Reparent user created PHB3 devices to the PnvChip

The powernv machine uses the object hierarchy to populate the device tree and each device should be parented to the chip it belongs to. This is not the case for user created devices which are parented to the container "/unattached". Make sure a PHB3 device is parented to its chip by reparenting

[PULL 32/34] ppc/pnv: Introduce user creatable pnv-phb4 devices

From: Daniel Henrique Barboza This patch introduces pnv-phb4 user creatable devices that are created in a similar manner as pnv-phb3 devices, allowing the user to interact with the PHBs directly instead of creating PCI Express Controllers that will create a certain amount of PHBs per controller

[PATCH v3 2/5] target/s390x: Fix SRDA CC calculation

SRDA uses r1_D32 for binding the first operand and s64 for setting CC. cout_s64() relies on o->out being the shift result, however, wout_r1_D32() clobbers it. Fix by using a temporary. Fixes: a79ba3398a0a ("target-s390: Convert SHIFT DOUBLE") Signed-off-by: Ilya Leoshkevich Reviewed-by: David

Re: [RFC] virtio_pmem: enable live migration support

On 31.12.21 13:01, Pankaj Gupta wrote: > From: Pankaj Gupta > > > Enable live migration support for virtio-pmem device. > Tested this: with live migration on same host. > > Need suggestion on below points to support virtio-pmem live migration > between two separate host systems: I assume

Re: [PATCH v2 1/4] jobs: drop qmp_ trace points

On Tue, Jan 11, 2022 at 06:44:58PM -0500, John Snow wrote: > On Mon, Jan 10, 2022 at 11:06 AM Stefan Hajnoczi wrote: > > > > On Thu, Dec 23, 2021 at 12:07:53PM +0100, Vladimir Sementsov-Ogievskiy > > wrote: > > > diff --git a/block/trace-events b/block/trace-events > > > index

[PULL 20/31] tests/docker: add libfuse3 development headers

From: Stefan Hajnoczi The FUSE exports feature is not built because most container images do not have libfuse3 development headers installed. Add the necessary packages to the Dockerfiles. Cc: Hanna Reitz Cc: Richard W.M. Jones Signed-off-by: Stefan Hajnoczi Acked-by: Richard W.M. Jones

[PULL 28/31] test/tcg/ppc64le: Add float reference files

From: Richard Henderson Generated on Power9, PowerNV 9006-22P. Signed-off-by: Richard Henderson Signed-off-by: Alex Bennée Message-Id: <20211224035541.2159966-3-richard.hender...@linaro.org> Message-Id: <20220105135009.1584676-30-alex.ben...@linaro.org> diff --git

[PULL 18/34] ppc/pnv: Attach PHB3 root port device when defaults are enabled

This cleanups the PHB3 model a bit more since the root port is an independent device and it will ease our task when adding user created PHB3s. pnv_phb_attach_root_port() is made public in pnv.c so it can be reused with the pnv_phb4 root port later. Signed-off-by: Cédric Le Goater Signed-off-by:

[PULL 14/34] target/ppc: Introduce a wrapper for powerpc_excp

From: Fabiano Rosas Next patches will split powerpc_excp in multiple family specific handlers. This patch adds a wrapper to make the transition clearer. Signed-off-by: Fabiano Rosas Reviewed-by: David Gibson Message-Id: <20220107222601.4101511-8-faro...@linux.ibm.com> Signed-off-by: Cédric Le

[PULL 08/34] target/ppc: powerpc_excp: Extract software TLB logging into a function

From: Fabiano Rosas Signed-off-by: Fabiano Rosas Reviewed-by: David Gibson Reviewed-by: Richard Henderson Message-Id: <20220107222601.4101511-2-faro...@linux.ibm.com> Signed-off-by: Cédric Le Goater --- target/ppc/excp_helper.c | 65 +++- 1 file changed,

[PATCH v11 5/7] net/vmnet: implement bridged mode (vmnet-bridged)

Signed-off-by: Vladislav Yaroshchuk --- net/vmnet-bridged.m | 100 +--- 1 file changed, 94 insertions(+), 6 deletions(-) diff --git a/net/vmnet-bridged.m b/net/vmnet-bridged.m index 4e42a90391..19a68a6a1c 100644 --- a/net/vmnet-bridged.m +++

[PATCH v11 7/7] net/vmnet: update MAINTAINERS list

Signed-off-by: Vladislav Yaroshchuk --- MAINTAINERS | 5 + 1 file changed, 5 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index c98a61caee..638d129305 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2641,6 +2641,11 @@ W: http://info.iet.unipi.it/~luigi/netmap/ S: Maintained F:

[PATCH v11 0/7] Add vmnet.framework based network backend

macOS provides networking API for VMs called 'vmnet.framework': https://developer.apple.com/documentation/vmnet We can provide its support as the new QEMU network backends which represent three different vmnet.framework interface usage modes: * `vmnet-shared`: allows the guest to

Re: [PATCH v3 0/2] Aspeed I3C device model

Hello Gregory, On 1/12/22 11:57, Graeme Gregory wrote: On Tue, Jan 11, 2022 at 04:45:44PM +0800, Troy Lee wrote: This series of patch introduce a dummy implemenation of aspeed i3c model, and it provide just enough information for guest machine. However, the driver probing is still failed, but

Re: [PATCH v6 23/23] hw/riscv: virt: Increase maximum number of allowed CPUs

Anup Patel 於 2021年12月30日 週四 下午9:06寫道： > From: Anup Patel > > To facilitate software development of RISC-V systems with large number > of HARTs, we increase the maximum number of allowed CPUs to 512 (2^9). > > We also add a detailed source level comments about limit defines which > impact the

Re: RFC: QMP configuration - allocating/setting qdev array properties?

Hi Mirela, On 1/11/22 17:54, Mirela Grujic wrote: Hi, While working on a prototype and configuring a whole machine using QMP we run into the following scenario. Some device models use array properties. The array is allocated when len- property is set, then, individual elements of the

Re: [PATCH] migration: Add canary to VMSTATE_END_OF_LIST

On Wed, 12 Jan 2022 at 10:24, Dr. David Alan Gilbert (git) wrote: > > From: "Dr. David Alan Gilbert" > > We fairly regularly forget VMSTATE_END_OF_LIST markers off descriptions; > given that the current check is only for ->name being NULL, sometimes > we get unlucky and the code apparently works

Re: [PATCH v14 02/26] target/loongarch: Add core definition

Hi, On 2022/1/12 18:17, gaosong wrote: > > Hi, > > On 2022/1/12 下午5:28, gaosong wrote: +    data = FIELD_DP32(data, CPUCFG16, L3_IUUNIFY, 1); +    data = FIELD_DP32(data, CPUCFG16, L3_IUINCL, 1); +    env->cpucfg[16] = data; + +    data = 0; +    data =

Re: [PATCH] iotests/308: Fix for CAP_DAC_OVERRIDE

Am 03.01.2022 um 13:00 hat Hanna Reitz geschrieben: > With CAP_DAC_OVERRIDE (which e.g. root generally has), permission checks > will be bypassed when opening files. > > 308 in one instance tries to open a read-only file (FUSE export) with > qemu-io as read/write, and expects this to fail.

Re: PyPI account

[Context: John created a PyPI QEMU user in order to publish the qemu.qmp package. If anyone wants to publish additional Python packages from qemu.git, please contact him for PyPI access.] On Tue, Jan 11, 2022 at 03:42:23PM -0500, John Snow wrote: > Account made: https://pypi.org/user/QEMU/ > > I

Re: [PATCH] migration: Add canary to VMSTATE_END_OF_LIST

On Wed, 12 Jan 2022 at 10:42, Dr. David Alan Gilbert wrote: > > * Peter Maydell (peter.mayd...@linaro.org) wrote: > > Does 'make check' definitely do the traversal for all vmstate > > structs, or do we need to add a "sanity check them all on startup" > > bit of test code ? > > Oh I doubt it does;

[PULL 07/31] tests: integrate lcitool for generating build env manifests

From: Daniel P. Berrangé This introduces https://gitlab.com/libvirt/libvirt-ci as a git submodule at tests/lcitool/libvirt-ci The 'lcitool' program within this submodule will be used to automatically generate build environment manifests from a definition of requirements in

Re: [PATCH] target/ppc: Add extra float instructions to POWER5P processors

On 1/10/22 17:19, Cédric Le Goater wrote: ISA v2.03 introduced Floating Round to Integer instructions : frin, friz, frip, and frim. Add them to POWER5+. The PPC_FLOAT_EXT flag also includes the fre (Floating Reciprocal Estimate) instruction which was introduced in ISA v2.0x. The architecture

[PULL 18/31] tests/docker: auto-generate alpine.docker with lcitool

From: Daniel P. Berrangé This commit is best examined using the "-b" option to diff. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Daniel P. Berrangé Signed-off-by: Alex Bennée Message-Id: <20211215141949.3512719-19-berra...@redhat.com> Message-Id:

Re: [PATCH 0/1] ppc/pnv: use stack->pci_regs[] in pnv_pec_stk_pci_xscom_write()

On 1/11/22 21:01, Daniel Henrique Barboza wrote: Hi, This is something that caught my eye when I was looking into the instances where we need stack properties versus phb4 properties. I tested this fix and it doesn't seem to impact the boot process whatsoever. Tracing

[PULL 29/31] FreeBSD: Upgrade to 12.3 release

From: Brad Smith Note, since libtasn1 was fixed in 12.3 [*], this commit re-enables GnuTLS. [*] https://gitlab.com/gnutls/libtasn1/-/merge_requests/71 Signed-off-by: Brad Smith Tested-by: Thomas Huth Reviewed-by: Warner Losh Signed-off-by: Alex Bennée Reviewed-by: Daniel P. Berrangé

[PATCH 0/2] virtio: Add vhost-user-gpio device's support

Hello, This patchset adds vhost-user-gpio device's support in Qemu. The support for the same has already been added to virtio specification and Linux Kernel. A Rust based backend is also in progress and is tested against this patchset: https://github.com/rust-vmm/vhost-device/pull/76 -- Viresh

Re: [PATCH 2/2] block/rbd: workaround for ceph issue #53784

Am 12.01.22 um 10:59 schrieb Ilya Dryomov: > On Mon, Jan 10, 2022 at 12:43 PM Peter Lieven wrote: >> librbd had a bug until early 2022 that affected all versions of ceph that >> supported fast-diff. This bug results in reporting of incorrect offsets >> if the offset parameter to rbd_diff_iterate2

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