From: Gavin Shan
The default block size is same as to the THP size, which is either
retrieved from "/sys/kernel/mm/transparent_hugepage/hpage_pmd_size"
or hardcoded to 2MB. There are flaws in both mechanisms and this
intends to fix them up.
* When
Am 20.01.2022 um 14:22 hat Paolo Bonzini geschrieben:
> On 1/19/22 19:34, Kevin Wolf wrote:
> > So if we go back to a bdrv_invalidate_cache() that does all the graph
> > manipulations (and asserts that we're in the main loop) and then have a
> > much smaller bdrv_co_invalidate_cache() that
On 1/19/22 22:41, Jagannathan Raman wrote:
The compiler path that cmake gets from meson is corrupted. It results in
the following error:
| -- The C compiler identification is unknown
| CMake Error at CMakeLists.txt:35 (project):
| The CMAKE_C_COMPILER:
|
Kevin Wolf writes:
> Am 19.01.2022 um 14:44 hat Hanna Reitz geschrieben:
>> On 19.01.22 13:58, Markus Armbruster wrote:
>> > Hanna Reitz writes:
>> >
>> > > We want to add a --daemonize argument to QSD's command line.
>> >
>> > Why?
>>
>> OK, s/we/I/. I find it useful, because without such
Cc'ing Beraldo
On 20/1/22 16:13, Peter Maydell wrote:
On Fri, 30 Jul 2021 at 16:12, Peter Maydell wrote:
"make check-acceptance" takes way way too long. I just did a run
on an arm-and-aarch64-targets-only debug build and it took over
half an hour, and this despite it skipping or cancelling
Eric Auger writes:
> At the moment the IO space limit is hardcoded to
> QPCI_PIO_LIMIT = 0x1. When accesses are performed to a bar,
> the base address of this latter is compared against the limit
> to decide whether we perform an IO or a memory access.
>
> On ARM, we cannot keep this PIO
"Michael S. Tsirkin" writes:
> On Thu, Jan 20, 2022 at 09:32:34AM +0530, Viresh Kumar wrote:
>> On 17-01-22, 10:11, Alex Bennée wrote:
>> >
>> > "Michael S. Tsirkin" writes:
>> >
>> > > On Wed, Jan 12, 2022 at 05:04:57PM +0530, Viresh Kumar wrote:
>> > >> Hello,
>> > >>
>> > >> This
Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20220120-1
for you to fetch changes up to b9d383ab797f54ae5fa8746117770709921dc529:
hw/intc/arm_gicv3: Check for !MEMTX_OK instead of MEMTX_ERROR (2022-01-20
16:04:58 +0
> On Jan 19, 2022, at 7:12 PM, Michael S. Tsirkin wrote:
>
> On Wed, Jan 19, 2022 at 04:41:52PM -0500, Jagannathan Raman wrote:
>> Allow PCI buses to be part of isolated CPU address spaces. This has a
>> niche usage.
>>
>> TYPE_REMOTE_MACHINE allows multiple VMs to house their PCI devices in
Fabian Ebner writes:
> Am 21.10.21 um 12:01 schrieb Stefan Reiter:
>> 'protocol' and 'connected' are better suited as enums than as strings,
>> make use of that. No functional change intended.
>> Suggested-by: Markus Armbruster
>> Reviewed-by: Markus Armbruster
>> Signed-off-by: Stefan Reiter
Test new qcow2 open option: keep-dirty.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
tests/qemu-iotests/tests/qcow2-keep-dirty | 104 ++
tests/qemu-iotests/tests/qcow2-keep-dirty.out | 34 ++
2 files changed, 138 insertions(+)
create mode 100755
On Tue, 11 Jan 2022 at 08:46, Troy Lee wrote:
>
> v3:
> - Remove unrelated changes to SPI2 address
> - Remove controller irq line
>
> v2: Rebase to mainline QEMU
>
> Signed-off-by: Troy Lee
This turns out not to build on macOS or on 32-bit hosts
because of format string issues -- you can't
From: Yanan Wang
Support one cluster level between core and physical package in the
cpu-map of Arm/virt devicetree. This is also consistent with Linux
Doc "Documentation/devicetree/bindings/cpu/cpu-topology.txt".
Signed-off-by: Yanan Wang
Reviewed-by: Andrew Jones
Message-id:
The bounds check on the number of interrupt IDs is correct, but
doesn't match our convention; change the variable name, initialize it
to the 2^n value rather than (2^n)-1, and use >= instead of > in the
comparison.
Signed-off-by: Peter Maydell
Reviewed-by: Alex Bennée
Message-id:
-arm.git
tags/pull-target-arm-20220120
for you to fetch changes up to 9705e3c1dcff96b0b3c7e594b6cd68d27d6c4ced:
hw/intc/arm_gicv3: Check for !MEMTX_OK instead of MEMTX_ERROR (2022-01-20
11:47:54 +)
target-arm:
* hw/intc
Fix process_mapc() to consistently return CMD_STALL for memory
errors and CMD_CONTINUE for parameter errors, as we claim in the
comments that we do.
Signed-off-by: Peter Maydell
Reviewed-by: Alex Bennée
Reviewed-by: Richard Henderson
Message-id:
On Thu, 20 Jan 2022 at 14:32, Peter Maydell wrote:
>
>
> But the code you are effectively removing is never executed
> for the instructions where you're changing the access function.
> If you're proposing this as a performance improvement, can
> you provide before-and-after benchmarks
The ITS has several tables which all share a similar format,
described by the TableDesc struct: the guest may configure them
to be a single-level table or a two-level table. Currently we
open-code the process of finding the table entry in all the
functions which read or write the device table or
On Tue, Jan 18, 2022 at 06:13:48AM +0100, Philippe Mathieu-Daudé wrote:
> On 18/1/22 00:27, John Snow wrote:
> > On Mon, Jan 17, 2022 at 9:11 AM Daniel P. Berrangé
> > wrote:
> > >
> > > With the current 'qmp-shell' tool developers must first spawn QEMU with
> > > a suitable -qmp arg and then
On 1/20/22 01:08, Philippe Mathieu-Daudé via wrote:
"host" pages are related to the *host* not the *target*,
thus the qemu_host_page_size / qemu_host_page_mask variables
and the HOST_PAGE_ALIGN() / REAL_HOST_PAGE_ALIGN() macros
can be moved to "exec/cpu-common.h" which is target agnostic.
On Fri, 30 Jul 2021 at 16:12, Peter Maydell wrote:
>
> "make check-acceptance" takes way way too long. I just did a run
> on an arm-and-aarch64-targets-only debug build and it took over
> half an hour, and this despite it skipping or cancelling 26 out
> of 58 tests!
>
> I think that ~10 minutes
The SGX NUMA patches were merged into Qemu 7.0 release, we need
clarify detailed version history information and also change
some related comments, which make SGX related comments clearer.
The QMP command schema promises backwards compatibility as standard.
We temporarily restore "@section-size",
On Thu, Jan 20, 2022 at 04:31:14PM +0100, Philippe Mathieu-Daudé wrote:
> On 20/1/22 10:10, Daniel P. Berrangé wrote:
> > On Wed, Jan 19, 2022 at 06:57:20PM -0500, Yang Zhong wrote:
> > > The SGX NUMA patches were merged into Qemu 7.0 release, we need
> > > clarify detailed version history
On 1/19/22 13:54, Fabiano Rosas wrote:
David Gibson writes:
On Tue, Jan 18, 2022 at 03:44:47PM -0300, Fabiano Rosas wrote:
The 405 Program Interrupt does not set SRR1 with any diagnostic bits,
just a clean copy of the MSR.
We're using the BookE Exception Syndrome Register which is different
On 20/1/22 14:37, Thomas Huth wrote:
On 20/01/2022 12.05, Philippe Mathieu-Daudé wrote:
From: Michael Tokarev
For a long time, we assumed that libxml2 is neecessary for parallels
Also "necessary",
block format support (block/parallels*). However, this format actually
does not use libxml
To allow/disallow the CSR access based on the privilege spec, a new field
in the csr_ops is introduced. It also adds the privileged specification
version (v1.12) for the CSRs introduced in the v1.12. This includes the
new ratified extensions such as Vector, Hypervisor and secconfig CSR.
Eric Auger writes:
> ARM does not not support hotplug on pcie.0. Add a flag on the bus
> which tells if devices can be hotplugged and skip hotplug tests
> if the bus cannot be hotplugged. This is a temporary solution to
> enable the other pci tests on aarch64.
>
> Signed-off-by: Eric Auger
>
On Wed, Jan 19, 2022 at 02:39:13PM -0500, John Snow wrote:
> The old legacy runner no longer seems to work with output logging, so we
> can't see failure logs when a test case fails. The new runner doesn't
> (seem to) support Coverage.py yet, but seeing error output is a more
> important feature.
From: Marc Zyngier
In order to only keep the highmem devices that actually fit in
the PA range, check their location against the range and update
highest_gpa if they fit. If they don't, mark them as disabled.
Signed-off-by: Marc Zyngier
Reviewed-by: Eric Auger
Message-id:
On 18/1/22 19:04, John Snow wrote:
On Tue, Jan 18, 2022 at 5:06 AM Daniel P. Berrangé wrote:
It would be nice to just have this integrated into 'make check' so we
don't need to remember to run a special command.
The CI will run it, but 'make check' doesn't. To add it to make check,
I need
On Thu, 20 Jan 2022 at 13:25, Idan Horowitz wrote:
>
> On Thu, 20 Jan 2022 at 14:32, Peter Maydell wrote:
> >
> >
> > But the code you are effectively removing is never executed
> > for the instructions where you're changing the access function.
> > If you're proposing this as a performance
About the context:
In my case the file format is raw but it's can be also qcow2.
You have right in your explanation in nova it's not a "snapshot" but it's an
image of the instance.
The goal of this image is to put it in glance after to store this image and
create a new instance or rebuild an
On Thu, Jan 20, 2022 at 09:01:55AM +0100, Klaus Jensen wrote:
> +static inline bool nvme_addr_is_iomem(NvmeCtrl *n, hwaddr addr)
> +{
> +hwaddr hi, lo;
> +
> +lo = n->bar0.addr;
> +hi = lo + int128_get64(n->bar0.size);
> +
> +return addr >= lo && addr < hi;
Looks fine considering
The exynos4210_uart_post_load() function assumes that it is passed
the Exynos4210UartState, but it has been attached to the
VMStateDescription for the Exynos4210UartFIFO type. The result is a
SIGSEGV when attempting to load VM state for any machine type
including this device.
Fix the bug by
> On Jan 20, 2022, at 8:27 AM, Paolo Bonzini wrote:
>
> On 1/19/22 22:41, Jagannathan Raman wrote:
>> The compiler path that cmake gets from meson is corrupted. It results in
>> the following error:
>> | -- The C compiler identification is unknown
>> | CMake Error at CMakeLists.txt:35
> -Original Message-
> From: Dr. David Alan Gilbert
> Sent: Thursday, January 20, 2022 1:52 AM
> To: Zhang, Chen
> Cc: Juan Quintela ; qemu-dev de...@nongnu.org>
> Subject: Re: [PATCH 1/3] migration/migration.c: Add missed default error
> handler for migration state
>
> * Zhang Chen
On Thu, Jan 20, 2022, 4:13 AM Daniel P. Berrangé
wrote:
> On Wed, Jan 19, 2022 at 02:39:16PM -0500, John Snow wrote:
> > The old QMP library would actually bind to the server address during
> > __init__(). The new library delays this to the accept() call, because
> > binding occurs inside of the
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/cpu_bits.h | 3 +++
target/riscv/csr.c | 28 ++--
2 files changed, 25 insertions(+), 6 deletions(-)
diff --git a/target/riscv/cpu_bits.h
From: Philippe Mathieu-Daudé
The Marvell 88W8618 is a system-on-chip with an ARM core.
We implement its audio codecs and network interface.
Homogeneous SoC Kconfig are usually defined in the hw/$ARCH
directory. Move it there.
Suggested-by: Richard Henderson
Reviewed-by: Richard Henderson
In process_its_cmd() and process_mapti() we must check the
event ID against a limit defined by the size field in the DTE,
which specifies the number of ID bits minus one. Convert
this code to our num_foo convention:
* change the variable names
* use uint64_t and 1ULL when calculating the number
On Thu, Jan 20, 2022 at 02:33:46PM +0100, Philippe Mathieu-Daudé wrote:
> On 18/1/22 19:04, John Snow wrote:
> > On Tue, Jan 18, 2022 at 5:06 AM Daniel P. Berrangé
> > wrote:
>
> > > It would be nice to just have this integrated into 'make check' so we
> > > don't need to remember to run a
Thank you for the replies. I will note that I suspected SeaBIOS as
well. However, testing 6.2.0 with SeaBIOS 14 (which is the version
that shipped with 6.1.1) did not change the behavior, so I concluded
it was a change in Qemu, despite the fact that SeaBIOS is setting up
the tables.
I was about
On Wed, 8 Dec 2021 at 23:14, Richard Henderson
wrote:
>
> These features are all related and relatively small.
>
> Testing so far has been limited to booting a kernel
> with 64k pages and VA and PA set to 52 bits, which
> excercises LVA and LPA.
>
> There is not yet upstream support for LPA2,
On 22.12.21 18:40, Vladimir Sementsov-Ogievskiy wrote:
Introduce a new driver, that works in pair with copy-before-write to
improve fleecing.
Without fleecing driver, old fleecing scheme looks as follows:
[guest]
|
|root
v
[copy-before-write] -> [temp.qcow2] <--- [nbd export]
|
From: Marc Zyngier
The highmem attribute is nothing but another way to express the
PA range of a VM. To support HW that has a smaller PA range then
what QEMU assumes, pass this PA range to the virt_set_memmap()
function, allowing it to correctly exclude highmem devices
if they are outside of the
From: Lucas Ramage
Buglink: https://gitlab.com/qemu-project/qemu/-/issues/527
Signed-off-by: Lucas Ramage
Message-id: 20220105205628.5491-1-oxr...@gmx.us
Reviewed-by: Peter Maydell
[PMM: Move to docs/system/devices/ rather than top-level;
fix a pre-existing typo in passing]
Signed-off-by:
On 1/19/22 19:34, Kevin Wolf wrote:
So if we go back to a bdrv_invalidate_cache() that does all the graph
manipulations (and asserts that we're in the main loop) and then have a
much smaller bdrv_co_invalidate_cache() that basically just calls into
the driver, would that solve the problem?
I
It's a new year; update the copyright strings for our
help/version/about information and for our documentation.
Signed-off-by: Peter Maydell
---
For once I remembered to do this in January :-)
I suppose at some point we should try to arrange that Sphinx
can pick up the copyright year from a
From: Yanan Wang
Support CPU cluster topology level in generation of ACPI
Processor Properties Topology Table (PPTT).
Signed-off-by: Yanan Wang
Reviewed-by: Andrew Jones
Message-id: 20220107083232.16256-6-wangyana...@huawei.com
Signed-off-by: Peter Maydell
---
hw/acpi/aml-build.c | 18
When an ITS detects an error in a command, it has an
implementation-defined (CONSTRAINED UNPREDICTABLE) choice of whether
to ignore the command, proceeding to the next one in the queue, or to
stall the ITS command queue, processing nothing further. The
behaviour required when the read of the
Fix process_its_cmd() to consistently return CMD_STALL for
memory errors and CMD_CONTINUE for parameter errors, as
we claim in the comments that we do.
Signed-off-by: Peter Maydell
Reviewed-by: Alex Bennée
Reviewed-by: Richard Henderson
Message-id:
On 20/1/22 10:10, Daniel P. Berrangé wrote:
On Wed, Jan 19, 2022 at 06:57:20PM -0500, Yang Zhong wrote:
The SGX NUMA patches were merged into Qemu 7.0 release, we need
clarify detailed version history information and also change
some related comments, which make SGX related comments clearer.
From: Petr Pavlu
Implement support for reading GICC_IIDR. This register is used by the
Linux kernel to recognize that GICv2 with GICC_APRn is present.
Signed-off-by: Petr Pavlu
Message-id: 20220113151916.17978-2-ppa...@suse.cz
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
On Thu, Jan 20, 2022 at 8:05 PM Anup Patel wrote:
> On Thu, Jan 20, 2022 at 1:49 PM Frank Chang
> wrote:
> >
> > On Thu, Jan 20, 2022 at 12:20 AM Anup Patel wrote:
> >>
> >> Hi Frank,
> >>
> >> On Wed, Jan 19, 2022 at 9:07 PM Frank Chang
> wrote:
> >> >
> >> > On Wed, Jan 19, 2022 at 11:27 PM
When we still have an AIOCB registered for DMA operations, we try to
settle the respective operation by draining the BlockBackend associated
with the IDE device.
However, this assumes that every DMA operation is associated with an
increment of the BlockBackend’s in-flight counter (e.g. through
Consider the case:
Thirdparty component works with qcow2 image, and dirty bit is set.
Thirdparty component want to start qemu-img to do some manipulation.
Ofcourse, third party component flushes refcounts and other metadata
before starting QEMU.
But the component don't want to clear dirty bit,
On Thu, Jan 20, 2022 at 12:47:13PM +, Peter Maydell wrote:
> It's a new year; update the copyright strings for our
> help/version/about information and for our documentation.
>
> Signed-off-by: Peter Maydell
> ---
> For once I remembered to do this in January :-)
>
> I suppose at some point
On 20.01.22 17:00, Markus Armbruster wrote:
Kevin Wolf writes:
Am 19.01.2022 um 14:44 hat Hanna Reitz geschrieben:
On 19.01.22 13:58, Markus Armbruster wrote:
Hanna Reitz writes:
We want to add a --daemonize argument to QSD's command line.
Why?
OK, s/we/I/. I find it useful, because
In process_cmdq(), we read 64 bits of the command packet, which
contain the command identifier, which we then switch() on to dispatch
to an appropriate sub-function. However, if address_space_ldq_le()
reports a memory transaction failure, we still read the command
identifier out of the data and
From: Philippe Mathieu-Daudé
We are going to move this code, so fix its style first to avoid:
ERROR: spaces required around that '/' (ctx:VxV)
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Message-id: 20220107184429.423572-3-f4...@amsat.org
Signed-off-by: Peter
Fix process_mapti() to consistently return CMD_STALL for memory
errors and CMD_CONTINUE for parameter errors, as we claim in the
comments that we do.
Signed-off-by: Peter Maydell
Reviewed-by: Alex Bennée
Reviewed-by: Richard Henderson
Message-id:
Thanks for taking the time to write this up!
On Wed, 19 Jan 2022 at 02:30, Alistair Francis wrote:
>
> On Wed, Jan 19, 2022 at 11:19 AM Alistair Francis
> wrote:
> >
> > On Wed, Jan 19, 2022 at 9:22 AM Philipp Tomsich
> > wrote:
> > >
> > > Alistair,
> > >
> > > Some of us (the merit almost
Eric Auger writes:
> -netdev vhost-user,vhostforce is deprecated and vhostforce=on
> should be used instead.
>
> Signed-off-by: Eric Auger
> Reviewed-by: Thomas Huth
Reviewed-by: Alex Bennée
--
Alex Bennée
On 20/1/22 16:40, Daniel P. Berrangé wrote:
On Thu, Jan 20, 2022 at 04:31:14PM +0100, Philippe Mathieu-Daudé wrote:
On 20/1/22 10:10, Daniel P. Berrangé wrote:
On Wed, Jan 19, 2022 at 06:57:20PM -0500, Yang Zhong wrote:
The SGX NUMA patches were merged into Qemu 7.0 release, we need
clarify
In commit d5093d961585f02 we added a VMStateDescription to
the TYPE_ARMV7M object, to handle migration of its Clocks.
However a cut-and-paste error meant we used the wrong struct
name in the VMSTATE_CLOCK() macro arguments. The result was
that attempting a 'savevm' might result in an assertion
Hi all! Here is suggestion of a new option which we need for our
developments in Virtuozzo.
For details look at patch 01.
Vladimir Sementsov-Ogievskiy (2):
qcow2: add keep-dirty open option
iotests: add qcow2-keep-dirty
qapi/block-core.json | 5 +
block/qcow2.h
the initial PC (2022-01-20 09:09:37 +0100)
>
> ----
> m68k pull request 20220120
>
> Fix virt-m68k reboot
>
>
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/7.0
for any user-visible changes.
-- PMM
On 1/20/22 7:16 AM, Peter Maydell wrote:
The exynos4210_uart_post_load() function assumes that it is passed
the Exynos4210UartState, but it has been attached to the
VMStateDescription for the Exynos4210UartFIFO type. The result is a
SIGSEGV when attempting to load VM state for any machine type
> -Original Message-
> From: Dr. David Alan Gilbert
> Sent: Thursday, January 20, 2022 3:41 AM
> To: Zhang, Chen
> Cc: Juan Quintela ; qemu-dev de...@nongnu.org>
> Subject: Re: [PATCH 2/3] migration/migration.c: Avoid COLO boot in postcopy
> migration
>
> * Zhang Chen
On 20/1/22 23:31, Yang Zhong wrote:
The SGX NUMA patches were merged into Qemu 7.0 release, we need
clarify detailed version history information and also change
some related comments, which make SGX related comments clearer.
The QMP command schema promises backwards compatibility as standard.
On 20/01/2022 12.05, Philippe Mathieu-Daudé wrote:
From: Michael Tokarev
For a long time, we assumed that libxml2 is neecessary for parallels
block format support (block/parallels*). However, this format actually
does not use libxml [*]. Since this is the only user of libxml2 in
while qemu
On Wed, 19 Jan 2022 at 12:17, Philippe Mathieu-Daudé wrote:
>
> On 13/1/22 21:20, Philipp Tomsich wrote:
> > This adds the decoder and translation for the XVentanaCondOps custom
> > extension (vendor-defined by Ventana Micro Systems), which is
> > documented at
> >
Hi Alistair and Anup,
On Tue, Jan 18, 2022 at 12:56 PM Alistair Francis wrote:
>
> On Tue, Jan 18, 2022 at 1:31 PM Anup Patel wrote:
> >
> > On Tue, Jan 18, 2022 at 6:47 AM Weiwei Li wrote:
> > >
> > > From: Guo Ren
> > >
> > > Highest bits of PTE has been used for svpbmt, ref: [1], [2], so
From: Philippe Mathieu-Daudé
The Marvell 88W8618 network device is hidden in the Musicpal
machine. Move it into a new unit file under the hw/net/ directory.
Acked-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Message-id: 20220107184429.423572-4-f4...@amsat.org
Reviewed-by: Peter
From: Yanan Wang
Run ./tests/data/acpi/rebuild-expected-aml.sh from build directory
to update PPTT binary. Also empty bios-tables-test-allowed-diff.h.
The disassembled differences between actual and expected PPTT:
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version
From: Marc Zyngier
Just like we can control the enablement of the highmem PCIe region
using highmem_ecam, let's add a control for the highmem GICv3
redistributor region.
Similarily to highmem_ecam, these redistributors are disabled when
highmem is off.
Reviewed-by: Andrew Jones
Signed-off-by:
From: Patrick Venture
Reviewed-by: Hao Wu
Signed-off-by: Patrick Venture
Message-id: 2022072338.1525587-1-vent...@google.com
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
hw/arm/npcm7xx_boards.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git
On Thu, Jan 20, 2022 at 09:44:34AM +, Daniel P. Berrangé wrote:
> On Thu, Jan 20, 2022 at 05:16:01PM +0800, Yang Zhong wrote:
> > On Thu, Jan 20, 2022 at 09:10:34AM +, Daniel P. Berrangé wrote:
> > > On Wed, Jan 19, 2022 at 06:57:20PM -0500, Yang Zhong wrote:
> > > > The SGX NUMA patches
Am 21.10.21 um 12:01 schrieb Stefan Reiter:
'protocol' and 'connected' are better suited as enums than as strings,
make use of that. No functional change intended.
Suggested-by: Markus Armbruster
Reviewed-by: Markus Armbruster
Signed-off-by: Stefan Reiter
---
monitor/hmp-cmds.c | 29
From: Marc Zyngier
Now that the devices present in the extended memory map are checked
against the available PA space and disabled when they don't fit,
there is no need to keep the same checks against highmem, as
highmem really is a shortcut for the PA space being 32bit.
Reviewed-by: Eric Auger
From: Troy Lee
Add the new i3c device to the AST2600 SoC.
Signed-off-by: Troy Lee
Reviewed-by: Graeme Gregory
Reviewed-by: Cédric Le Goater
Tested-by: Graeme Gregory
Message-id: 20220111084546.4145785-3-troy_...@aspeedtech.com
[PMM: tidied commit message]
Signed-off-by: Peter Maydell
---
/seabios-20220118-pull-request' into staging (2022-01-19
> 18:46:28 +)
>
> are available in the Git repository at:
>
> https://git.linaro.org/people/pmaydell/qemu-arm.git
> tags/pull-target-arm-20220120-1
>
> for you to fetch changes up to b9d383ab797f54ae5fa8746117770709
On Wed, Jan 19, 2022 at 11:09 PM Weiwei Li wrote:
>
> Signed-off-by: Weiwei Li
> Signed-off-by: Junqiang Wang
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu.c | 13 +
> 1 file changed, 13 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
>
On Fri, Jan 21, 2022 at 6:48 AM LIU Zhiwei wrote:
>
>
> On 2022/1/20 下午9:47, Guo Ren wrote:
> > Hi Alistair and Anup,
> >
> > On Tue, Jan 18, 2022 at 12:56 PM Alistair Francis
> > wrote:
> >> On Tue, Jan 18, 2022 at 1:31 PM Anup Patel wrote:
> >>> On Tue, Jan 18, 2022 at 6:47 AM Weiwei Li
On 1/20/22 13:47, Peter Maydell wrote:
> It's a new year; update the copyright strings for our
> help/version/about information and for our documentation.
>
> Signed-off-by: Peter Maydell
> ---
> For once I remembered to do this in January :-)
>
> I suppose at some point we should try to
RISC-V International (RVI) has ratified many RISC-V ISA extensions recently[1].
The privileged specification version is also upgraded to v1.12. It means
certain CSRs introduced in v1.12 should only be accessible only if the
priv specification version supported is equal or greater than v1.12.
Doing
On Mon, Jan 10, 2022 at 6:29 PM John Snow wrote:
>
> Based-on: <20220110232521.1922962-1-js...@redhat.com>
> (jsnow/python staging branch)
> GitLab: https://gitlab.com/jsnow/qemu/-/commits/python-qmp-legacy-switch
> CI: https://gitlab.com/jsnow/qemu/-/pipelines/445163212
>
> Hi, this
On Wed, Jan 19, 2022 at 9:52 PM Weiwei Li wrote:
>
> - reuse partial instructions of zbb extension, update extension check for
> them
> - add brev8, pack, packh, packw, unzip, zip instructions
>
> Signed-off-by: Weiwei Li
> Signed-off-by: Junqiang Wang
Acked-by: Alistair Francis
Alistair
On 2022/1/21 上午9:50, Guo Ren wrote:
On Fri, Jan 21, 2022 at 6:48 AM LIU Zhiwei wrote:
On 2022/1/20 下午9:47, Guo Ren wrote:
Hi Alistair and Anup,
On Tue, Jan 18, 2022 at 12:56 PM Alistair Francis wrote:
On Tue, Jan 18, 2022 at 1:31 PM Anup Patel wrote:
On Tue, Jan 18, 2022 at 6:47 AM
- Support akcipher for virtio-crypto.
- Introduce akcipher class.
- Introduce ASN1 decoder into QEMU.
- Implement RSA backend by nettle/hogweed.
Lei He (1):
crypto: Introduce RSA algorithm
Zhenwei Pi (2):
virtio-crypto: header update
virtio_crypto: Support virtio crypto asym operation
On Thu, 20 Jan 2022, Peter Maydell wrote:
> In commit d5093d961585f02 we added a VMStateDescription to
> the TYPE_ARMV7M object, to handle migration of its Clocks.
> However a cut-and-paste error meant we used the wrong struct
> name in the VMSTATE_CLOCK() macro arguments. The result was
>
From: Wilfred Mallawa
This patch removes the left-over/unused `ibex_plic.h` file. Previously
used by opentitan, which now follows the RISC-V standard and uses the
SiFivePlicState.
Fixes: 434e7e021 ("hw/intc: Remove the Ibex PLIC")
Signed-off-by: Wilfred Mallawa
---
include/hw/intc/ibex_plic.h
From: Yifei Jiang
Add target/riscv/kvm.c to place kvm_arch_* function needed by
kvm/kvm-all.c.
Signed-off-by: Yifei Jiang
Signed-off-by: Mingwang Li
Reviewed-by: Alistair Francis
Reviewed-by: Anup Patel
Message-id: 20220112081329.1835-3-jiangyi...@huawei.com
Signed-off-by: Alistair Francis
Virt machine uses privileged specification version 1.12 now.
All other machine continue to use the default one defined for that
machine unless changed to 1.12 by the user explicitly.
Signed-off-by: Atish Patra
---
target/riscv/cpu.c | 8 +---
target/riscv/csr.c | 10 ++
2 files
On 2022/1/20 下午9:47, Guo Ren wrote:
Hi Alistair and Anup,
On Tue, Jan 18, 2022 at 12:56 PM Alistair Francis wrote:
On Tue, Jan 18, 2022 at 1:31 PM Anup Patel wrote:
On Tue, Jan 18, 2022 at 6:47 AM Weiwei Li wrote:
From: Guo Ren
Highest bits of PTE has been used for svpbmt, ref: [1],
Add the definition for ratified privileged specification version v1.12
Signed-off-by: Atish Patra
---
target/riscv/cpu.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 4d630867650a..671f65100b1a 100644
--- a/target/riscv/cpu.h
+++
On 1/18/22 19:44, Fabiano Rosas wrote:
The 405 ISI does not set SRR1 with any exception syndrome bits, only a
clean copy of the MSR.
Signed-off-by: Fabiano Rosas
---
target/ppc/excp_helper.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/target/ppc/excp_helper.c
On Fri, Jan 21, 2022 at 1:49 AM Anup Patel wrote:
>
> This series aims at improving RISC-V spike machine BIOS support by allowing
> use of binary firmware as bios. Further, this also allows us to totally
> remove the ELF bios images shipped with QEMU RISC-V.
>
> These patches can also be found in
On Thu, Jan 20, 2022 at 8:40 AM Daniel P. Berrangé wrote:
>
> On Thu, Jan 20, 2022 at 02:33:46PM +0100, Philippe Mathieu-Daudé wrote:
> > On 18/1/22 19:04, John Snow wrote:
> > > On Tue, Jan 18, 2022 at 5:06 AM Daniel P. Berrangé
> > > wrote:
> >
> > > > It would be nice to just have this
On Fri, Jan 21, 2022 at 1:51 AM LIU Zhiwei wrote:
>
> In this patch set, we process the pc reigsters writes,
> gdb reads and writes, and address calculation under
> different UXLEN settings.
>
> The patch set v8 has been tested by running rv64 Linux with
> rv32 rootfs in compat mode. You can
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