From: "Dr. David Alan Gilbert"
Perform a check on vmsd structures during test runs in the hope
of catching any missing terminators and other simple screwups.
Signed-off-by: Dr. David Alan Gilbert
Reviewed-by: Peter Maydell
Reviewed-by: Juan Quintela
Signed-off-by: Juan Quintela
---
From: Peter Xu
Right now we loop ramblocks for twice, the 1st time chunk the dirty bits with
huge page information; the 2nd time we send the discard ranges. That's not
necessary - we can do them in a single loop.
Signed-off-by: Peter Xu
Reviewed-by: Dr. David Alan Gilbert
Reviewed-by: Juan
On Wed, Jan 26, 2022 at 11:27 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> On 1/25/22 12:29, Warner Losh wrote:
> > +case EXCP_NOCP:
> > +case EXCP_INVSTATE:
> > +/*
> > + * See arm/arm/undefined.c undefinedinstruction();
> > +
/qemu-dm.git
tags/pull-xen-20220127
for you to fetch changes up to a021a2dd8b790437d27db95774969349632f856a:
xen-mapcache: Avoid entry->lock overflow (2022-01-27 15:14:21 +)
Xen patches
- bug fixes for mapcache and io
This series fixes our handling of PSCI calls where the function ID is
not recognized. These are supposed to return an error value, but
currently we instead emulate the SMC or HVC instruction to trap to the
guest at EL3 or EL2. Particularly of note for code review:
* patches 4-9 include some "is
Am 22.01.2022 um 14:49 hat Philippe Mathieu-Daudé geschrieben:
> When building on FreeBSD we get:
>
> [816/6851] Compiling C object libblockdev.fa.p/block_export_fuse.c.o
> ../block/export/fuse.c:628:16: error: use of undeclared identifier
> 'FALLOC_FL_KEEP_SIZE'
> if (mode &
Change the Xilinx ZynqMP-based board xlnx-zcu102 to use the new
boot.c functionality to allow us to enable psci-conduit only if
the guest is being booted in EL1 or EL2, so that if the user runs
guest EL3 firmware code our PSCI emulation doesn't get in its
way.
To do this we stop setting the
Test new qcow2 open option: keep-dirty.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
tests/qemu-iotests/tests/qcow2-keep-dirty | 99 +++
tests/qemu-iotests/tests/qcow2-keep-dirty.out | 31 ++
2 files changed, 130 insertions(+)
create mode 100755
On Fri, 21 Jan 2022 at 16:11, Francisco Iglesias
wrote:
>
> Hi,
>
> This series attempts to add support for Xilinx Versal's PMC SLCR
> (system-level control registers) and OSPI flash memory controller to
> Xilinx Versal virt machine.
>
> The series start with adding a model of Versal's PMC SLCR
> On Jan 25, 2022, at 10:48 AM, Stefan Hajnoczi wrote:
>
> On Wed, Jan 19, 2022 at 04:42:06PM -0500, Jagannathan Raman wrote:
>> + * The client subsequetly asks the remote server for any data that
>
> subsequently
>
>> +static void vfu_mig_state_running(vfu_ctx_t *vfu_ctx)
>> +{
>> +
On 1/27/22 7:11 PM, Li Zhang wrote:
On 1/27/22 10:53 AM, Juan Quintela wrote:
Li Zhang wrote:
Clean up some unnecessary code
Signed-off-by: Li Zhang
Hi
---
migration/multifd.c | 12 +++-
1 file changed, 3 insertions(+), 9 deletions(-)
diff --git a/migration/multifd.c
On 1/27/22 7:31 PM, Li Zhang wrote:
On 1/27/22 7:11 PM, Li Zhang wrote:
On 1/27/22 10:53 AM, Juan Quintela wrote:
Li Zhang wrote:
Clean up some unnecessary code
Signed-off-by: Li Zhang
Hi
---
migration/multifd.c | 12 +++-
1 file changed, 3 insertions(+), 9 deletions(-)
* Vivek Goyal (vgo...@redhat.com) wrote:
> Move core file creation bits in a separate function. Soon this is going
> to get more complex as file creation need to set security context also.
> And there will be multiple modes of file creation in next patch.
>
> Signed-off-by: Vivek Goyal
Hi
On Thu, Jan 27, 2022 at 10:29 PM BALATON Zoltan wrote:
> Hello,
>
> We've found a problem with mouse pointer jumping around then constantly
> warping making it unusable which only seems to happen with the gtk
> display. Similar problem was reported with MacOS guests but now we could
> also
The 74xx don't have MSR_HV so all the LPES0 logic can be removed.
Also remove the BookE IRQ code.
Signed-off-by: Fabiano Rosas
---
target/ppc/excp_helper.c | 38 --
1 file changed, 38 deletions(-)
diff --git a/target/ppc/excp_helper.c
The 74xx does not have alternate/hypervisor Save and Restore
Registers, so we can set SRR0 and SRR1 directly.
Signed-off-by: Fabiano Rosas
---
target/ppc/excp_helper.c | 13 ++---
1 file changed, 2 insertions(+), 11 deletions(-)
diff --git a/target/ppc/excp_helper.c
On 1/23/22 05:24, Peter Maydell wrote:
The MemoryRegionOps gicv3_its_translation_ops currently provides only
a .write_with_attrs function, because the only register in this
region is the write-only GITS_TRANSLATER. However, if you don't
provide a read function and the guest tries reading from
This series patch add softmmu support for LoongArch.
The latest kernel:
* https://github.com/loongson/linux/tree/loongarch-next
The latest uefi:
* https://github.com/loongson/edk2
* https://github.com/loongson/edk2-platforms
The manual:
*
On 1/23/22 05:24, Peter Maydell wrote:
Implement the ITS MOVI command. This command specifies a (physical) LPI
by DeviceID and EventID and provides a new ICID for it. The ITS must
find the interrupt translation table entry for the LPI, which will
tell it the old ICID. It then moves the pending
This includes:
- TLBSRCH
- TLBRD
- TLBWR
- TLBFILL
- TLBCLR
- TLBFLUSH
- INVTLB
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
target/loongarch/disas.c | 17 +
target/loongarch/helper.h | 12 +
.../insn_trans/trans_privileged.c.inc |
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
hw/loongarch/Kconfig | 4
hw/loongarch/fw_cfg.c| 33 ++
hw/loongarch/fw_cfg.h| 15 ++
hw/loongarch/loongson3.c | 35
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
hw/loongarch/loongson3.c | 81
include/hw/loongarch/loongarch.h | 5 ++
2 files changed, 86 insertions(+)
diff --git a/hw/loongarch/loongson3.c b/hw/loongarch/loongson3.c
index
On Fri, Jan 28, 2022 at 7:24 AM Alistair Francis wrote:
>
> On Thu, Jan 20, 2022 at 1:55 AM Anup Patel wrote:
> >
> > From: Anup Patel
> >
> > The RISC-V AIA (Advanced Interrupt Architecture) defines a new
> > interrupt controller for MSIs (message signal interrupts) called
> > IMSIC (Incoming
This patch add the irq hierarchy for the virt board.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
hw/loongarch/loongson3.c | 88 ++
include/hw/pci-host/ls7a.h | 13 ++
2 files changed, 101 insertions(+)
diff --git
Emulate a 3A5000 board use the new loongarch instruction.
3A5000 belongs to the Loongson3 series processors.
The board consists of a 3A5000 cpu model and the 7A1000
bridge. The host 3A5000 board is really complicated and
contains many functions.Now for the tcg softmmu mode
only part functions are
This patch realize the EIOINTC interrupt controller.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
hw/intc/Kconfig| 3 +
hw/intc/loongarch_extioi.c | 409 +
hw/intc/meson.build| 1 +
hw/intc/trace-events
Add tree nodes for 3A5000 device tree.
- cpu nodes;
- fw_cfg nodes;
- pcie nodes.
The lastest loongarch bios have supported fdt.
- https://github.com/loongson/edk2
- https://github.com/loongson/edk2-platforms
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
hw/loongarch/loongson3.c
在 2022/1/22 上午4:27, Eugenio Pérez 写道:
Is needed so vhost-vdpa knows the device's kick event fd.
Signed-off-by: Eugenio Pérez
---
hw/virtio/vhost-shadow-virtqueue.h | 4
hw/virtio/vhost-shadow-virtqueue.c | 10 +-
2 files changed, 13 insertions(+), 1 deletion(-)
diff --git
在 2022/1/22 上午4:27, Eugenio Pérez 写道:
This function allows the vhost-vdpa backend to override kick_fd.
Signed-off-by: Eugenio Pérez
---
hw/virtio/vhost-shadow-virtqueue.h | 1 +
hw/virtio/vhost-shadow-virtqueue.c | 45 ++
2 files changed, 46 insertions(+)
在 2022/1/22 上午4:27, Eugenio Pérez 写道:
At this moment no buffer forwarding will be performed in SVQ mode: Qemu
just forward the guest's kicks to the device. This commit also set up
SVQs in the vhost device.
Host memory notifiers regions are left out for simplicity, and they will
not be
On 1/23/22 05:24, Peter Maydell wrote:
The ITS-related parts of the redistributor code make some checks for
whether registers like GICR_PROPBASER and GICR_PENDBASER are zero.
There is no requirement in the specification for treating zeroes in
these address registers specially -- they contain
On 1/23/22 05:24, Peter Maydell wrote:
The GICR_CTLR.CES bit is a read-only bit which is set to 1 to indicate
that the GICR_CTLR.EnableLPIs bit can be written to 0 to disable
LPIs (as opposed to allowing LPIs to be enabled but not subsequently
disabled). Our implementation permits this, so
On 1/23/22 05:24, Peter Maydell wrote:
Currently when we fill in a TableDesc based on the value the guest
has written to the GITS_BASER register, we calculate both:
* num_entries : the number of entries in the table, constrained
by the amount of memory the guest has given it
* num_ids :
On 1/23/22 05:24, Peter Maydell wrote:
The ITS has a bank of 8 GITS_BASER registers, which allow the
guest to specify the base address of various data tables. Each
register has a read-only type field indicating which table it is for
and a read-write field where the guest can write in the base
This series patch add softmmu support for LoongArch.
The latest kernel:
* https://github.com/loongson/linux/tree/loongarch-next
The latest uefi:
* https://github.com/loongson/edk2
* https://github.com/loongson/edk2-platforms
The manual:
*
This includes:
- IOCSR{RD/WR}.{B/H/W/D}
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
target/loongarch/cpu.c| 8 +
target/loongarch/cpu.h| 4 +
target/loongarch/disas.c | 8 +
target/loongarch/helper.h
Loongson-3A5000 support 14 interrupts from 64 - 77(Timer->75 IPI->76)
Loongson-3A5000 and ls7a form a legacy model and extended model irq
hierarchy.Tcg mode emulate a simplified extended model which
has no Legacy I/O Interrupt Controller(LIOINTC) and LPC.
e.g:
|+-++-+
This patch add ls7a rtc device support.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
hw/loongarch/Kconfig | 1 +
hw/loongarch/loongson3.c | 4 +
hw/rtc/Kconfig | 3 +
hw/rtc/ls7a_rtc.c | 322 +
On Thu, Jan 13, 2022 at 11:52 AM Weiwei Li wrote:
>
> Co-authored-by: ardxwe
> Signed-off-by: Weiwei Li
> Signed-off-by: Junqiang Wang
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu_helper.c | 6 +-
> target/riscv/csr.c| 25 -
>
在 2022/1/28 上午11:57, Peter Xu 写道:
On Thu, Jan 27, 2022 at 10:24:27AM +0100, Eugenio Perez Martin wrote:
On Thu, Jan 27, 2022 at 9:06 AM Peter Xu wrote:
On Tue, Jan 25, 2022 at 10:40:01AM +0100, Eugenio Perez Martin wrote:
So I think that the first step to remove complexity from the old one
On Thu, Jan 13, 2022 at 11:52 AM Weiwei Li wrote:
>
> - update extension check REQUIRE_ZFINX_OR_F
> - update single float point register read/write
> - disable nanbox_s check
>
> Co-authored-by: ardxwe
> Signed-off-by: Weiwei Li
> Signed-off-by: Junqiang Wang
> Reviewed-by: Richard
21.01.2022 13:46, Vladimir Sementsov-Ogievskiy wrote:
20.01.2022 19:11, Hanna Reitz wrote:
On 22.12.21 18:40, Vladimir Sementsov-Ogievskiy wrote:
Introduce a new driver, that works in pair with copy-before-write to
improve fleecing.
Without fleecing driver, old fleecing scheme looks as
From: Peter Xu
It will just never fail. Drop those return values where they're constantly
zeros.
A tiny touch-up on the tracepoint so trace_ram_postcopy_send_discard_bitmap()
is called after the logic itself (which sounds more reasonable).
Signed-off-by: Peter Xu
Reviewed-by: Philippe
Signed-off-by: Juan Quintela
Reviewed-by: Dr. David Alan Gilbert
---
migration/multifd.h | 3 ++-
migration/multifd.c | 4 ++--
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/migration/multifd.h b/migration/multifd.h
index be460f821b..4dda900a0b 100644
--- a/migration/multifd.h
Change the iMX-SoC based boards to use the new boot.c functionality
to allow us to enable psci-conduit only if the guest is being booted
in EL1 or EL2, so that if the user runs guest EL3 firmware code our
PSCI emulation doesn't get in its way.
To do this we stop setting the psci-conduit property
From: Philippe Mathieu-Daudé
postcopy_send_discard_bm_ram() always return zero. Since it can't
fail, simplify and do not return anything.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: David Edmondson
Reviewed-by: Juan Quintela
Signed-off-by: Juan Quintela
---
migration/ram.c | 6
Markus Armbruster writes:
> Alex Bennée writes:
>
>> Victor Toso writes:
>>
>>> Similar to f7160f3218 "schemas: Add vim modeline"
>>>
>>> Signed-off-by: Victor Toso
>>> ---
>>> qapi/audio.json | 1 +
>>> qapi/compat.json | 1 +
>>> qapi/replay.json | 1 +
>>> qapi/trace.json | 1 +
>>> 4
From: Peter Xu
Temp pages will need to grow if we want to have multiple channels for postcopy,
because each channel will need its own temp page to cache huge page data.
Before doing that, cleanup the related code. No functional change intended.
Since at it, touch up the errno handling a
* Vivek Goyal (vgo...@redhat.com) wrote:
> Kernel version 5.17 has increased the size of "struct fuse_init_in" struct.
> Previously this struct was 16 bytes and now it has been extended to
> 64 bytes in size.
>
> Once qemu headers are updated to latest, it will expect to receive 64 byte
> size
* Vivek Goyal (vgo...@redhat.com) wrote:
> Add some code to parse extended "struct fuse_init_in". And use a local
> variable "flag" to represent 64 bit flags. This will make it easier
> to add more features without having to worry about two 32bit flags (->flags
> and ->flags2) in "fuse_struct_in".
Hello,
We've found a problem with mouse pointer jumping around then constantly
warping making it unusable which only seems to happen with the gtk
display. Similar problem was reported with MacOS guests but now we could
also reproduce with MorphOS on pegasos2 and thus confirm it's not a guest
On Wed, 12 Jan 2022 at 00:25, Titus Rwantare wrote:
>
> From: Patrick Venture
>
> Signed-off-by: Patrick Venture
> Reviewed-by: Titus Rwantare
Reviewed-by: Peter Maydell
thanks
-- PMM
Introduce a new powerpc_excp function specific for PowerPC 74xx
CPUs. This commit copies powerpc_excp_legacy verbatim so the next one
has a clean diff.
Signed-off-by: Fabiano Rosas
---
target/ppc/excp_helper.c | 474 +++
1 file changed, 474 insertions(+)
On 11/18/21 06:57, Philippe Mathieu-Daudé wrote:
Trivial fix for CVE-2021-3507.
Philippe Mathieu-Daudé (2):
hw/block/fdc: Prevent end-of-track overrun (CVE-2021-3507)
tests/qtest/fdc-test: Add a regression test for CVE-2021-3507
hw/block/fdc.c | 8
On Thu, Jan 27, 2022 at 8:48 PM Marc-André Lureau <
marcandre.lur...@gmail.com> wrote:
> Hi
>
> On Thu, Jan 27, 2022 at 10:29 PM BALATON Zoltan
> wrote:
>
>> Hello,
>>
>> We've found a problem with mouse pointer jumping around then constantly
>> warping making it unusable which only seems to
On 1/23/22 05:24, Peter Maydell wrote:
The list of #defines for the ITS command packet numbers is neither
in alphabetical nor numeric order. Sort it into numeric order.
Signed-off-by: Peter Maydell
---
hw/intc/gicv3_internal.h | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
On 1/23/22 05:24, Peter Maydell wrote:
The current ITS code clears GITS_CREADR when GITS_CTLR.ENABLED is set.
This is not correct -- guest code can validly clear ENABLED and then
set it again and expect the ITS to continue processing where it left
off. Remove the erroneous assignment.
On 1/23/22 05:24, Peter Maydell wrote:
Implement the ITS MOVALL command, which takes all the pending
interrupts on a source redistributor and makes the not-pending on
that source redistributor and pending on a destination redistributor.
This is a GICv3 ITS command which we forgot to implement.
This patch realize the IPI interrupt controller.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
hw/intc/Kconfig | 3 +
hw/intc/loongarch_ipi.c | 164
hw/intc/meson.build | 1 +
hw/intc/trace-events|
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
Reviewed-by: Richard Henderson
---
qapi/machine-target.json | 6 --
target/loongarch/cpu.c | 26 ++
2 files changed, 30 insertions(+), 2 deletions(-)
diff --git a/qapi/machine-target.json
This is a model of the PCIe Host Bridge found on a Loongson-5000
processor. It includes a interrupt controller, some interface for
pci and nonpci devices. Mainly emulate part of it that is not
exactly the same as the host and only use part devices for
tcg mode. It support for MSI and MSIX
This patch realize the PCH-PIC interrupt controller.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
hw/intc/Kconfig | 4 +
hw/intc/loongarch_pch_pic.c | 488
hw/intc/meson.build | 1 +
hw/intc/trace-events
On Thu, Jan 27, 2022 at 10:24:27AM +0100, Eugenio Perez Martin wrote:
> On Thu, Jan 27, 2022 at 9:06 AM Peter Xu wrote:
> >
> > On Tue, Jan 25, 2022 at 10:40:01AM +0100, Eugenio Perez Martin wrote:
> > > So I think that the first step to remove complexity from the old one
> > > is to remove
When try to get one msr from KVM, I found there's no such kind of
existing interface while kvm_put_one_msr() is there. So here comes
the patch. It'll remove redundant preparation code before finally
call KVM_GET_MSRS IOCTL.
No functional change intended.
Signed-off-by: Yang Weijiang
---
On Mon, Jan 24, 2022 at 5:54 PM Frédéric Pétrot
wrote:
>
> The addition of uxl support in gdbstub adds a few checks on the maximum
> register length, but omitted MXL_RV128, leading to the occurence of
> "code should not be reached" in a few places.
> This patch makes rv128 react as rv64 for gdb,
On Thu, Jan 13, 2022 at 11:51 AM Weiwei Li wrote:
>
> Co-authored-by: ardxwe
> Signed-off-by: Weiwei Li
> Signed-off-by: Junqiang Wang
> Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu.c | 12
> target/riscv/cpu.h |
On Thu, Jan 13, 2022 at 11:56 AM Weiwei Li wrote:
>
> Co-authored-by: ardxwe
> Signed-off-by: Weiwei Li
> Signed-off-by: Junqiang Wang
> Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu.c | 5 +
> 1 file changed, 5 insertions(+)
>
> diff
On Tue, Jan 25, 2022 at 5:47 PM Weiwei Li wrote:
>
> Signed-off-by: Weiwei Li
> Signed-off-by: Junqiang Wang
> Reviewed-by: Anup Patel
Could you please add a commit message to this patch?
Alistair
> ---
> target/riscv/cpu_helper.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git
在 2022/1/22 上午4:27, Eugenio Pérez 写道:
Vhost shadow virtqueue (SVQ) is an intermediate jump for virtqueue
notifications and buffers, allowing qemu to track them. While qemu is
forwarding the buffers and virtqueue changes, it is able to commit the
memory it's being dirtied, the same way regular
Hi,
On 2022/1/26 17:14, Igor Mammedov wrote:
On Wed, 26 Jan 2022 13:24:10 +0800
Gavin Shan wrote:
The default CPU-to-NUMA association is given by mc->get_default_cpu_node_id()
when it isn't provided explicitly. However, the CPU topology isn't fully
considered in the default association and
-EMISSINGPATCHDESCRIPTION
Please avoid sending patches without patch description. E.g. explain here
*why* this needs to be adjusted.
Thanks,
Thomas
On 28/01/2022 01.56, Will Cohen wrote:
Signed-off-by: Fabian Franz
Signed-off-by: Will Cohen
---
tests/qtest/virtio-9p-test.c | 2 +-
在 2022/1/28 下午1:40, Alistair Francis 写道:
On Tue, Jan 25, 2022 at 5:47 PM Weiwei Li wrote:
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Anup Patel
Could you please add a commit message to this patch?
Alistair
OK. I'll add it.
Regards,
Weiwei Li
---
On Fri, Jan 28, 2022 at 6:56 AM Jason Wang wrote:
>
>
> 在 2022/1/28 上午11:57, Peter Xu 写道:
> > On Thu, Jan 27, 2022 at 10:24:27AM +0100, Eugenio Perez Martin wrote:
> >> On Thu, Jan 27, 2022 at 9:06 AM Peter Xu wrote:
> >>> On Tue, Jan 25, 2022 at 10:40:01AM +0100, Eugenio Perez Martin wrote:
>
On 1/23/22 05:24, Peter Maydell wrote:
The ITS currently has no tracepoints; add a minimal set
that allows basic monitoring of guest register accesses and
reading of commands from the command queue.
Signed-off-by: Peter Maydell
---
hw/intc/arm_gicv3_its.c | 11 +++
On 1/23/22 05:24, Peter Maydell wrote:
In an SMP system it can be unclear which CPU is taking an exception;
add the CPU index (which is the same value used in the TCG 'Trace
%d:' logging) to the "Taking exception" log line to clarify it.
Signed-off-by: Peter Maydell
---
target/arm/internals.h
On 1/23/22 05:24, Peter Maydell wrote:
The GICD_CTLR distributor register has enable bits which control
whether the different interrupt groups (Group 0, Non-secure Group 1
and Secure Group 1) are forwarded to the CPU. We get this right for
traditional interrupts, but forgot to account for it
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
target/loongarch/cpu-csr.h | 236 +
target/loongarch/cpu.c | 35 ++
target/loongarch/cpu.h | 57 +
3 files changed, 328 insertions(+)
create mode 100644 target/loongarch/cpu-csr.h
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
docs/system/loongarch/loongson3.rst | 78 +
target/loongarch/README | 28 +++
2 files changed, 106 insertions(+)
create mode 100644 docs/system/loongarch/loongson3.rst
diff --git
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
Reviewed-by: Richard Henderson
---
target/loongarch/cpu.c | 3 ++
target/loongarch/internals.h | 4 ++
target/loongarch/machine.c | 85
target/loongarch/meson.build | 6 +++
4 files changed, 98
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
target/loongarch/constant_timer.c | 62 +++
target/loongarch/cpu.h| 10 +
target/loongarch/meson.build | 1 +
3 files changed, 73 insertions(+)
create mode 100644
1.This patch Add loongarch interrupt and exception handle.
2.Rename the user excp to the exccode from the csr defintions.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
linux-user/loongarch64/cpu_loop.c | 8 +-
target/loongarch/cpu.c| 251
This includes:
-RDTIME{L/H}.W
-RDTIME.D
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
target/loongarch/helper.h | 1 +
target/loongarch/insn_trans/trans_extra.c.inc | 32 +++
target/loongarch/op_helper.c | 6
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
softmmu/qdev-monitor.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/softmmu/qdev-monitor.c b/softmmu/qdev-monitor.c
index 01f3834db5..49491d74a1 100644
--- a/softmmu/qdev-monitor.c
+++ b/softmmu/qdev-monitor.c
@@
Add a simple acpi model for LoongArch cpu
More complex functions will be added later
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
hw/acpi/Kconfig | 4 +
hw/acpi/ls7a.c | 374 ++
hw/acpi/meson.build | 1 +
- We write a very minimal softmmu harness.
- This is a very simple smoke test with no need to run a full Linux/kernel.
- The Makefile.softmmu-target record the rule to run.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
tests/tcg/loongarch64/Makefile.softmmu-target | 33 +++
On Tue, Jan 25, 2022 at 5:49 PM Weiwei Li wrote:
>
>
> 在 2022/1/25 下午5:00, Guo Ren 写道:
> > On Tue, Jan 25, 2022 at 4:54 PM LIU Zhiwei wrote:
> >>
> >> On 2022/1/25 16:40, Guo Ren wrote:
> >>> On Tue, Jan 25, 2022 at 4:34 PM LIU Zhiwei wrote:
> On 2022/1/25 14:45, Weiwei Li wrote:
> >
1.Add uart,virtio-net,vga and usb for 3A5000.
2.Add irq set and map for the pci host. Non pci device
use irq 0-16, pci device use 16-64.
3.Add some unimplented device to emulate guest unused
memory space.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
hw/loongarch/Kconfig | 7
在 2022/1/22 上午4:27, Eugenio Pérez 写道:
vhost_vdpa_set_features and vhost_vdpa_init need to use
vhost_vdpa_get_features in svq mode.
vhost_vdpa_dev_start needs to use almost all _set_ functions:
vhost_vdpa_set_vring_dev_kick, vhost_vdpa_set_vring_dev_call,
vhost_vdpa_set_dev_vring_base and
在 2022/1/22 上午4:27, Eugenio Pérez 写道:
This series enables shadow virtqueue (SVQ) for vhost-vdpa devices. This
is intended as a new method of tracking the memory the devices touch
during a migration process: Instead of relay on vhost device's dirty
logging capability, SVQ intercepts the VQ
On 1/23/22 05:24, Peter Maydell wrote:
In our implementation, all ITSes connected to a GIC share a single
AddressSpace, which we keep in the GICv3State::dma_as field and
initialized based on the GIC's 'sysmem' property. The right place
to set it up by calling address_space_init() is therefore in
On 1/23/22 05:24, Peter Maydell wrote:
The ITS specification says that when the guest writes to GITS_CBASER
this causes GITS_CREADR to be cleared. However it does not have an
equivalent clause for GITS_CWRITER. (This is because GITS_CREADR is
read-only, but GITS_CWRITER is writable and the
This includes:
-CACOP
-LDDIR
-LDPTE
-ERTN
-DBCL
-IDLE
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
target/loongarch/cpu.h| 2 +
target/loongarch/disas.c | 17
target/loongarch/helper.h | 4 +
This includes:
- CSRRD
- CSRWR
- CSRXCHG
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
target/loongarch/cpu.h| 88
target/loongarch/csr_helper.c | 112
target/loongarch/disas.c | 15 +++
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
target/loongarch/cpu-param.h | 2 +-
target/loongarch/cpu.c| 30
target/loongarch/cpu.h| 42 -
target/loongarch/internals.h | 9 +
target/loongarch/machine.c| 17 ++
target/loongarch/meson.build |
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
configs/targets/loongarch64-softmmu.mak | 1 +
gdb-xml/loongarch-base64.xml| 43 +++
gdb-xml/loongarch-fpu64.xml | 57 +++
target/loongarch/cpu.c | 7 ++
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
hw/loongarch/Kconfig | 1 +
hw/loongarch/loongson3.c | 42
include/hw/loongarch/loongarch.h | 1 +
3 files changed, 44 insertions(+)
diff --git a/hw/loongarch/Kconfig
This patch realize PCH-MSI interrupt controller.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
hw/intc/Kconfig | 5 ++
hw/intc/loongarch_pch_msi.c | 75 +
hw/intc/meson.build | 1 +
hw/intc/trace-events
在 2022/1/22 上午4:27, Eugenio Pérez 写道:
At this mode no buffer forwarding will be performed in SVQ mode: Qemu
will just forward the guest's kicks to the device.
Also, host notifiers must be disabled at SVQ start, and they will not
start if SVQ has been enabled when the device is stopped. This
在 2022/1/28 下午2:09, Alistair Francis 写道:
On Thu, Jan 13, 2022 at 11:52 AM Weiwei Li wrote:
- update extension check REQUIRE_ZFINX_OR_F
- update single float point register read/write
- disable nanbox_s check
Co-authored-by: ardxwe
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang
On Fri, Jan 28, 2022 at 6:59 AM Jason Wang wrote:
>
>
> 在 2022/1/22 上午4:27, Eugenio Pérez 写道:
> > vhost_vdpa_set_features and vhost_vdpa_init need to use
> > vhost_vdpa_get_features in svq mode.
> >
> > vhost_vdpa_dev_start needs to use almost all _set_ functions:
> >
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