Hi Richard,
On 2022/6/10 上午2:42, Richard Henderson wrote:
void helper_asrtle_d(CPULoongArchState *env, target_ulong rj,
target_ulong rk)
{
if (rj > rk) {
+#ifdef CONFIG_USER_ONLY
+ cpu_loop_exit_sigsegv(env_cpu(env), GETPC(),
+ MMU_DATA_LOAD, true,
On 09/06/2022 11:53, Peter Maydell wrote:
On Sun, 22 May 2022 at 19:19, Mark Cave-Ayland
wrote:
This enables use to expose the register memory region of the I8042_MMIO device
using sysbus_init_mmio().
Signed-off-by: Mark Cave-Ayland
---
hw/input/pckbd.c | 8
1 file changed, 8
On 09/06/2022 12:21, Peter Maydell wrote:
On Sun, 22 May 2022 at 19:20, Mark Cave-Ayland
wrote:
Add a qdev gpio input in lasips2_init() by taking the existing
lasips2_port_set_irq()
function, updating it accordingly and then renaming to lasips2_set_irq(). Use
these
new qdev gpio inputs to
On 09/06/2022 11:49, Peter Maydell wrote:
On Sun, 22 May 2022 at 19:19, Mark Cave-Ayland
wrote:
This allows the I8042_MMIO reset function to be registered directly within the
DeviceClass rather than using qemu_register_reset() directly.
Signed-off-by: Mark Cave-Ayland
---
On 06/09/22 16:03, Kevin Locke wrote:
> On Thu, 2022-06-09 at 09:45 +0200, Laszlo Ersek wrote:
>> (2) Assigned PCI Express GPUs that offer legacy VGA compatibility,
>> and that such compatibility is expected of (due to booting with
>> SeaBIOS, or due to UEFI driver bugs or
On Tue, May 31, 2022 at 01:23:26PM -0700, Dongwon Kim wrote:
> Detaching any addtional guest displays in case there are multiple
> displays assigned to the guest OS (e.g. max_outputs=n) so that
> all of them are visible upon lauching.
>
> Cc: Daniel P. Berrangé
> Cc: Markus Armbruster
> Cc:
On Thu, Jun 09, 2022 at 04:12:25PM +0200, BALATON Zoltan wrote:
> On Thu, 9 Jun 2022, Gerd Hoffmann wrote:
> > On Wed, May 18, 2022 at 12:37:18PM +0200, Paolo Bonzini wrote:
> > > On 5/17/22 21:47, BALATON Zoltan wrote:
> > > > On Mon, 9 May 2022, BALATON Zoltan wrote:
> > > > > On Mon, 2 May
On 09/06/2022 12:18, Peter Maydell wrote:
On Sun, 22 May 2022 at 19:20, Mark Cave-Ayland
wrote:
This enables the IRQ to be wired up using qdev_connect_gpio_out() in
lasips2_initfn().
Signed-off-by: Mark Cave-Ayland
---
hw/input/lasips2.c | 8
include/hw/input/lasips2.h
On 09/06/2022 11:58, Peter Maydell wrote:
On Sun, 22 May 2022 at 19:19, Mark Cave-Ayland
wrote:
This exposes the I8042_MMIO device to the caller to allow the register memory
region to be mapped outside of i8042_mm_init().
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Peter Maydell
I'm
On Tue, May 31, 2022 at 01:23:27PM -0700, Dongwon Kim wrote:
> New integer array parameter, 'monitor' is for specifying the target
> displays where individual QEMU windows are placed upon launching.
>
> The array contains a series of numbers representing the monitor where
> QEMU windows are
On 09/06/2022 12:05, Peter Maydell wrote:
On Sun, 22 May 2022 at 19:20, Mark Cave-Ayland
wrote:
Define the gpio for the PS2 output IRQ in ps2_init() and add logic to optionally
use it in ps2_raise_irq() and ps2_lower_irq() if the gpio is connected. If the
gpio is not connected then call the
From: Igor Mammedov
Signed-off-by: Igor Mammedov
Acked-by: Gerd Hoffmann
Message-Id: <20220608135340.3304695-9-imamm...@redhat.com>
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsirkin
---
include/hw/isa/isa.h | 1 -
hw/isa/isa-bus.c | 12 +---
2 files changed, 1
From: Igor Mammedov
wire AcpiDevAmlIf interface to build ich9-smb and its slave
devices AML. It will be used by followup patches to switch
from creating AML in ad-hoc way to a more systematic one
that will scan present devices and ask them to provide
their AML code like it's done with ISA
From: Mark Cave-Ayland
This is in preparation for separating out the VIOT ACPI table build from the
PCI host bridge numeration.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Ani Sinha
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20220525173232.31429-2-mark.cave-ayl...@ilande.co.uk>
From: Mark Cave-Ayland
Instead of generating each table entry inline, move the individual PCI host
bridge
table entry generation to a separate build_pci_host_range() function.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Ani Sinha
Reviewed-by: Philippe Mathieu-Daudé
Message-Id:
From: Jonathan Cameron
Refactoring step on path to moving all CXL state out of
MachineState.
Signed-off-by: Jonathan Cameron
Reviewed-by: Ben Widawsky
Message-Id: <20220608145440.26106-3-jonathan.came...@huawei.com>
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsirkin
---
From: Jonathan Cameron
As the CXLState will no long be accessible via MachineState
at time of PXB_CXL realization, come back later from the machine specific
code to fill in the missing memory region setup. Only at this stage
is it possible to check if cxl=on, so that check is moved to this
later
From: Mark Cave-Ayland
This ensures that the VIOT ACPI table output is always stable for a given PCI
topology by ensuring that entries are ordered according to min_bus.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Ani Sinha
Reviewed-by: Philippe Mathieu-Daudé
Message-Id:
From: Igor Mammedov
Signed-off-by: Igor Mammedov
Reviewed-by: Ani Sinha
Acked-by: Gerd Hoffmann
Message-Id: <20220608135340.3304695-33-imamm...@redhat.com>
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsirkin
---
hw/i386/acpi-build.c | 10 ++
1 file changed, 2
From: Akihiko Odaki
Signed-off-by: Akihiko Odaki
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20220529082508.89097-1-akihiko.od...@gmail.com>
Signed-off-by: Gerd Hoffmann
---
ui/cocoa.m | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/ui/cocoa.m b/ui/cocoa.m
index
From: Akihiko Odaki
Signed-off-by: Akihiko Odaki
Message-Id: <20220226115516.59830-4-akihiko.od...@gmail.com>
Signed-off-by: Gerd Hoffmann
---
include/hw/virtio/virtio-gpu.h | 1 +
hw/display/virtio-gpu-base.c | 1 +
hw/display/virtio-gpu.c| 1 +
3 files changed, 3 insertions(+)
From: "Hongren (Zenithal) Zheng"
Signed-off-by: Hongren (Zenithal) Zheng
Message-Id:
Signed-off-by: Gerd Hoffmann
---
docs/system/device-emulation.rst | 1 +
docs/system/devices/canokey.rst | 168 +++
2 files changed, 169 insertions(+)
create mode 100644
On Fri, Jun 10, 2022 at 3:00 PM dramforever wrote:
>
> Hi Anup Patel,
>
> I think there are some misunderstandings of the privileged spec with regards
> to
> [m|h]tinst handling. Here are some possible issues I've found:
>
> > +case OPC_RISC_C_FUNC_FLD_LQ:
> > +if
From: Igor Mammedov
.. which will be used by follow up smbus-ipmi test-case
Signed-off-by: Igor Mammedov
Message-Id: <20220608135340.3304695-10-imamm...@redhat.com>
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsirkin
---
tests/qtest/bios-tables-test-allowed-diff.h | 1 +
From: Igor Mammedov
Signed-off-by: Igor Mammedov
Message-Id: <20220608135340.3304695-13-imamm...@redhat.com>
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsirkin
---
tests/qtest/bios-tables-test-allowed-diff.h | 1 +
1 file changed, 1 insertion(+)
diff --git
From: Igor Mammedov
Signed-off-by: Igor Mammedov
Acked-by: Gerd Hoffmann
Message-Id: <20220608135340.3304695-8-imamm...@redhat.com>
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsirkin
---
hw/input/pckbd.c | 14 +-
1 file changed, 9 insertions(+), 5 deletions(-)
From: Igor Mammedov
expected AML change:
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
I2cSerialBusV2 (0x, ControllerInitiated, 0x000186A0,
- AddressingMode7Bit, "\\_SB.PCI0.SMB0",
+ AddressingMode7Bit, "^",
From: Jonathan Cameron
The CEDT table includes addreses of host bridge registers.
There are allocated in a different order due to the previous
patch, so update to the table is needed.
Signed-off-by: Jonathan Cameron
Reviewed-by: Ben Widawsky
Message-Id:
From: Jonathan Cameron
This removes the last of the CXL code from the MachineState where it
is visible to all Machines to only those that support CXL (currently i386/pc)
As i386/pc always support CXL now, stop allocating the state independently.
Note the pxb register hookup code runs even if
From: Igor Mammedov
@@ -145,6 +145,37 @@ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC",
0x0001)
{
Name (_ADR, 0x001F) // _ADR: Address
OperationRegion (PIRQ, PCI_Config, 0x60, 0x0C)
+Device (PEVT)
+{
+
On Thu, May 19, 2022 at 6:35 PM Eric DeVolder wrote:
>
>
>
> On 5/13/22 09:10, Ani Sinha wrote:
> > At any step when any validation fail in check_erst_backend_storage(), there
> > is
> > no need to continue further through other validation checks. Further, by
> > continuing even when record_size
On Thu, Jun 09, 2022 at 10:30:19PM -0300, Leonardo Bras Soares Passos wrote:
> Hello Daniel,
>
> On Thu, Jun 9, 2022 at 5:10 AM Daniel P. Berrangé wrote:
> >
> > On Wed, Jun 08, 2022 at 06:04:02PM -0300, Leonardo Bras wrote:
> > > During implementation of MSG_ZEROCOPY feature, a lot of #ifdefs
From: Volker Rümelin
The counterpart function for gd_gl_area_create_context() is
currently empty. Implement the gd_gl_area_destroy_context()
function to avoid GL context leaks.
Signed-off-by: Volker Rümelin
Message-Id: <20220605085131.7711-1-vr_q...@t-online.de>
Signed-off-by: Gerd Hoffmann
From: "Hongren (Zenithal) Zheng"
Signed-off-by: Hongren (Zenithal) Zheng
Message-Id:
Signed-off-by: Gerd Hoffmann
---
hw/usb/canokey.c| 13 +
hw/usb/trace-events | 16
2 files changed, 29 insertions(+)
diff --git a/hw/usb/canokey.c b/hw/usb/canokey.c
index
From: Arnout Engelen
The 'active' bit passes control over a qTD between the guest and the
controller: set to 1 by guest to enable execution by the controller,
and the controller sets it to '0' to hand back control to the guest.
ehci_state_writeback write two dwords to main memory using DMA:
the
From: Joelle van Dyne
When launching QEMU with "-loadvm", usbredir_create_parser() should avoid
setting up the hello packet (just as with "-incoming". On the latest version
of libusbredir, usbredirparser_unserialize() will return error if the parser
is not "pristine."
Signed-off-by: Joelle van
On Thu, 9 Jun 2022 at 21:29, Richard Henderson
wrote:
>
> This is mostly code movement at this point, out of headers
> and into op_helper.c and debug_helper.c.
>
> Changes for v3:
> * Drop helper_exception_advsimdfp_access.
> * Drop Rearrange Secure PL1 test in arm_debug_target_el.
> *
From: Igor Mammedov
Signed-off-by: Igor Mammedov
Acked-by: Gerd Hoffmann
Message-Id: <20220608135340.3304695-5-imamm...@redhat.com>
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsirkin
---
hw/char/parallel.c | 14 +-
1 file changed, 9 insertions(+), 5 deletions(-)
From: Igor Mammedov
basic q35 DSDT with an extra device node:
Device (MI1)
{
Name (_HID, EisaId ("IPI0001")) // _HID: Hardware ID
Name (_STR, "ipmi_smbus") // _STR: Description String
Name (_UID, One) // _UID: Unique ID
Name (_CRS, ResourceTemplate ()
From: Igor Mammedov
Signed-off-by: Igor Mammedov
Message-Id: <20220609114855.3477822-1-imamm...@redhat.com>
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsirkin
---
tests/qtest/bios-tables-test-allowed-diff.h | 32 +
1 file changed, 32 insertions(+)
diff
From: Igor Mammedov
replaces adhoc build_isa_devices_aml() with generic AcpiDevAmlIf
way to build bridge AML including all devices that are attached
to its ISA bus.
Later when PCI is converted to AcpiDevAmlIf, build_q35_isa_bridge()
will also be dropped since PCI parts itself will take care of
From: Igor Mammedov
smbus-ipmi AML description needs to specify a path to its parent
node in _CRS. The rest of IPMI inplementations (ISA based)
do not need path at all. Instead of passing through a full path
use relative path to point to smbus-ipmi's parent node, it will
let follow up patches to
From: Igor Mammedov
tpm-tis 2.0, is not a PCI device but ISA one, move it
under ISA scope to fix incorrect placement.
Fixes: 24cf5413aa0 (acpi: Make TPM 2.0 with TIS available as MSFT0101)
Signed-off-by: Igor Mammedov
Reviewed-by: Ani Sinha
Acked-by: Gerd Hoffmann
Message-Id:
From: Igor Mammedov
.. and clean up not longer needed conditionals in DSTD build code
tpm-tis AML will be fetched and included when ISA bridge will
build its own AML code (including attached devices).
Expected AML change:
the device under separate _SB.PCI0.ISA scope is moved directly
From: Mark Cave-Ayland
Perform the generation of the VIOT ACPI table in 2 separate passes: the first
pass
enumerates all of the PCI host bridges and adds the min_bus and max_bus
information
to an array.
Once this is done the VIOT table header is generated using the size of the array
to
From: Jonathan Cameron
Whilst here take the oportunity to shorten the function name.
Signed-off-by: Jonathan Cameron
Reviewed-by: Ben Widawsky
Message-Id: <20220608145440.26106-4-jonathan.came...@huawei.com>
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsirkin
---
From: "Hongren (Zenithal) Zheng"
This commit added a new emulated device called CanoKey to QEMU.
CanoKey implements platform independent features in canokey-core
https://github.com/canokeys/canokey-core, and leaves the USB implementation
to the platform.
In this commit the USB part was
On Thu, 9 Jun 2022 at 22:26, Hao Wu wrote:
>
> Hi,
>
> We did some experiments on this issue. It looks like the image size
> restriction is in firmware. So in qtest we can make it
> much smaller (e.g. 1MB) and the test still passes. We can send a patch with
> this change if necessary.
Yes,
From: Volker Rümelin
Since about 2018 virglrenderer (commit fa835b0f88 "vrend: don't
hardcode context version") tries to open the highest available GL
context version. This is done by creating the known GL context
versions from the highest to the lowest until (*create_gl_context)
returns a
From: Akihiko Odaki
The returned value is not used and misleading.
Signed-off-by: Akihiko Odaki
Message-Id: <20220226115516.59830-2-akihiko.od...@gmail.com>
Signed-off-by: Gerd Hoffmann
---
include/ui/console.h | 2 +-
hw/display/virtio-gpu-base.c | 6 +++---
hw/display/virtio-vga.c
Hi,
On Wednesday, June 8, 2022, Thomas Huth wrote:
> On 06/06/2022 18.43, Kashyap Chamarthy wrote:
>
>> This document is referred to from the GettingStartedDevelopers wiki
>> which will be rSTified in a follow-up commit.
>>
>> Converted from Mediawiki to rST using:
>>
>> $> pandoc -f
On 09/06/22 9:17 pm, Daniel P. Berrangé wrote:
On Thu, Jun 09, 2022 at 07:33:01AM +, Het Gala wrote:
As of now, the multi-FD feature supports connection over the default network
only. This Patchset series is a Qemu side implementation of providing multiple
interfaces support for multi-FD.
From: Igor Mammedov
Signed-off-by: Igor Mammedov
Acked-by: Gerd Hoffmann
Message-Id: <20220608135340.3304695-7-imamm...@redhat.com>
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsirkin
---
hw/rtc/mc146818rtc.c | 14 +-
1 file changed, 9 insertions(+), 5 deletions(-)
From: Igor Mammedov
Signed-off-by: Igor Mammedov
Acked-by: Gerd Hoffmann
Message-Id: <20220608135340.3304695-6-imamm...@redhat.com>
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsirkin
---
hw/char/serial-isa.c | 14 +-
1 file changed, 9 insertions(+), 5 deletions(-)
From: Igor Mammedov
Signed-off-by: Igor Mammedov
Acked-by: Gerd Hoffmann
Message-Id: <20220608135340.3304695-28-imamm...@redhat.com>
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsirkin
---
tests/qtest/bios-tables-test.c | 12
1 file changed, 12 insertions(+)
diff
From: Jonathan Cameron
Needed to allow memory address changes as a result of next patch.
Signed-off-by: Jonathan Cameron
Reviewed-by: Ben Widawsky
Message-Id: <20220608145440.26106-5-jonathan.came...@huawei.com>
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsirkin
---
From: Changpeng Liu
Currently vhost-user-scsi driver doesn't allow to change
the configuration space of virtio_scsi, while vhost-user-blk
support that, so here we set the flag in vhost-user-blk driver
and unset it in vhost-user-scsi.
Signed-off-by: Changpeng Liu
Message-Id:
From: Changpeng Liu
Variable `vdev` in `struct vhost_dev` will not be ready
until start the device, so let's not use it for the error
output here.
Fixes: 5653493 ("hw/virtio/vhost-user: don't suppress F_CONFIG when supported")
Signed-off-by: Changpeng Liu
Message-Id:
From: Jonathan Cameron
Without being able to write these registers, no interleaving is possible.
More refined checks of HDM register state on commit to follow.
Signed-off-by: Jonathan Cameron
Reviewed-by: Ben Widawsky
Message-Id: <20220608130804.25795-1-jonathan.came...@huawei.com>
-20220610-pull-request
for you to fetch changes up to 02319a4d67d3f19039127b8dc9ca9478b6d6ccd8:
virtio-gpu: Respect UI refresh rate for EDID (2022-06-10 11:11:44 +0200)
usb: add CanoKey device, fixes for ehci + redir
ui: fixes for gtk
From: "Hongren (Zenithal) Zheng"
Signed-off-by: Hongren (Zenithal) Zheng
Message-Id:
Signed-off-by: Gerd Hoffmann
---
docs/system/devices/usb.rst | 4
1 file changed, 4 insertions(+)
diff --git a/docs/system/devices/usb.rst b/docs/system/devices/usb.rst
index afb7d6c2268d..872d9167589b
From: Daniel P. Berrangé
The 'keymaps' directory contents is nothing to do with the firmware
blobs. The 'pc-bios/keymaps' directory appears to have been used
previously as a convenience for getting the files installed into
a subdir of the firmware install dir. This install time arrangement
does
On 6/10/22 04:01, Liu Jaloo wrote:
Dear Paul Brook:
in qemu/tcg/README:
"
...
QOP code generator written by Paul Brook.
...
"
Is there some text about QOP? or basically what QOP stands for?
I can't find out anything about QOP from Google. thanks.
On Fri, Jun 10, 2022 at 01:48:57PM +0530, Ani Sinha wrote:
> On Thu, May 19, 2022 at 6:35 PM Eric DeVolder
> wrote:
> >
> >
> >
> > On 5/13/22 09:10, Ani Sinha wrote:
> > > At any step when any validation fail in check_erst_backend_storage(),
> > > there is
> > > no need to continue further
From: Igor Mammedov
expected new device node:
Device (MI1)
{
Name (_HID, EisaId ("IPI0001")) // _HID: Hardware ID
Name (_STR, "ipmi_smbus") // _STR: Description String
Name (_UID, One) // _UID: Unique ID
Name (_CRS, ResourceTemplate () // _CRS:
From: Jonathan Cameron
Paolo Bonzini requested this change to simplify the ongoing
effort to allow machine setup entirely via RPC.
Includes shortening the command line form cxl-fixed-memory-window
to cxl-fmw as the command lines are extremely long even with this
change.
The json change is
From: Igor Mammedov
Signed-off-by: Igor Mammedov
Message-Id: <20220608135340.3304695-23-imamm...@redhat.com>
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsirkin
---
tests/qtest/bios-tables-test-allowed-diff.h | 1 +
tests/data/acpi/q35/DSDT.applesmc | 0
2 files
From: Igor Mammedov
Expected AML change:
ISA devices under separate _SB.PCI0.ISA scope are moved
directly under Device(ISA) node.
Example from PC machine, and q35 have similar changes:
{
Name (_ADR, 0x0001) // _ADR: Address
OperationRegion (P40C,
From: Igor Mammedov
.. and clean up not longer needed conditionals in DSTD build code
pvpanic-isa AML will be fetched and included when ISA bridge will
build its own AML code (including attached devices).
Expected AML change:
the device under separate _SB.PCI0.ISA scope is moved directly
From: Mark Cave-Ayland
Differences between disassembled ASL files for VIOT:
+++ /tmp/asl-V69GM1.dsl 2022-05-18 10:22:27.239796759 +0100
@@ -36,11 +36,11 @@
[041h 0065 1] Reserved : 00
[042h 0066 2] Length : 0018
-[044h 0068 4]
From: zhenwei pi
There are two parts in this patch:
1, support akcipher service by cryptodev-builtin driver
2, virtio-crypto driver supports akcipher service
In principle, we should separate this into two patches, to avoid
compiling error, merge them into one.
Then virtio-crypto gets request
On Thu, 9 Jun 2022 at 23:58, Richard Henderson
wrote:
>
> On 6/9/22 08:35, Peter Maydell wrote:
> >> +if (!disas_sme(s, insn)) {
> >> +unallocated_encoding(s);
> >> +}
> >> +break;
> >
> > I still think we should check bit 31 here.
>
> We don't do anything
From: Bernhard Beschow
The tables contain spcifically crafted constants for algorithms, so make
them immutable.
Signed-off-by: Bernhard Beschow
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20220520180109.8224-3-shen...@gmail.com>
Signed-off-by: Gerd Hoffmann
---
hw/audio/cs4231a.c | 8
From: Dongwon Kim
It only needs to update the scanouts containing the rect area
coming with the resource-flush request from the guest.
Cc: Gerd Hoffmann
Cc: Vivek Kasireddy
Signed-off-by: Dongwon Kim
Message-Id: <20220505214030.4261-1-dongwon@intel.com>
Signed-off-by: Gerd Hoffmann
---
From: Igor Mammedov
.. and clean up not longer needed conditionals in DSTD build
code. applesmc AML will be fetched and included when ISA bridge
will build its own AML code (incl. attached devices).
Expected AML change:
the device under separate _SB.PCI0.ISA scope is moved directly
under
From: Igor Mammedov
replaces ad-hoc build_isa_devices_aml() with generic AcpiDevAmlIf
way to build bridge AML including all devices that are attached to
its ISA bus.
Later when PCI is converted to AcpiDevAmlIf, build_piix4_isa_bridge()
will also be dropped since PCI parts itself will take care
From: Igor Mammedov
@@ -145,6 +145,23 @@ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC",
0x0001)
{
Name (_ADR, 0x001F) // _ADR: Address
OperationRegion (PIRQ, PCI_Config, 0x60, 0x0C)
+Device (SMC)
+{
+Name
From: Igor Mammedov
Signed-off-by: Igor Mammedov
Message-Id: <20220608135340.3304695-27-imamm...@redhat.com>
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsirkin
---
tests/qtest/bios-tables-test-allowed-diff.h | 1 +
tests/data/acpi/q35/DSDT.pvpanic-isa| 0
2 files
From: Jonathan Cameron
As all the CXL elements have moved to boards that support
CXL, there is no need to maintain a top level flag.
Signed-off-by: Jonathan Cameron
Reviewed-by: Ben Widawsky
Message-Id: <20220608145440.26106-9-jonathan.came...@huawei.com>
Reviewed-by: Michael S. Tsirkin
From: Igor Mammedov
Signed-off-by: Igor Mammedov
Acked-by: Ani Sinha
Message-Id: <20220608135340.3304695-31-imamm...@redhat.com>
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsirkin
---
tests/qtest/bios-tables-test-allowed-diff.h | 2 ++
1 file changed, 2 insertions(+)
diff
From: Igor Mammedov
the last remaining dependency on ISA in acpi-build.c
is iapc_boot_arch_8042() which pulls in in isa.h
in its own header hw/input/i8042.h. Clean up
not longer needed direct inclusion of isa.h in
acpi-build.c
Signed-off-by: Igor Mammedov
Acked-by: Gerd Hoffmann
Message-Id:
From: "Hongren (Zenithal) Zheng"
Signed-off-by: Hongren (Zenithal) Zheng
Message-Id:
Signed-off-by: Gerd Hoffmann
---
meson_options.txt | 2 ++
hw/usb/Kconfig| 5 +
hw/usb/meson.build| 5 +
meson.build | 6 ++
From: Akihiko Odaki
This change adds a new member, refresh_rate to QemuUIInfo in
include/ui/console.h. It represents the refresh rate of the
physical display backend, and it is more appropriate than
GUI update interval as the refresh rate which the emulated device
reports:
- sdl may set GUI
From: Igor Mammedov
There is already ISADeviceClass::build_aml() callback which
builds device specific AML blob for some ISA devices.
To extend the same idea to other devices, add TYPE_ACPI_DEV_AML_IF
Interface that will provide a more generic callback which
will be used not only for ISA but
From: Igor Mammedov
To allow incremental conversion from ISADeviceClass::build_aml
to AcpiDevAmlIf, add support for the later without removing
the former. Once conversion is complete, another commit will
drop ISADeviceClass::build_aml related code.
Signed-off-by: Igor Mammedov
Reviewed-by: Ani
The following changes since commit 6d940eff4734bcb40b1a25f62d7cec5a396f994a:
Merge tag 'pull-tpm-2022-06-07-1' of https://github.com/stefanberger/qemu-tpm
into staging (2022-06-07 19:22:18 -0700)
are available in the Git repository at:
git://git.kernel.org/pub/scm/virt/kvm/mst/qemu.git
From: Igor Mammedov
Signed-off-by: Igor Mammedov
Acked-by: Gerd Hoffmann
Message-Id: <20220608135340.3304695-4-imamm...@redhat.com>
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsirkin
---
hw/block/fdc-isa.c | 16 ++--
hw/i386/acpi-build.c | 1 -
2 files changed,
From: Igor Mammedov
by default we do not version ACPI AML as it's considered
a part of firmware. Drop do_not_add_smb_acpi that blocked
SMBUS AML description on 3.1 and older machine types without
providing justification.
Signed-off-by: Igor Mammedov
Acked-by: Gerd Hoffmann
Message-Id:
From: Igor Mammedov
convert ad-hoc way we use to generate AML for ISA/SMB IPMI devices
to a generic approach (i.e. make devices provide its own AML blobs
like it is done with other ISA devices (ex. KBD))
Signed-off-by: Igor Mammedov
Acked-by: Gerd Hoffmann
Message-Id:
From: Igor Mammedov
expected move of tmp-tis device description directly under
Device(ISA) node.
for tpm-tis 2.0:
@@ -145,6 +145,189 @@ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC",
0x0001)
{
Name (_ADR, 0x001F) // _ADR: Address
From: Igor Mammedov
Signed-off-by: Igor Mammedov
Acked-by: Gerd Hoffmann
Message-Id: <20220608135340.3304695-24-imamm...@redhat.com>
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsirkin
---
tests/qtest/bios-tables-test.c | 12
1 file changed, 12 insertions(+)
diff
From: Mark Cave-Ayland
Signed-off-by: Mark Cave-Ayland
Acked-by: Ani Sinha
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20220525173232.31429-5-mark.cave-ayl...@ilande.co.uk>
Reviewed-by: Jean-Philippe Brucker
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsirkin
---
From: Claudio Fontana
the code in pcibus_get_fw_dev_path contained the potential for a
stack buffer overflow of 1 byte, potentially writing to the stack an
extra NUL byte.
This overflow could happen if the PCI slot is >= 0x1000,
and the PCI function is >= 0x1000, due to the size
From: "Hongren (Zenithal) Zheng"
Signed-off-by: Hongren (Zenithal) Zheng
Message-Id:
Signed-off-by: Gerd Hoffmann
---
MAINTAINERS | 8
1 file changed, 8 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 5580a36b68e1..4ae9d707d5b0 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
On Thu, 9 Jun 2022 at 22:52, Richard Henderson
wrote:
>
> Adjust RW, fixing #1062, and adjusting bits [4:2].
>
> Changes for v2:
> * Fix patch 1 vs reset.
>
Applied to target-arm.next, thanks. (Fixed a missing space
at end of comment in patch 2.)
-- PMM
in the Git repository at:
g...@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20220610
for you to fetch changes up to 07314158f6aa4d2589520c194a7531b9364a8d54:
target/riscv: trans_rvv: Avoid assert for RV32 and e64 (2022-06-10 09:42:12
+1000
On 9/6/22 23:41, Hao Wu wrote:
Creating 1GB image for a simple qtest is unnecessary
and could lead to failures. We reduce the image size
to 1MB to reduce the test overhead.
Signed-off-by: Hao Wu
---
tests/qtest/npcm7xx_sdhci-test.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Hi Pavel,
On 9/6/22 10:23, Pavel Dovgalyuk wrote:
This patch adds Cavium Octeon vCPU for providing
Octeon-specific instructions.
Signed-off-by: Pavel Dovgalyuk
--
v2 changes:
- vCPU name changed to Octeon68XX (suggested by Richard Henderson)
---
target/mips/cpu-defs.c.inc | 28
On Thu, Jun 09, 2022 at 05:02:29PM -0400, Peter Xu wrote:
> On Wed, Jun 08, 2022 at 06:05:28PM +0100, Dr. David Alan Gilbert wrote:
> > > @@ -2005,7 +2005,17 @@ static void loadvm_postcopy_handle_run_bh(void
> > > *opaque)
> > > /* TODO we should move all of this lot into postcopy_ram.c or a
While forcing the CPU to unrealize by hand does trigger the clean-up
code we never fully free resources because refcount never reaches
zero. This is because QOM automatically added objects without an
explicit parent to /unattached/, incrementing the refcount.
Instead of manually triggering
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