On 6/26/22 23:14, Mark Cave-Ayland wrote:
The following changes since commit 40d522490714b65e0856444277db6c14c5cc3796:
Merge tag 'for-upstream' of git://repo.or.cz/qemu/kevin into staging
(2022-06-24 10:52:46 -0700)
are available in the Git repository at:
This should fix the last caller causing a NULL ISADev to be passed to
isa_register_portio_list() which now allows for disusing the isabus global
there.
Signed-off-by: Bernhard Beschow
---
hw/ide/piix.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/ide/piix.c
These are some basic changes required in meson.build file in order to
incorporate python based qtests later on. No new qtests have been added in this
change.
Signed-off-by: Ani Sinha
---
tests/qtest/meson.build | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git
This is initial commit of cpuid, acpi and smbios python test scripts for
biosbits to execute. No change has been made to them from the original code
written by the biosbits author Josh Triplett. They are required to be installed
into the bits iso file and then run from within the virtual machine
smilatency tests does not reliably pass every time it is run from QEMU. This
change adds the test file unchanged from bits so that the next change can
disable the test.
Signed-off-by: Ani Sinha
---
tests/qtest/acpi-bits/bits-tests/meson.build | 2 +-
On 13:45 Tue 07 Jun , Richard Henderson wrote:
> Add a GuestFDType for connecting to the semihosting console.
> Hook up to read, write, isatty, and fstat syscalls.
>
> Note that the arm-specific syscall flen cannot be applied
> to the console, because the console is not a descriptor
> exposed
Coverity pointed out (CID 1490222, 1490227) that we called
ioctl somewhere without checking the return value. This
patch fixes these issues.
Fixes: Coverity CID 1490222, 1490227
Signed-off-by: Xie Yongji
---
subprojects/libvduse/libvduse.c | 10 --
1 file changed, 8 insertions(+), 2
On 08:05 Wed 22 Jun , Richard Henderson wrote:
> On 6/22/22 02:35, Luc Michel wrote:
> > On 13:45 Tue 07 Jun , Richard Henderson wrote:
> > > Split out the non-ARM specific portions of SYS_OPEN to a
> > > reusable function. This handles gdb and host file i/o.
> > >
> > > Add helpers to
From: Richard Henderson
This register is part of SME, but isn't closely related to the
rest of the extension.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20220620175235.60881-2-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/cpu.h| 1
From: Alexander Graf
We need to fetch the name of the current accelerator in flexible error
messages more going forward. Let's create a helper that gives it to us
without casting in the target code.
Signed-off-by: Alexander Graf
Reviewed-by: Richard Henderson
Message-id:
From: Martin Liška
Fixes the following Sphinx warning (treated as error) starting
with 5.0 release:
Warning, treated as error:
Invalid configuration value found: 'language = None'. Update your configuration
to a valid langauge code. Falling back to 'en' (English).
Signed-off-by: Martin Liska
From: Richard Henderson
This cpreg is used to access two new bits of PSTATE
that are not visible via any other mechanism.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20220620175235.60881-6-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
From: Alexander Graf
Some features such as running in EL3 or running M profile code are
incompatible with virtualization as QEMU implements it today. To prevent
users from picking invalid configurations on other virt solutions like
Hvf, let's run the same checks there too.
Resolves:
On Mon, Jun 27, 2022 at 12:14 PM Ani Sinha wrote:
>
> Biosbits is a software written by Josh Triplett that can be downloaded by
> visiting https://biosbits.org/. The github codebase can be found here:
> https://github.com/biosbits/bits/tree/master. It is a software that exercizes
> the bios
Biosbits is a software written by Josh Triplett that can be downloaded by
visiting https://biosbits.org/. The github codebase can be found here:
https://github.com/biosbits/bits/tree/master. It is a software that exercizes
the bios components such as acpi and smbios tables directly through acpica
On Mon, Jun 27, 2022 at 12:22 PM Ani Sinha wrote:
>
> On Mon, Jun 27, 2022 at 12:14 PM Ani Sinha wrote:
> >
> > Biosbits is a software written by Josh Triplett that can be downloaded by
> > visiting https://biosbits.org/. The github codebase can be found here:
> >
This change adds initial biosbits config file that instructs biosbits to run
bios test suits in batch mode. Additionally acpi and smbios structures are also
dumped.
Signed-off-by: Ani Sinha
---
tests/qtest/acpi-bits/bits-config/bits-cfg.txt | 18 ++
On 13:45 Tue 07 Jun , Richard Henderson wrote:
> Will replace qemu_semihosting_console_{outs,outc},
> but we need more plumbing first.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Luc Michel
> ---
> include/semihosting/console.h | 12
> linux-user/semihost.c |
PSS tests in acpi test suite seems to be failing in biosbits. This is because
the test is unable to find PSS support in QEMU bios. Let us disable
them for now so that make check does not fail. We can fix the tests and
re-enable them later.
Example failure:
ACPI _PSS (Pstate) table
On 6/27/22 02:19, Sam Li wrote:
---
block/file-posix.c | 60
include/block/block-common.h | 4 +--
2 files changed, 62 insertions(+), 2 deletions(-)
diff --git a/block/file-posix.c b/block/file-posix.c
index 73c2cdfbca..74c0245e0f 100644
---
On 13:45 Tue 07 Jun , Richard Henderson wrote:
> For arm-compat, initialize console_{in,out}_gf;
> otherwise, initialize stdio file descriptors.
>
> This will go some way to cleaning up arm-compat, and
> will allow other semihosting to use normal stdio.
>
> Signed-off-by: Richard Henderson
While the HMAC mode is not modelled, the accumulative mode is.
Accumulative mode is enabled by setting one of the bits in the HMAC
engine command mode part of the register, so fix the unimplemented check
to only look at the upper of the two bits.
Fixes: 5cd7d8564a8b ("aspeed/hace: Support
From: Richard Henderson
We need SVL separate from VL for RDSVL et al, as well as
ZA storage loads and stores, which do not require PSTATE.SM.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20220620175235.60881-20-richard.hender...@linaro.org
Signed-off-by: Peter
From: Richard Henderson
When Streaming SVE mode is enabled, the size is taken from
SMCR_ELx instead of ZCR_ELx. The format is shared, but the
set of vector lengths is not. Further, Streaming SVE does
not require any particular length to be supported.
Adjust sve_vqm1_for_el to pass the current
Hello there,
considering that Linux v5.19 will include support for NVMe TP4084:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/nvme/host/core.c?id=354201c53e61e493017b15327294b0c8ab522d69
I thought that it might be nice to have QEMU support for the same.
On 6/27/22 16:10, Marc-André Lureau wrote:
Could you describe how to reproduce? I naively --disable-virglrenderer and I
get:
$ tests/venv/bin/avocado run tests/avocado/virtio-gpu.py
Fetching asset from
tests/avocado/virtio-gpu.py:VirtioGPUx86.test_virtio_vga_virgl
Fetching asset from
On 27/06/2022 07:40, Alistair Francis wrote:
We have previously kept the addresses backwards compatible. So that
software for an older virt machine will work on a newer one. There is
currently talks about changing the virt machine memory layout in a
breaking way and versioning in the current one
Actually, I have gotten the QEMU disassembler to run with some short
customization. But I am having trouble understanding the output. I see lots
of lines like this:
|
OBJD-H: 06040102a83507000cd8027620272573004c04cd20c100782244038c
On Sun, Jun 26, 2022 at 11:00 PM Kenneth Adam Miller <
The README file is added describing the directory structure and the purpose
of every file it contains. It also describes how to add new tests, make changes
to existing tests or bits config files or regenerate the bits software.
Signed-off-by: Ani Sinha
---
tests/qtest/acpi-bits/README | 168
I wrote the biosbits test framework, the qtest for testing QEMU with biosbits
and all the related changes. Making myself as the maintainer for biosbits
related files and test scripts.
Signed-off-by: Ani Sinha
---
MAINTAINERS | 5 +
1 file changed, 5 insertions(+)
diff --git a/MAINTAINERS
Hannes Reinecke 于2022年6月27日周一 15:30写道：
>
> On 6/27/22 02:19, Sam Li wrote:
> > ---
>
> Good coding style would advise to add some text here what the patch does.
>
> > block/io.c | 21 +++
> > include/block/block-io.h | 13 +
> > qemu-io-cmds.c | 121
Hannes Reinecke 于2022年6月27日周一 15:31写道：
>
> On 6/27/22 02:19, Sam Li wrote:
> > Use sysfs attribute files to get the zoned device information in case
> > that ioctl() commands of zone management interface won't work. It can
> > return long type of value like chunk_sectors, zoned_append_max_bytes,
mhartid csr is not available in user-mode code path and
user-mode build fails because of its reference in
riscv_cpu_realize function
Signed-off-by: Rahul Pathak
---
target/riscv/cpu.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index
From: Richard Henderson
These are required to determine if various insns
are allowed to issue.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20220620175235.60881-9-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/cpu.h | 2 ++
Hi
On Mon, Jun 27, 2022 at 7:14 AM Richard Henderson <
richard.hender...@linaro.org> wrote:
> Hi Mark,
>
> > +def test_virtio_vga_virgl(self):
>
> > +"""
>
> > +:avocado: tags=arch:x86_64
>
> > +:avocado: tags=device:virtio-vga
>
> > +"""
>
> > +
Add property "ioeventfd" which is enabled by default. When this is
enabled, updates on the doorbell registers will cause KVM to signal
an event to the QEMU main loop to handle the doorbell updates.
Therefore, instead of letting the vcpu thread run both guest VM and
IO emulation, we now use the
From: Richard Henderson
Pull the three sve_vq_* values into a structure.
This will be reused for SME.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20220620175235.60881-13-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/cpu.h| 29
From: Richard Henderson
Rename from cpu_arm_{get,set}_sve_vq, and take the
ARMVQMap as the opaque parameter.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20220620175235.60881-14-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/cpu64.c | 29
Victor Toso writes:
> Hi,
>
> This is the second iteration of RFC v1:
> https://lists.gnu.org/archive/html/qemu-devel/2022-04/msg00226.html
>
>
> # What this is about?
>
> To generate a simple Golang interface that could communicate with QEMU
> over QMP. The Go code that is generated is meant
Now that the PIIX IDE device models check for presence of an ISABus before
using it, this fix isn't needed any longer.
This reverts commit 9405d87be25db6dff4d7b5ab48a81bbf6d083e47.
Signed-off-by: Bernhard Beschow
---
hw/ide/ioport.c | 16 ++--
hw/ide/piix.c |
This change adds python based qtest framework that can be used to run
qtests from within a virtual environment. A bash script creates the virtual
environment and then runs the python based tests from within that environment.
All dependent python packages are installed in the virtual environment
In vduse_name_is_valid(), we actually check whether
the name is invalid or not. So let's change the
function name to vduse_name_is_invalid() to match
the behavior.
Signed-off-by: Xie Yongji
---
subprojects/libvduse/libvduse.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff
Richard Henderson writes:
> For arm-compat, initialize console_{in,out}_gf;
> otherwise, initialize stdio file descriptors.
>
> This will go some way to cleaning up arm-compat, and
> will allow other semihosting to use normal stdio.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Alex
On 13:45 Tue 07 Jun , Richard Henderson wrote:
> This will be used for implementing the xtensa select_one
> system call. Choose "poll" over "select" so that we can
> reuse Glib's g_poll constants and to avoid struct timeval.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Luc Michel
>
Richard Henderson writes:
> This function has been replaced by *_write.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Alex Bennée
--
Alex Bennée
On 6/24/22 20:30, Iris Chen wrote:
Signed-off-by: Iris Chen
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
Adding Signed Off By tag -- sorry I missed that !
tests/qtest/aspeed_smc-test.c | 62 +++
1 file changed, 62 insertions(+)
diff --git
' of https://github.com/mcayland/qemu into
staging (2022-06-27 05:21:05 +0530)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20220627
for you to fetch changes up to 59e1b8a22ea9f947d038ccac784de1020f266e14:
target/arm: Check
From: Richard Henderson
This is CheckSMEAccess, which is the basis for a set of
related tests for various SME cpregs and instructions.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20220620175235.60881-3-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
From: Richard Henderson
Implement the streaming mode identification register, and the
two streaming priority registers. For QEMU, they are all RES0.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20220620175235.60881-8-richard.hender...@linaro.org
Signed-off-by:
From: Richard Henderson
Rename from cpu_arm_{get,set}_sve_default_vec_len,
and take the pointer to default_vq from opaque.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20220620175235.60881-15-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
From: Richard Henderson
This will be used for raising various traps for SME.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20220620175235.60881-4-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/syndrome.h | 14 ++
1 file
These are some basic changes required in meson.build file in order to
incorporate python based qtests later on. No new qtests have been added in this
change.
Signed-off-by: Ani Sinha
---
tests/qtest/meson.build | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git
On Tue, Jun 7, 2022 at 11:21 PM Alistair Francis
wrote:
>
> From: Alistair Francis
>
> We previously stored the device tree at a 16MB alignment from the end of
> memory (or 3GB). This means we need at least 16MB of memory to be able
> to do this. We don't actually need the FDT to be 16MB
Now that all call sites of these functions are fixed to pass non-NULL
ISADevices, the ISABus can be determined from the ISADevice argument.
Patch based on https://lists.nongnu.org/archive/html/qemu-devel/2021-05/
msg05785.html.
Signed-off-by: Bernhard Beschow
---
hw/ide/ioport.c | 4 ++--
Now that only isa_bus_new() accesses the isabus global it can be removed
assuming that all call sites take care of not passing the same address
spaces twice to different isa_bus_new() invocations.
Signed-off-by: Bernhard Beschow
---
hw/isa/isa-bus.c | 8 ++--
1 file changed, 2
added acpi-bits subdirectory in meson.build so that the tests in that
subdirectory can be run as a part of make check.
Signed-off-by: Ani Sinha
---
tests/qtest/acpi-bits/acpi-bits-test.py | 4 ++--
tests/qtest/meson.build | 2 ++
2 files changed, 4 insertions(+), 2 deletions(-)
On 13:45 Tue 07 Jun , Richard Henderson wrote:
> Signed-off-by: Richard Henderson
Reviewed-by: Luc Michel
> ---
> semihosting/arm-compat-semi.c | 11 +--
> 1 file changed, 9 insertions(+), 2 deletions(-)
>
> diff --git a/semihosting/arm-compat-semi.c
Richard Henderson writes:
> Move the ARM and RISCV specific helpers into
> their own header file.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Alex Bennée
> ---
> target/arm/common-semi-target.h | 62
> target/riscv/common-semi-target.h | 50
>
Richard Henderson writes:
> Signed-off-by: Richard Henderson
> ---
> semihosting/arm-compat-semi.c | 27 ++-
> 1 file changed, 18 insertions(+), 9 deletions(-)
>
> diff --git a/semihosting/arm-compat-semi.c b/semihosting/arm-compat-semi.c
> index
From: Richard Henderson
These two instructions are aliases of MSR (immediate).
Use the two helpers to properly implement svcr_write.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20220620175235.60881-11-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
From: Richard Henderson
Place this late in the resettable section of the structure,
to keep the most common element offsets from being > 64k.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20220620175235.60881-10-richard.hender...@linaro.org
[PMM: expanded comment on
* Daniel P. Berrangé (berra...@redhat.com) wrote:
> This directly implements the get_buffer logic using QIOChannel APIs.
>
> Reviewed-by: Dr. David Alan Gilbert
> Signed-off-by: Daniel P. Berrangé
Coverity is pointing out a fun deadcode path from this:
> diff --git a/migration/qemu-file.c
On 6/27/22 02:19, Sam Li wrote:
---
Good coding style would advise to add some text here what the patch does.
block/io.c | 21 +++
include/block/block-io.h | 13 +
qemu-io-cmds.c | 121 +++
3 files changed, 155
smilatency test is latency sensitive and does not pass deterministically when
run in QEMU environment under biosbits. Disable the test suite for now.
Example failure:
SMI latency test
Warning: touching the keyboard can affect the results of this test.
Starting test. Wait here, I will
On Mon, Jun 27, 2022 at 12:25 PM Ani Sinha wrote:
>
> On Mon, Jun 27, 2022 at 12:22 PM Ani Sinha wrote:
> >
> > On Mon, Jun 27, 2022 at 12:14 PM Ani Sinha wrote:
> > >
> > > Biosbits is a software written by Josh Triplett that can be downloaded by
> > > visiting https://biosbits.org/. The
On Mon, Jun 27, 2022 at 12:45 PM Markus Armbruster wrote:
>
> Kevin Wolf writes:
>
> > From: Xie Yongji
> >
> > VDUSE [1] is a linux framework that makes it possible to implement
> > software-emulated vDPA devices in userspace. This adds a library
> > as a subproject to help implementing VDUSE
On 26/06/2022 10:46, Bernhard Beschow wrote:
The only user of xen_set_pci_link_route() is
xen_piix_pci_write_config_client() which implements PIIX-specific logic in
the xen namespace. This makes xen-hvm depend on PIIX which could be
avoided if xen_piix_pci_write_config_client() was implemented
Richard Henderson writes:
> Moving this to be useful for another function
> besides do_common_semihosting.
>
> Reviewed-by: Peter Maydell
> Signed-off-by: Richard Henderson
Reviewed-by: Alex Bennée
--
Alex Bennée
Richard Henderson writes:
> Add a GuestFDType for connecting to the semihosting console.
> Hook up to read, write, isatty, and fstat syscalls.
>
> Note that the arm-specific syscall flen cannot be applied
> to the console, because the console is not a descriptor
> exposed to the guest.
>
>
From: Richard Henderson
This will be used for controlling access to SME cpregs.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20220620175235.60881-5-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/cpregs.h| 5 +
From: Richard Henderson
These cpregs control the streaming vector length and whether the
full a64 instruction set is allowed while in streaming mode.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20220620175235.60881-7-richard.hender...@linaro.org
Signed-off-by:
From: Richard Henderson
Keep all of the error messages together. This does mean that
when setting many sve length properties we'll only generate
one error, but we only really need one.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id:
From: Richard Henderson
In machvirt_init we create a cpu but do not fully initialize it.
Thus the propagation of V7VE to LPAE has not been done, and we
compute the wrong value for some v7 cpus, e.g. cortex-a15.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1078
Signed-off-by: Richard
On 6/27/22 12:10, Kenneth Adam Miller wrote:
Actually, I have gotten the QEMU disassembler to run with some short customization. But I
am having trouble understanding the output. I see lots of lines like this:
|
OBJD-H: 06040102a83507000cd8027620272573004c04cd20c100782244038c
You want
On 6/18/2022 12:51 AM, Alex Williamson wrote:
External email: Use caution opening links or attachments
On Mon, 13 Jun 2022 14:21:26 +0300
Avihai Horon wrote:
On 6/8/2022 12:32 AM, Alex Williamson wrote:
External email: Use caution opening links or attachments
On Tue, 7 Jun 2022
On 6/27/22 02:19, Sam Li wrote:
Use sysfs attribute files to get the zoned device information in case
that ioctl() commands of zone management interface won't work. It can
return long type of value like chunk_sectors, zoned_append_max_bytes,
max_open_zones, max_active_zones.
---
On Mon, Jun 27, 2022 at 7:20 AM Alistair Francis
wrote:
> On Fri, Jun 24, 2022 at 1:31 AM Christoph Muellner
> wrote:
> >
> > This patch adds support for the Zawrs ISA extension.
> > Given the current (incomplete) implementation of reservation sets
> > there seems to be no way to provide a full
On 13:45 Tue 07 Jun , Richard Henderson wrote:
> This function has been replaced by *_write.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Luc Michel
> ---
> include/semihosting/console.h | 13 --
> linux-user/semihost.c | 17
> semihosting/console.c
Hannes Reinecke 于2022年6月27日周一 15:41写道：
>
> On 6/27/22 02:19, Sam Li wrote:
> > ---
> > block/file-posix.c | 60
> > include/block/block-common.h | 4 +--
> > 2 files changed, 62 insertions(+), 2 deletions(-)
> >
> > diff --git
On 13:45 Tue 07 Jun , Richard Henderson wrote:
> This function has been replaced by *_write.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Luc Michel
> ---
> include/semihosting/console.h | 13 -
> linux-user/semihost.c | 16
>
On 26/06/2022 10:46, Bernhard Beschow wrote:
xen_piix_pci_write_config_client() is implemented in the xen sub tree and
uses PIIX constants internally, thus creating a direct dependency on
PIIX. Now that xen_set_pci_link_route() is stubbable, the logic of
xen_piix_pci_write_config_client() can be
On 24/06/2022 10.50, Thomas Huth wrote:
The s390-ccw bios fails to boot if the boot disk is a virtio-blk
disk with a sector size of 4096. For example:
dasdfmt -b 4096 -d cdl -y -p -M quick /dev/dasdX
fdasd -a /dev/dasdX
install a guest onto /dev/dasdX1 using virtio-blk
qemu-system-s390x
From: Richard Henderson
Move the code from hw/arm/virt.c that is supposed
to handle v7 into the one function.
Signed-off-by: Richard Henderson
Reported-by: He Zhe
Message-id: 20220619001541.131672-2-richard.hender...@linaro.org
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
The next patch will introduce a quirk for user-created PIIX IDE devices for
backwards compatibility. In order to opt-in to new behavior for builtin
devices a property will need to be set until a deprecation period is over.
Signed-off-by: Bernhard Beschow
---
hw/i386/pc_piix.c | 3 ++-
1 file
Now that all call-sites have been fixed to pass non-NULL ISADevices, we can
assert() on NULL ISADevices to catch regressions.
Signed-off-by: Bernhard Beschow
---
hw/isa/isa-bus.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/hw/isa/isa-bus.c b/hw/isa/isa-bus.c
index
On 6/27/22 02:19, Sam Li wrote:
By adding zone management operations in BlockDriver, storage
controller emulation can use the new block layer APIs including
zone_report and zone_mgmt(open, close, finish, reset).
---
block/block-backend.c| 56
block/coroutines.h
pci_ide_init_ioport() and pci_register_portio_list() are introduced which
mirror their ISA counterparts. But rather than asking for an ISADevice, the
functions ask for PCIDevice which can be used in hw/ide/piix which fixes
having to pass a NULL ISADevice which is not avialable there.
Passing NULL
Hi Hannes,
Hannes Reinecke 于2022年6月27日周一 15:21写道：
>
> On 6/27/22 02:19, Sam Li wrote:
> > By adding zone management operations in BlockDriver, storage
> > controller emulation can use the new block layer APIs including
> > zone_report and zone_mgmt(open, close, finish, reset).
> > ---
> >
On 13:45 Tue 07 Jun , Richard Henderson wrote:
> Signed-off-by: Richard Henderson
Reviewed-by: Luc Michel
> ---
> semihosting/arm-compat-semi.c | 27 ++-
> 1 file changed, 18 insertions(+), 9 deletions(-)
>
> diff --git a/semihosting/arm-compat-semi.c
On 13:45 Tue 07 Jun , Richard Henderson wrote:
> Signed-off-by: Richard Henderson
Reviewed-by: Luc Michel
> ---
> semihosting/arm-compat-semi.c | 20
> 1 file changed, 16 insertions(+), 4 deletions(-)
>
> diff --git a/semihosting/arm-compat-semi.c
From: Richard Henderson
Drop the aa32-only inline fallbacks,
and just use a couple of ifdefs.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
Message-id: 20220620175235.60881-16-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/cpu.h | 6 --
Since we verify that "ready_delay" parameter has to be smaller than CRWMT,
we know that the namespace will always become ready.
Therefore the "Namespace Not Ready" status code will never have the DNR
bit set.
Add a new parameter "never_ready" that can be used to emulate a namespace
that never
TP4084 adds a new mode, CC.CRIME, that can be used to mark a namespace
as ready independently from the controller.
When CC.CRIME is 0 (default), things behave as before, all namespaces
are ready when CSTS.RDY gets set to 1.
When CC.CRIME is 1, the controller will become ready when CSTS.RDY gets
On Jun 16 20:34, Jinhao Fan wrote:
> This patch adds shadow doorbell buffer support in NVMe 1.3 to QEMU
> NVMe. The Doorbell Buffer Config admin command is implemented for the
> guest to enable shadow doobell buffer. When this feature is enabled, each
> SQ/CQ is associated with two buffers, i.e.,
Inverse the condition checking to PG_PRESENT_MASK when walk LA57
guest's pdpe/pde for "info mem" command.
The current condition checking:
if (PG_PRESENT_MASK is set)
Skip low level page table.
else
Try to walk low level page table.
This is wrong because PG_PRESENT_MASK is set means the
This series resolves the global "isabus" variable and is basically a v2 of [1].
Note that the majority of the work consists of fixing ISA API calls in PIIX IDE
which implicitly rely on the usage of the isabus global.
Rather than adding an ISABus pointer in PCIIDEState as in "v1" this series uses
isa_get_irq() currently always uses the "isabus" global to get the
desired qemu_irq. In order to resolve this global, we want
isa_get_irq() to determine the ISABus from its *dev parameter using
isa_bus_from_device(). As a preparation, all callers who pass NULL
as *dev need to be resolved which
ide_init_ioport() takes an ISADevice* parameter which eventually gets passed
to isa_address_space_io(). Unfortunately, there is no ISADevice in hw/ide/
piix, so NULL gets passed instead. This causes isa_address_space_io() to
resort to using the isabus global - which we want to get rid of.
To
This is an alternative solution to commit
9405d87be25db6dff4d7b5ab48a81bbf6d083e47 'hw/ide: Fix crash when plugging a
piix3-ide device into the x-remote machine' which allows for cleaning up the
ISA API while keeping PIIX IDE functions user-createable for an arbitrarily
long deprecation period.
Biosbits is a software written by Josh Triplett that can be downloaded by
visiting https://biosbits.org/. The github codebase can be found here:
https://github.com/biosbits/bits/tree/master. It is a software that exercizes
the bios components such as acpi and smbios tables directly through acpica
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