* Peter Maydell (peter.mayd...@linaro.org) wrote:
> On Thu, 15 Sept 2022 at 16:21, Dr. David Alan Gilbert
> wrote:
> >
> > * Peter Maydell (peter.mayd...@linaro.org) wrote:
> > > On Tue, 6 Sept 2022 at 20:41, John Snow wrote:
> > > > Hi, I suspect I have asked this before, but I didn't write it
We already limit the scope of the cross system build to reduce the
cross build times. With the recent addition of more targets we are
also running into timeout issues for some of the cross user builds.
I've selected a few of those linux-user targets which are less likely
to be in common use as
On Mon, 22 Aug 2022 at 17:41, Richard Henderson
wrote:
>
> This value is unused.
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/ptw.c | 5 ++---
> 1 file changed, 2 insertions(+), 3 deletions(-)
>
> diff --git a/target/arm/ptw.c b/target/arm/ptw.c
> index 680139b478..5c6e5eea88 100644
On Mon, 22 Aug 2022 at 16:59, Richard Henderson
wrote:
>
> Use a switch. Do not apply memattr or shareability for Stage2
> translations. Make sure to apply HCR_{DC,DCT} only to Regime_EL10,
> per the pseudocode in AArch64.S1DisabledOutput.
>
> Signed-off-by: Richard Henderson
> ---
> +
The ACPI GTDT table contains two invalid 64-bit physical addresses according to
the ACPI spec. 6.5 [1]. Those are the Counter Control Base physical address and
the Counter Read Base physical address. Those fields of the GTDT table should be
set to 0x if not provided, rather than
On Tue, Sep 20, 2022 at 6:30 PM Mark Cave-Ayland
wrote:
> On 17/09/2022 23:27, Philippe Mathieu-Daudé via wrote:
> > On 17/9/22 14:09, BALATON Zoltan wrote:
> >> On Sat, 17 Sep 2022, Mark Cave-Ayland wrote:
> >>> There are already 32 feature bits in use, so change the size of the m68k
> >>> CPU
From: Richard Henderson
As pmovmskb is used by strlen et al, this is the third
highest overhead sse operation at %0.8.
Signed-off-by: Richard Henderson
[Reorganize to generate code for any vector size. - Paolo]
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/emit.c.inc | 90
From: Thomas Huth
It's still based on Fedora 30 - which is not supported anymore by QEMU
since years. Seems like nobody is using (and refreshing) this, and it's
easier to test this via a container anyway, so let's remove this now.
Signed-off-by: Thomas Huth
Message-Id:
We missed removing this dependency when we flattened the build.
Fixes: 39ce923732 (gitlab: enable a very minimal build with the tricore
container)
Signed-off-by: Alex Bennée
Reviewed-by: Thomas Huth
Message-Id: <20220914155950.804707-16-alex.ben...@linaro.org>
diff --git
Signed-off-by: Helge Deller
---
linux-user/strace.list | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/linux-user/strace.list b/linux-user/strace.list
index ad9ef94689..97d8ccadac 100644
--- a/linux-user/strace.list
+++ b/linux-user/strace.list
@@ -355,7 +355,7 @@
{
It's becoming harder to maintain a cross-compiler to test this host
architecture as the old stable Debian 10 ("Buster") moved into LTS
which supports fewer architectures. For now:
- mark it's deprecation in the docs
- downgrade the containers to build TCG tests only
- drop the cross builds
The new implementation of SSE will cover AVX from the get go, so include
the 24 extra comparison operators that are only available with the VEX
prefix.
Based on a patch by Paul Brook .
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
target/i386/ops_sse.h| 38
The new implementation of SSE will cover AVX from the get go, because
all the work for the helper functions is already done. We just need to
build them.
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
target/i386/helper.h | 2 ++
target/i386/ops_sse.h| 5 +
On 19/9/22 10:13, Richard Henderson wrote:
On 9/18/22 00:29, Philippe Mathieu-Daudé wrote:
On 17/9/22 13:25, Mark Cave-Ayland wrote:
Any write to SR can change the security state so always call
gen_exit_tb() when
this occurs. In particular MacOS makes use of andiw/oriw in a few
places to
These are mostly moves, and yet are a total pain. The main issue
is that:
1) some instructions are selected by mod==11 (register operand)
vs. mod=00/01/10 (memory operand)
2) stores to memory are two-operand operations, while the 3-register
and load-from-memory versions operate on the entire
Update to the latest stable Debian. While we are at it flatten into a
single dockerfile. We also need to ensure we install clang as it is
used for those builds as well.
It would be nice to port this to lcitool but for now this will do.
Signed-off-by: Alex Bennée
Reviewed-by: Thomas Huth
Compared to Paul's implementation, the new decoder will use a different approach
to implement AVX's merging of dst with src1 on scalar operations. Adjust the
old SSE decoder to be compatible with new-style helpers.
The affected instructions are CVTSx2Sx, ROUNDSx, RSQRTSx, SQRTSx, RCPSx.
Many SSE and AVX instructions are only valid with specific prefixes
(none, 66, F3, F2). Introduce a direct way to encode this in the
decoding table to avoid using decode groups too much.
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/decode-new.c.inc | 37
On the parisc architecture the stack grows upwards.
Move the TASK_UNMAPPED_BASE to high memory area as it's done by the
kernel on physical machines.
Signed-off-by: Helge Deller
---
linux-user/mmap.c | 4
1 file changed, 4 insertions(+)
diff --git a/linux-user/mmap.c b/linux-user/mmap.c
From: Víctor Colombo
Signed-off-by: Víctor Colombo
Reviewed-by: Richard Henderson
Message-Id: <20220905123746.54659-2-victor.colo...@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza
---
target/ppc/insn32.decode | 7 +++
target/ppc/translate/fp-impl.c.inc | 29
From: Víctor Colombo
Add the Special Purpose Registers HASHKEYR and HASHPKEYR, which were
introduced by the Power ISA 3.1B. They are used by the new instructions
hashchk(p) and hashst(p).
The ISA states that the Operating System should generate the value for
these registers when creating a
The 2nd check on RAM_SAVE_FLAG_CONTINUE is a bit redundant. Use a boolean
to be clearer.
Signed-off-by: Peter Xu
---
migration/ram.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/migration/ram.c b/migration/ram.c
index fc59c052cf..62ff2c1469 100644
---
Hi Markus,
> Any overlap with Dongwon Kim's "[PATCH v5 0/2] handling guest multiple
> displays"?
[Kasireddy, Vivek] Yes, there is some overlap but as I mentioned in the cover
letter,
this series is intended to replace Dongwon's series dealing with multiple
displays.
>
> Message-Id:
On Tue, Sep 20, 2022 at 06:52:27PM -0400, Peter Xu wrote:
> With the new code to send pages in rp-return thread, there's little help to
> keep lots of the old code on maintaining the preempt state in migration
> thread, because the new way should always be faster..
>
> Then if we'll always send
We used to allocate PSS structure on the stack for precopy when sending
pages. Make it static, so as to describe per-channel ram migration status.
Here we declared RAM_CHANNEL_MAX instances, preparing for postcopy to use
it, even though this patch has not yet to start using the 2nd instance.
Don't take the bitmap mutex when sending pages, or when being throttled by
migration_rate_limit() (which is a bit tricky to call it here in ram code,
but seems still helpful).
It prepares for the possibility of concurrently sending pages in >1 threads
using the function ram_save_host_page()
On Tue, Sep 20, 2022 at 8:59 PM Michael S. Tsirkin wrote:
>
> On Tue, Sep 20, 2022 at 10:03:23AM +0800, Jason Wang wrote:
> > On Tue, Sep 20, 2022 at 9:38 AM Jason Wang wrote:
> > >
> > > On Tue, Sep 20, 2022 at 9:10 AM liuhaiwei wrote:
> > > >
> > > > From: liuhaiwei
> > > >
> > > > the limit
On 17/09/2022 13:09, BALATON Zoltan wrote:
On Sat, 17 Sep 2022, Mark Cave-Ayland wrote:
There are already 32 feature bits in use, so change the size of the m68k
CPU features to uint64_t (allong with the associated m68k_feature()
functions) to allow up to 64 feature bits to be used.
On 14/09/2022 13.52, Richard Henderson wrote:
From: Peter Maydell
The PMU cycle and event counter infrastructure design requires that
operations on the PMU register fields are wrapped in pmu_op_start()
and pmu_op_finish() calls (or their more specific pmmcntr and
pmevcntr equivalents). This
The later prefix wins if both are present, make it show in s->prefix too.
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/decode-new.c.inc | 160 ++-
target/i386/tcg/decode-new.h | 32 +++
target/i386/tcg/emit.c.inc | 37 ++-
target/i386/tcg/translate.c | 18 ++--
4 files changed, 235 insertions(+), 12
Now lcitool has support for building a x86_64 cross image we can use
it for this.
Signed-off-by: Alex Bennée
Acked-by: Thomas Huth
Message-Id: <20220914155950.804707-26-alex.ben...@linaro.org>
diff --git a/.gitlab-ci.d/container-cross.yml b/.gitlab-ci.d/container-cross.yml
index
Update to the latest stable Debian. While we are at it flatten into a
single dockerfile. We really don't need the rest of the stuff from
the QEMU base image just to compile test images.
Signed-off-by: Alex Bennée
Reviewed-by: Thomas Huth
Message-Id:
These are more simple integer instructions present in both MMX and SSE/AVX,
with no holes that were later occupied by newer instructions.
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/decode-new.c.inc | 28
target/i386/tcg/emit.c.inc | 32
Add gpios in/out init for aspeed gpio to add the ability to connect
to other gpio devices.
Based the qdev-core.h comments, If you want to connect a GPIO to other
devices, you need to call qdev_init_gpio_in() or qdev_init_gpio_out().
```
For input gpios:
*
* Outbound GPIO lines can be connected
This adds another kind of weirdness when you thought you had seen it all:
an opcode byte that comes _after_ the address, not before. It's not
worth adding a new X86_SPECIAL_* constant for it, but it's actually
not unlike VCMP; so, forgive me for exploiting the similarity and just
deciding to
From: Paul Brook
Adjust all #ifdefs to match the ones in ops_sse.h.
Signed-off-by: Paul Brook
Message-Id: <20220424220204.2493824-23-p...@nowt.org>
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
target/i386/ops_sse_header.h | 114 +++
1 file
The following changes since commit d29201ff34a135cdfc197f4413c1c5047e4f58bb:
Merge tag 'pull-hmp-20220915a' of https://gitlab.com/dagrh/qemu into staging
(2022-09-17 10:31:11 -0400)
are available in the Git repository at:
https://gitlab.com/danielhb/qemu.git tags/pull-ppc-20220920
for you
From: Víctor Colombo
In ppc emulation, exception flags are not cleared at the end of an
instruction. Instead, the next instruction is responsible to clear
it before its emulation. However, some helpers are not doing it,
causing an issue where the previously set exception flags are being
used and
On Wed, Aug 24, 2022 at 01:41:29PM -0400, Stefan Hajnoczi wrote:
> On Thu, Aug 18, 2022 at 02:46:19PM -0400, Yusuke Okada wrote:
> > From: Yusuke Okada
> >
> > The "%f" specifier in g_date_time_format() is only available in glib
> > 2.65.2 or later. If combined with older glib, the function
On Tue, Sep 20, 2022 at 02:25:48PM -0400, Stefan Hajnoczi wrote:
> On Tue, 20 Sept 2022 at 10:18, Alex Bennée wrote:
> >
> >
> > Stefan Hajnoczi writes:
> >
> > > [[PGP Signed Part:Undecided]]
> > > On Fri, Sep 16, 2022 at 07:51:40AM +0100, Alex Bennée wrote:
> > >>
> > >> Alex Bennée writes:
>
From: Víctor Colombo
Very trivial rogue space removal. There are two spaces between Int128
and s128 in ppc_vsr_t struct, where it should be only one.
Signed-off-by: Víctor Colombo
Reviewed-by: Daniel Henrique Barboza
Message-Id: <20220906125523.38765-2-victor.colo...@eldorado.org.br>
This patchset does bug fixes that I found when testing preempt-full.
Patch 1 should fix a possible deadloop when I hit when testing the
preempt-full code. I didn't verify it because it's so hard to trigger, but
the logic should be explained in the patch.
Patch 2 fixes a race condition I can
From: Bernhard Beschow
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Bernhard Beschow
Message-Id: <20220919231720.163121-5-shen...@gmail.com>
Signed-off-by: Daniel Henrique Barboza
---
include/hw/ppc/spapr.h | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git
From: Víctor Colombo
Implementation for instructions hashst and hashchk, which were added
in Power ISA 3.1B.
It was decided to implement the hash algorithm from ground up in this
patch exactly as described in Power ISA.
Signed-off-by: Víctor Colombo
Reviewed-by: Lucas Mateus Castro
It should have been automatic, there's mirroring set up.
Paolo
Il mar 20 set 2022, 23:00 Jason A. Donenfeld ha scritto:
> On Mon, Sep 19, 2022 at 04:35:54PM +0200, Jason A. Donenfeld wrote:
> > FYI, that commit made it to:
> >
> > https://github.com/bonzini/qboot
> >
> > But wasn't pushed to:
From: Víctor Colombo
The macros xer_ov, xer_ca, xer_ov32, and xer_ca32 are both unused and
hiding the usage of env. Remove them.
Signed-off-by: Víctor Colombo
Reviewed-by: Daniel Henrique Barboza
Message-Id: <20220906125523.38765-3-victor.colo...@eldorado.org.br>
Signed-off-by: Daniel
Am 20. September 2022 09:55:37 UTC schrieb Peter Maydell
:
>On Tue, 20 Sept 2022 at 00:18, Bernhard Beschow wrote:
>>
>> In address-spaces.h it can be read that get_system_memory() and
>> get_system_io() are temporary interfaces which "should only be used
>> temporarily
>> until a proper bus
Am 20. September 2022 04:50:51 UTC schrieb "Philippe Mathieu-Daudé"
:
>On 20/9/22 01:17, Bernhard Beschow wrote:
>> The next commit would not compile w/o the include directive.
>>
>> Signed-off-by: Bernhard Beschow
>> ---
>> include/exec/hwaddr.h | 1 +
>> 1 file changed, 1 insertion(+)
>>
Am 20. September 2022 15:36:26 UTC schrieb Mark Cave-Ayland
:
>On 20/09/2022 10:55, Peter Maydell wrote:
>
>> On Tue, 20 Sept 2022 at 00:18, Bernhard Beschow wrote:
>>>
>>> In address-spaces.h it can be read that get_system_memory() and
>>> get_system_io() are temporary interfaces which "should
Am 20. September 2022 11:36:47 UTC schrieb Markus Armbruster
:
>Alistair Francis writes:
>
>> On Tue, Sep 20, 2022 at 9:18 AM Bernhard Beschow wrote:
>>>
>>> SiFiveEState inherits from SysBusDevice while it's TypeInfo claims it to
>>> inherit from TYPE_MACHINE. This is an inconsistency which
On Mon, Sep 19, 2022 at 04:35:54PM +0200, Jason A. Donenfeld wrote:
> FYI, that commit made it to:
>
> https://github.com/bonzini/qboot
>
> But wasn't pushed to:
>
> https://github.com/qemu/qboot
> https://gitlab.com/qemu-project/qboot
> https://git.qemu.org/?p=qboot.git;a=summary
>
> I have
Wang Liang writes:
> On Tue, 2022-09-20 at 13:18 +, Alberto Garcia wrote:
>> On Tue 20 Sep 2022 08:33:50 PM +08, wanglian...@126.com wrote:
>> > From: Wang Liang
>> >
>> > The delay time should never be a negative value.
>> >
>> > -return limit->slice_end_time - now;
>> > +return
From: Thomas Huth
The assets that this test tries to download have been removed from the
server. Update to a newer version to get it working again.
Signed-off-by: Thomas Huth
Reviewed-by: Alistair Francis
Message-Id: <20220829080940.110831-1-th...@redhat.com>
Signed-off-by: Alex Bennée
ldq takes a pointer to the first byte to load the 64-bit word in;
ldo takes a pointer to the first byte of the ZMMReg. Make them
consistent, which will be useful in the new SSE decoder's
load/writeback routines.
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 43
These are mostly floating-point SSE operations. The odd ones out
are MOVMSK and CVTxx2yy, the others are straightforward.
Unary operations are a bit special in AVX because they have 2 operands
for PD/PS operands (VEX. must be b), and 3 operands for SD/SS.
They are handled using
The following changes since commit d29201ff34a135cdfc197f4413c1c5047e4f58bb:
Merge tag 'pull-hmp-20220915a' of https://gitlab.com/dagrh/qemu into staging
(2022-09-17 10:31:11 -0400)
are available in the Git repository at:
https://github.com/stsquad/qemu.git tags/pull-testing-next-200922-2
The "O" operand type in the Intel SDM needs to load an 8- to 64-bit
unsigned value, while insn_get is limited to 32 bits. Extract the code
out of disas_insn and into a separate function.
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 36
Update to the latest stable Debian. While we are at it flatten into a
single dockerfile as we do not some of the extraneous packages from
the base image to build the toolchain.
Signed-off-by: Alex Bennée
Reviewed-by: Richard Henderson
Message-Id:
From: Richard Henderson
This will be used for emission and endian adjustments of gvec operations.
Signed-off-by: Richard Henderson
Message-Id: <2022083722.1697758-2-richard.hender...@linaro.org>
Signed-off-by: Paolo Bonzini
---
target/i386/cpu.h | 56
This patchset adds a simple latching_switch, which is a switch that
can be turned on/off by a trigger.
The latching switch is a switch that can be turned on and off.
When the input new state and match the trigger edge, the switch
state will be toggled.
This device privide 2 properties
Nothing special going on here, for once.
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/decode-new.c.inc | 5 +++
target/i386/tcg/emit.c.inc | 75
target/i386/tcg/translate.c | 1 +
3 files changed, 81 insertions(+)
From: Víctor Colombo
According to PowerISA: "OV32 is set whenever OV is implicitly set, and
is set to the same value that OV is defined to be set to in 32-bit
mode".
This patch changes helper_update_ov_legacy to set/clear ov32 when
applicable.
Signed-off-by: Víctor Colombo
Reviewed-by: Daniel
From: Víctor Colombo
According to the ISA, for instruction DENBCD:
"If an invalid BCD digit or sign code is detected in the source
operand, an invalid-operation exception (VXCVI) occurs."
In the Invalid Operation Exception section, there is the situation:
"When Invalid Operation Exception is
From: Víctor Colombo
FPR register are mapped to the first doubleword of the VSR registers.
Since PowerISA v3.1, the second doubleword of the target register
must be zeroed for FP instructions.
This patch does it by writting 0 to the second dw everytime the
first dw is being written using
With the new code to send pages in rp-return thread, there's little help to
keep lots of the old code on maintaining the preempt state in migration
thread, because the new way should always be faster..
Then if we'll always send pages in the rp-return thread anyway, we don't
need those logic to
From: Xuzhou Cheng
pnv_phb3_root_bus_info and pnv_phb4_root_bus_info are missing the
instance_size initialization. This results in accessing out-of-bound
memory when setting 'chip-id' and 'phb-id', and eventually crashes
glib's malloc functionality with the following message:
Il mer 21 set 2022, 00:11 Jason A. Donenfeld ha scritto:
> On Tue, Sep 20, 2022 at 11:57:09PM +0200, Paolo Bonzini wrote:
> > It should have been automatic, there's mirroring set up.
>
> Hm, something is weird. Gitlab says "This project is mirrored from
> https://gitlab.com/bonzini/qboot.git.
On Tue, 2022-09-20 at 13:18 +, Alberto Garcia wrote:
> On Tue 20 Sep 2022 08:33:50 PM +08, wanglian...@126.com wrote:
> > From: Wang Liang
> >
> > The delay time should never be a negative value.
> >
> > -return limit->slice_end_time - now;
> > +return MAX(limit->slice_end_time -
On Mon, 22 Aug 2022 at 17:43, Richard Henderson
wrote:
>
> These subroutines did not need ENV for anything except
> retrieving the effective value of HCR anyway.
>
> We have computed the effective value of HCR in the callers,
> and this will be especially important for interpreting HCR
> in a
We want to migrate from docker.py to building our images directly with
docker/podman. Before we get there we need to make sure we don't
re-introduce our layered builds so bug out if we see FROM qemu/ in a
Dockerfile.
Signed-off-by: Alex Bennée
Acked-by: Thomas Huth
Reviewed-by: Richard
We should be aiming to keep our tests under 2 minutes so lets reduce
the default timeout to that. Tests that we know take longer should
explicitly set a longer timeout.
Signed-off-by: Alex Bennée
Reviewed-by: Richard Henderson
Message-Id: <20220914155950.804707-8-alex.ben...@linaro.org>
diff
We no longer use these in any of our images. Clean-up the remaining
comments and documentation that reference them and remove from the
build.
Signed-off-by: Alex Bennée
Reviewed-by: Thomas Huth
Reviewed-by: Richard Henderson
Message-Id: <20220914155950.804707-31-alex.ben...@linaro.org>
diff
We don't want to rely on the soon to be reduced default time. These
tests are still slow for something we want to run in CI though.
Signed-off-by: Alex Bennée
Reviewed-by: Richard Henderson
Message-Id: <20220914155950.804707-6-alex.ben...@linaro.org>
diff --git a/tests/avocado/boot_linux.py
Because these are the only VEX instructions that QEMU supports, the
new decoder is entered on the first byte of a valid VEX prefix, and VEX
decoding only needs to be done in decode-new.c.inc.
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/decode-new.c.inc | 59
This is working around current limitation of Meson's handling of
--disable-pie.
Signed-off-by: Alex Bennée
Cc: Paolo Bonzini
Reviewed-by: Richard Henderson
Message-Id: <20220914155950.804707-19-alex.ben...@linaro.org>
diff --git a/configure b/configure
index 575dde1c1f..0bbf9d28af 100755
---
Update to the latest stable Debian. While we are at it flatten into a
single dockerfile as we do not need anything from the base image to
build the toolchain. This is used to build both the nios and
microblaze toolchains.
Signed-off-by: Alex Bennée
Reviewed-by: Thomas Huth
Reviewed-by: Richard
Compared to Paul's implementation, the new decoder will use a different approach
to implement AVX's merging of dst with src1 on scalar operations. Adjust the
helpers to provide this functionality.
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
target/i386/ops_sse.h | 16
Implement a simple latching switch device.
The latching switch is a switch that can be turned on and off.
When the input new state and match the trigger edge, the switch
state will be toggled.
This device privide 2 properties `state(bool)` and `trigger-edge(string)`,
and 2 gpios `input` and
Three-byte opcodes from the 0F3Ah area all have an immediate byte which
is usually unsigned. Clarify in the helper code that it is unsigned;
the new decoder treats immediates as signed by default, and seeing
an intN_t in the prototype might give the wrong impression that one
can use
These are exactly the same as the non-VEX version, but one has to be careful
that only VEX.L=0 is allowed.
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/decode-new.c.inc | 25 +
target/i386/tcg/emit.c.inc | 20
2 files changed, 45
Add to the helpers all the operands that are needed to implement AVX.
Extracted from a patch by Paul Brook .
Message-Id: <20220424220204.2493824-26-p...@nowt.org>
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
target/i386/ops_sse.h| 173
Extracted from a patch by Paul Brook .
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
tests/tcg/i386/Makefile.target | 2 +-
tests/tcg/i386/test-avx.c | 201 ++---
tests/tcg/i386/test-avx.py | 5 +-
3 files changed, 113 insertions(+),
Flatten into a single dockerfile. We really don't need the rest of the
stuff from the QEMU base image just to compile test images.
Signed-off-by: Alex Bennée
Reviewed-by: Thomas Huth
Message-Id: <20220914155950.804707-15-alex.ben...@linaro.org>
diff --git a/.gitlab-ci.d/container-cross.yml
The following changes since commit 621da7789083b80d6f1ff1c0fb499334007b4f51:
Update version for v7.1.0 release (2022-08-30 09:40:11 -0700)
are available in the Git repository at:
https://github.com/hdeller/qemu-hppa.git tags/publish1-pull-request
for you to fetch changes up to
Signed-off-by: Helge Deller
---
linux-user/strace.c | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/linux-user/strace.c b/linux-user/strace.c
index 6f818212d5..b6b9abaea4 100644
--- a/linux-user/strace.c
+++ b/linux-user/strace.c
@@ -3714,11 +3714,20 @@
On 20/9/22 17:17, Zhang Jian wrote:
Hi Philippe,
Thanks for your reply.
On Tue, Sep 20, 2022 at 7:09 AM Philippe Mathieu-Daudé wrote:
Hi Jian,
On 19/9/22 19:21, Jian Zhang wrote:
This patchset adds a host power device and added it into the g220a
mahcine. The BMC have a important is to
Now with rs->pss we can already cache channels in pss->pss_channels. That
pss_channel contains more infromation than rs->f because it's per-channel.
So rs->f could be replaced by rss->pss[RAM_CHANNEL_PRECOPY].pss_channel,
while rs->f itself is a bit vague now.
Note that vanilla postcopy still
From: Víctor Colombo
Implementation for instructions hashstp and hashchkp, the privileged
versions of hashst and hashchk, which were added in Power ISA 3.1B.
Signed-off-by: Víctor Colombo
Reviewed-by: Lucas Mateus Castro
Message-Id: <20220715205439.161110-4-victor.colo...@eldorado.org.br>
From: Xuzhou Cheng
spapr->htab is allocated by qemu_memalign(), hence we should use
qemu_vfree() to free it.
Fixes: c5f54f3e31bf ("pseries: Move hash page table allocation to reset time")
Fixes: b4db54132ffe ("target/ppc: Implement H_REGISTER_PROCESS_TABLE H_CALL"")
Signed-off-by: Xuzhou Cheng
Add the helper to show that postcopy preempt enabled, meanwhile active.
Reviewed-by: Dr. David Alan Gilbert
Signed-off-by: Peter Xu
---
migration/ram.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/migration/ram.c b/migration/ram.c
index 1d42414ecc..d8cf7cc901
df22fbb751 ("qboot: update to latest submodule") updated the qboot
submodule from a5300c49 to 8ca302e8. However, qboot isn't built during
the QEMU's build process but rather is included in binary form. So
rebuild it here.
Cc: Paolo Bonzini
Signed-off-by: Jason A. Donenfeld
---
Paolo - I have no
On Tue, 20 Sep 2022, Miguel Luis wrote:
> Step 3 from bios-tables-test.c documented procedure.
>
> Signed-off-by: Miguel Luis
Acked-by: Ani Sinha
> ---
> tests/qtest/bios-tables-test-allowed-diff.h | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git
On Tue, 20 Sep 2022, Miguel Luis wrote:
> Step 6 & 7 of the bios-tables-test.c documented procedure.
>
> Differences between disassembled ASL files for GTDT:
>
> @@ -13,14 +13,14 @@
> [000h 4]Signature : "GTDT"[Generic Timer
> Description Table]
>
Step 6 & 7 of the bios-tables-test.c documented procedure.
Differences between disassembled ASL files for GTDT:
@@ -13,14 +13,14 @@
[000h 4]Signature : "GTDT"[Generic Timer
Description Table]
[004h 0004 4] Table Length : 0060
Flatten into a single dockerfile and update to match the rest of the
test cross compile dockerfiles.
Signed-off-by: Alex Bennée
Reviewed-by: Richard Henderson
Message-Id: <20220914155950.804707-23-alex.ben...@linaro.org>
diff --git a/.gitlab-ci.d/container-cross.yml
On 17/09/2022 23:27, Philippe Mathieu-Daudé via wrote:
On 17/9/22 14:09, BALATON Zoltan wrote:
On Sat, 17 Sep 2022, Mark Cave-Ayland wrote:
There are already 32 feature bits in use, so change the size of the m68k
CPU features to uint64_t (allong with the associated m68k_feature()
functions)
Add generic code generation that takes care of preparing operands
around calls to decode.e.gen in a table-driven manner, so that ALU
operations need not take care of that.
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/decode-new.c.inc | 33 ++-
target/i386/tcg/decode-new.h | 7 ++
The new decoder is based on three principles:
- use mostly table-driven decoding, using tables derived as much as possible
from the Intel manual. Centralizing the decode the operands makes it
more homogeneous, for example all immediates are signed. All modrm
handling is in one function,
The more complicated ones here are d6-d7, e6-e7, f7. The others
are trivial.
For LDDQU, using gen_load_sse directly might corrupt the register if
the second part of the load fails. Therefore, add a custom X86_TYPE_WM
value; like X86_TYPE_W it does call gen_load(), but it also rejects a
value of
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