On 3/13/23 7:40 PM, Philippe Mathieu-Daudé wrote:
On 25/2/23 07:35, Gavin Shan wrote:
For some architectures like ARM64, multiple CPUs in one cluster can be
associated with different NUMA nodes, which is irregular configuration
because we shouldn't have this in baremetal environment. The
From: David Woodhouse
When dm_restrict is set, QEMU isn't permitted to update the XenStore node
to indicate its running status. Previously, the xs_write() call would fail
but the failure was ignored.
However, in refactoring to allow for emulated XenStore operations, a new
call to xs_open() was
On 27/2/23 17:31, Jonathan Cameron wrote:
From: Gregory Price
Defines are starting to exceed line length limits, align them for
cleanliness before making modifications.
Signed-off-by: Gregory Price
Signed-off-by: Jonathan Cameron
---
tests/qtest/cxl-test.c | 84
> > diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h
> > index 7e5ad65c1d..d589f78202 100644
> > --- a/include/hw/cxl/cxl_device.h
> > +++ b/include/hw/cxl/cxl_device.h
> > @@ -232,6 +232,14 @@ REG64(CXL_MEM_DEV_STS, 0)
> > FIELD(CXL_MEM_DEV_STS, MBOX_READY, 4, 1)
> >
On Tue, Mar 14, 2023 at 12:46:18PM +, Peter Maydell wrote:
> On Tue, 14 Mar 2023 at 10:12, Dr. David Alan Gilbert
> wrote:
> >
> > Copying Peter Xu on this one since it's poscopy, especially the newer
> > postcopy preempt.
> >
> > * Peter Maydell (peter.mayd...@linaro.org) wrote:
> > > On
On Tue, Mar 14, 2023 at 12:43:12PM +, Mark Cave-Ayland wrote:
> On 14/03/2023 06:33, Michael S. Tsirkin wrote:
>
> > On Tue, Mar 14, 2023 at 12:01:09AM -0400, Chuck Zmudzinski wrote:
> > > Commit 4f67543bb8c5 ("xen/pt: reserve PCI slot 2 for Intel igd-passthru")
> > > uses slot_reserved_mask
On Mon, 13 Mar 2023 at 14:11, Thomas Huth wrote:
>
> Hi Peter!
>
> The following changes since commit 29c8a9e31a982874ce4e2c15f2bf82d5f8dc3517:
>
> Merge tag 'linux-user-for-8.0-pull-request' of
> https://gitlab.com/laurent_vivier/qemu into staging (2023-03-12 10:57:00
> +)
>
> are
Copying Peter Xu on this one since it's poscopy, especially the newer
postcopy preempt.
* Peter Maydell (peter.mayd...@linaro.org) wrote:
> On Sun, 12 Mar 2023 at 14:06, Peter Maydell wrote:
> >
> > On Tue, 7 Mar 2023 at 09:53, Peter Maydell wrote:
> > >
> > > On Sat, 4 Mar 2023 at 15:39, Peter
On Tue, 2023-03-14 at 08:06 +0100, Christian Borntraeger wrote:
>
>
> Am 13.03.23 um 22:16 schrieb Ilya Leoshkevich:
> > TCG emulates ckc, cputm, last_break and prefix, and it's quite
> > useful
> > to have them during debugging.
>
> KVM provides those as well so I dont get what you are trying
On Tue, Jan 17, 2023 at 07:16:35PM +0100, Pavel Pisa wrote:
> Dear Ben,
>
> sorry for longer response times...
I think we've both dropped the ball on this one, just got reminded about
this set and found it got deleted from work email.
We've done review upates and will try and get some branches
Add a small test that checks whether early exceptions are recognized
and whether the correct ILC and old PSW are stored when they happen.
Signed-off-by: Ilya Leoshkevich
---
tests/tcg/s390x/Makefile.softmmu-target | 1 +
tests/tcg/s390x/early-exception-recognition.S | 38
Generate specification exception if a reserved bit is set in the PSW
mask or if the PSW address is out of bounds dictated by the addresing
mode.
Reported-by: Nina Schoetterl-Glausch
Signed-off-by: Ilya Leoshkevich
---
target/s390x/cpu.c | 26 ++
Fix this format string warning when defining MSI_DEBUG:
hw/pci/msi.c:209:28: warning: format specifies type 'char' but the argument
has type 'unsigned int' [-Wformat]
offset, nr_vectors, msi64bit, msi_per_vector_mask);
Per MST in [*]: "Calling pci_add_capability when VM is running is
likely to confuse guests".
Ensure this can't happen by asserting pci_add_capability() is never
called after a PCI device is realized.
[*]
https://lore.kernel.org/qemu-devel/20230308071628-mutt-send-email-...@kernel.org/
Based-on:
Hi Volker,
Thank you for the clarification. I see the problem now.
So is it safe to say that:
@@ -104,8 +104,9 @@ playback_on_process(void *data)
/* calculate the total no of bytes to read data from buffer */
req = b->requested * v->frame_size;
if (req == 0) {
-req = 4096
Both TCG and KVM emulate ckc, cputm, last_break and prefix, and it's
quite useful to have them during debugging. Right now they are grouped
together with KVM-only pp, pfault_token, pfault_select and
pfault_compare in s390-virt.xml, and are not available when debugging
TCG-emulated code.
Move
On Tue, Mar 14, 2023 at 4:35 AM David Woodhouse wrote:
>
> From: David Woodhouse
>
> When dm_restrict is set, QEMU isn't permitted to update the XenStore node
> to indicate its running status. Previously, the xs_write() call would fail
> but the failure was ignored.
>
> However, in refactoring
Hi,
Currently loading bad PSW flags does not lead to an exception, which is
not correct. This series fixes this by implementing what PoP calls
"Early Exception Recognition". Since it applies to both loading PSW with
LPSW/LPSWE and to interrupt handling, s390_cpu_set_psw() looks like the
right
On Monday, March 13, 2023 8:06:15 PM CET Dorinda Bassey wrote:
> >
> > Are you sure about sizeof(n_bytes) here? That's 4. ;-)
> >
> my bad!
>
> >
> > Volker's point was that "silence" is the center of the wave range. With
> > signed
> > range that's zero, yes, but with unsigned range that's
PCI capabilities can't appear magically at runtime.
Guests aren't expecting that. Assert all capabilities
are added _before_ a device instance is realized.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/pci/pci.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/hw/pci/pci.c
This 'used' array is allocated via:
pci_qdev_realize() -> do_pci_register_device() -> pci_config_alloc()
In a perfect world where all device models are correctly QOM'ified
this can't happen. Still it occured to me while refactoring QDev and
it was not obvious to figure out. This assert helped,
A PCI device can't magically become MSI-capable at runtime.
Guests aren't expecting that. Assert MSI is initialized
_before_ a device instance is realized.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/pci/msi.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/pci/msi.c b/hw/pci/msi.c
Chuang Xu writes:
> From: Peter Xu
>
> Calling RCU variance of address_space_get|to_flatview() during memory
"variants" rather than "variance", perhaps?
> commit (flatview updates, triggering memory listeners, or updating
> ioeventfds, etc.) is not 100% accurate, because commit() requires BQL
Currently, the kerneldoc Sphinx plugin doesn't honour the
--enable-werror configure option, so its warnings are never fatal.
This is because although we do pass sphinx-build the -W switch, the
warnings from kerneldoc are produced by the scripts/kernel-doc script
directly and don't go through
On 14/03/2023 06:33, Michael S. Tsirkin wrote:
On Tue, Mar 14, 2023 at 12:01:09AM -0400, Chuck Zmudzinski wrote:
Commit 4f67543bb8c5 ("xen/pt: reserve PCI slot 2 for Intel igd-passthru")
uses slot_reserved_mask to reserve slot 2 for the Intel IGD for the
xenfv machine when the guest is
On 14/3/23 11:00, Dinah Baum wrote:
Moved architecture agnostic data types to their own
file to avoid "attempt to use poisoned TARGET_*"
error that results when including qapi header
with commands that aren't defined for all architectures.
Required to implement enabling
On Thu, Mar 09, 2023 at 11:39:44AM +, Richard W.M. Jones wrote:
> To implement multi-conn, we will put multiple underlying NBD
> connections (ie. NBDClientConnection) inside the NBD block device
> handle (BDRVNBDState). This requires first breaking the one-to-one
> relationship between
On 3/14/2023 2:33 AM, Michael S. Tsirkin wrote:
> On Tue, Mar 14, 2023 at 12:01:09AM -0400, Chuck Zmudzinski wrote:
> > Commit 4f67543bb8c5 ("xen/pt: reserve PCI slot 2 for Intel igd-passthru")
> > uses slot_reserved_mask to reserve slot 2 for the Intel IGD for the
> > xenfv machine when the guest
On Tue, Mar 14, 2023 at 08:33:02AM -0400, Chuck Zmudzinski wrote:
> On 3/14/2023 2:33 AM, Michael S. Tsirkin wrote:
> > On Tue, Mar 14, 2023 at 12:01:09AM -0400, Chuck Zmudzinski wrote:
> > > Commit 4f67543bb8c5 ("xen/pt: reserve PCI slot 2 for Intel igd-passthru")
> > > uses slot_reserved_mask to
On 14/03/2023 08:35, David Woodhouse wrote:
From: David Woodhouse
When dm_restrict is set, QEMU isn't permitted to update the XenStore node
to indicate its running status. Previously, the xs_write() call would fail
but the failure was ignored.
However, in refactoring to allow for emulated
On 14.03.23 00:38, Ilya Leoshkevich wrote:
The code uses the wrong base for relative addressing: it should use the
target instruction address and not the EXECUTE's address.
Fix by storing the target instruction address in the new CPUS390XState
member and loading it from the code generated by
On Mon, Mar 13, 2023 at 5:32 PM Kevin Wolf wrote:
> > So I still think that this bug is a symptom of a problem in the design
> > of request queuing.
> >
> > In fact, shouldn't request queuing was enabled at the _end_ of
> > bdrv_drained_begin (once the BlockBackend has reached a quiescent
> >
On Tue, 14 Mar 2023 at 10:12, Dr. David Alan Gilbert
wrote:
>
> Copying Peter Xu on this one since it's poscopy, especially the newer
> postcopy preempt.
>
> * Peter Maydell (peter.mayd...@linaro.org) wrote:
> > On Sun, 12 Mar 2023 at 14:06, Peter Maydell
> > wrote:
> > > Here's another one, on
Change parsing of -cpu argument to allow -cpu cpu,help
to print options for the CPU type similar to
how the '-device' option works.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1480
Signed-off-by: Dinah Baum
---
cpu.c | 41 +++
This patch enables 'query-cpu-model-expansion' on all
architectures. Only architectures that implement
the command will return results, others will return an
error message as before.
This patch lays the groundwork for parsing a
-cpu cpu,help option as specified in
Moved architecture agnostic data types to their own
file to avoid "attempt to use poisoned TARGET_*"
error that results when including qapi header
with commands that aren't defined for all architectures.
Required to implement enabling `query-cpu-model-expansion`
on all architectures
Part 1 is a refactor/code motion patch for
qapi/machine target required for setup of
Part 2 which enables query-cpu-model-expansion
on all architectures
Part 3 implements the ',help' feature
Limitations:
Currently only 'FULL' expansion queries are implemented since
that's the only type enabled
* Peter Maydell (peter.mayd...@linaro.org) wrote:
> On Tue, 14 Mar 2023 at 10:12, Dr. David Alan Gilbert
> wrote:
> >
> > Copying Peter Xu on this one since it's poscopy, especially the newer
> > postcopy preempt.
> >
> > * Peter Maydell (peter.mayd...@linaro.org) wrote:
> > > On Sun, 12 Mar 2023
On 3/3/23 16:09, Jonathan Cameron wrote:
From: Ira Weiny
CXL has 24 bit unaligned fields which need to be stored to. CXL is
specified as little endian.
Define st24_le_p() and the supporting functions to store such a field
from a 32 bit host native value.
The use of b, w, l, q as the size
Hi Jonathan,
On 3/3/23 16:09, Jonathan Cameron wrote:
Note there are several series ahead of this one and in particular
the RAS error injection series needs some QAPI review.
The QAPI stuff in this patch is similar but in essence very similar
to what we have in that series.
Whilst I'm an
Am 13.03.23 um 22:16 schrieb Ilya Leoshkevich:
TCG emulates ckc, cputm, last_break and prefix, and it's quite useful
to have them during debugging.
KVM provides those as well so I dont get what you are trying to do here. (I
would understand moving out the pfault things into a KVM section)
This patch series adds qemu_strerror() function, which is thread-safe
version of the libc strerror(). The first patch introduces the
qemu_strerror() function, and the second patch replaces strerror()
function in linux-user/* with qemu_strerror() function.
Because it involves thread safety,
I'm sorry for sending ill-formed thread twice.
This problem was because the SMTP server overwrites Message-ID,
and git-sendemail does not reflect it to In-Reply-To: and Reply-To: in the
header.
I will test well before sending the next patch.
The original cover letter was
On Wed, Mar 8, 2023 at 4:10 AM Philipp Tomsich wrote:
>
> The Zicond standard extension implements the same instruction
> semantics as XVentanaCondOps, although using different mnemonics and
> opcodes.
>
> Point XVentanaCondOps to the (newly implemented) Zicond implementation
> to reduce the
Add qemu_strerror() which follows the POSIX specification for
strerror(). While strerror() is not guaranteed to be thread-safe, this
function is thread-safe.
This function is added to solve the following issue:
https://gitlab.com/qemu-project/qemu/-/issues/416
Signed-off-by: Yohei Kojima
---
strerror() is not guaranteed to be thread-safe as described in
(https://gitlab.com/qemu-project/qemu/-/issues/416).
This commit changes files under /linux-user that call strerror() to call
the safer qemu_strerror().
Signed-off-by: Yohei Kojima
---
linux-user/elfload.c | 4 ++--
On 3/3/23 16:09, Jonathan Cameron wrote:
Very simple implementation to allow testing of corresponding
kernel code. Note that for now we track each 64 byte section
independently. Whilst a valid implementation choice, it may
make sense to fuse entries so as to prove out more complex
corners of
On Mon, 2023-03-13 at 19:17 -0400, Jason Andryuk wrote:
> This looks good, better than what I posted, and seems to work for both
> dm_restrict set and unset.
Thanks.
> For dm_restricted, xs_write() does fail. I verified that with a print
> statement. I think "shouldn't even try" makes sense.
On Wed, Mar 8, 2023 at 4:10 AM Philipp Tomsich wrote:
>
> After the original Zicond support was stuck/fell through the cracks on
> the mailing list at v3 (and a different implementation was merged in
> the meanwhile), we need to refactor Zicond to prepare it to be reused
> by XVentanaCondOps.
>
>
On 3/3/23 16:09, Jonathan Cameron wrote:
Inject poison using qmp command cxl-inject-poison to add an entry to the
poison list.
For now, the poison is not returned CXL.mem reads,
What do you mean?
but only via the
mailbox command Get Poison List.
See CXL rev 3.0, sec 8.2.9.8.4.1 Get Poison
On Tue, Mar 14, 2023 at 12:01:09AM -0400, Chuck Zmudzinski wrote:
> Commit 4f67543bb8c5 ("xen/pt: reserve PCI slot 2 for Intel igd-passthru")
> uses slot_reserved_mask to reserve slot 2 for the Intel IGD for the
> xenfv machine when the guest is configured for igd-passthru.
>
> A desired
On 3/13/23 19:21, Richard Henderson wrote:
On 3/13/23 04:44, Luis Machado wrote:
Luis: I think that rather than doing (2) with a QEMU namespace,
we should define a gdb namespace for this. That makes it clear
that this is still a gdb-upstream-sanctioned way of exposing
the pauth registers.
From: Ivan Klokov
The decoding of the slli_uw currently contains decoding
error: shamt part of opcode has six bits, not five.
Fixes 3de1fb71("target/riscv: update disas.c for xnor/orn/andn and slli.uw")
Signed-off-by: Ivan Klokov
Reviewed-by: Philipp Tomsich
Acked-by: Alistair Francis
/alistair23/qemu.git tags/pull-riscv-to-apply-20230314
for you to fetch changes up to 0d581506de803204c5a321100afa270573382932:
Fix incorrect register name in disassembler for fmv,fabs,fneg instructions
(2023-03-14 16:36:43 +1000
From: Mikhail Tyutin
Fix incorrect register name in RISC-V disassembler for fmv,fabs,fneg
instructions
Signed-off-by: Mikhail Tyutin
Reviewed-by: Alistair Francis
Message-Id: <3454991f-7f64-24c3-9a36-f5fa2cc38...@yadro.com>
Signed-off-by: Alistair Francis
---
disas/riscv.c | 19
On 14/03/2023 13:26, Chuck Zmudzinski wrote:
On 3/14/2023 9:17 AM, Michael S. Tsirkin wrote:
On Tue, Mar 14, 2023 at 12:43:12PM +, Mark Cave-Ayland wrote:
On 14/03/2023 06:33, Michael S. Tsirkin wrote:
On Tue, Mar 14, 2023 at 12:01:09AM -0400, Chuck Zmudzinski wrote:
Commit
On Tue, 14 Mar 2023 at 14:01, Thomas Huth wrote:
>
> On 14/03/2023 14.33, Peter Maydell wrote:
> > The postcopy/preempt tests seem to have a race which makes them hang
> > on the s390x CI runner. Disable them for the moment, while we
> > investigate. As with the other disabled subtest, you can
The RVV verification will error out if fails and it's being done at the
end of riscv_cpu_validate_set_extensions(). Let's put it in its own
function and do it earlier.
We'll move it out of riscv_cpu_validate_set_extensions() in the near future,
but for now this is enough to clean the code a bit.
set_misa() is setting all 'misa' related env states and nothing else.
But other functions, namely riscv_cpu_validate_set_extensions(), uses
the config object to do its job.
This creates a need to set the single letter extensions in the cfg
object to keep both in sync. At this moment this is being
We have one last case where we're changing env->misa_ext* during
validation. riscv_cpu_disable_priv_spec_isa_exts(), at the end of
riscv_cpu_validate_set_extensions(), will disable cpu->cfg.ext_h and
cpu->cfg.ext_v if priv_ver check fails.
This check can be done in riscv_cpu_validate_misa_ext().
We're getting ready to use riscv_cpu_validate_set_extensions() to unify
the handling of write_misa() with the rest of the code base. But first
we need to deal with RVG.
The 'G' virtual extension enables a set of extensions in the CPU. At
this moment, this is done at the start of our validation
Cc'ing qemu-trivial@
On 24/2/23 22:41, Philippe Mathieu-Daudé wrote:
When modifying QAPI scripts and modifying C files along,
it makes sense to display QAPI changes first.
Signed-off-by: Philippe Mathieu-Daudé
---
Failed example:
On 3/14/2023 10:39 AM, Mark Cave-Ayland wrote:
> On 14/03/2023 14:21, Chuck Zmudzinski wrote:
>
> > On 3/14/2023 9:41 AM, Mark Cave-Ayland wrote:
> >> On 14/03/2023 13:26, Chuck Zmudzinski wrote:
> >>
> >>> On 3/14/2023 9:17 AM, Michael S. Tsirkin wrote:
> On Tue, Mar 14, 2023 at 12:43:12PM
On 3/14/23 06:47, Wu, Fei wrote:
On 3/13/2023 11:00 PM, Richard Henderson wrote:
On 3/13/23 07:13, Wu, Fei2 wrote:
Hi Richard,
Sorry for disturbing you. I'm doing some perf profiling on qemu-riscv64,
I see 10%+ faster to build stress-ng without the following patch. I know
it's incorrect to
On Tue, 14 Mar 2023 at 16:46, Peter Xu wrote:
> I've attached that simple fix. Peter, is it easy to verify it? I'm not
> sure the reproducability, fine by me too if it's easier to just disable
> preempt tests for 8.0 release.
If you all are happy that the fix is correct, I think the easiest
Am 13.03.2023 um 01:37 hat Wilfred Mallawa geschrieben:
> From: Wilfred Mallawa
>
> Fixup a few minor typos
>
> Signed-off-by: Wilfred Mallawa
Thanks, applied to the block-next branch.
Kevin
On 14/03/2023 18.08, Peter Maydell wrote:
The cadence UART attempts to avoid allowing the guset to set invalid
baud rate register values in the uart_write() function. However it
does the "mask to the size of the register field" and "check for
invalid values" in the wrong order, which means that
On Tue, Mar 14, 2023 at 12:46:34PM -0400, Peter Xu wrote:
> On Tue, Mar 14, 2023 at 10:11:53AM +, Dr. David Alan Gilbert wrote:
> > OK, I think I kind of see what's happening here, one for Peter Xu.
> > If I'm right it's a race something like:
> > a) The test harness tells the source it
On Tue, 14 Mar 2023, Fan Ni wrote:
Replace the magic number 32 with CXL_RAS_ERR_HEADER_NUM for better code
readability and maintainability.
Reviewed-by: Davidlohr Bueso
Signed-off-by: Fan Ni
---
include/hw/cxl/cxl_device.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
On Tue, 2023-03-14 at 12:00 +0100, Ilya Leoshkevich wrote:
> Generate specification exception if a reserved bit is set in the PSW
Generate a ...
> mask or if the PSW address is out of bounds dictated by the addresing
addresSing
> mode.
Does this approach also work with SET SYSTEM MASK and
* Peter Xu (pet...@redhat.com) wrote:
> On Tue, Mar 14, 2023 at 05:15:58PM +, Dr. David Alan Gilbert (git) wrote:
> > From: "Dr. David Alan Gilbert"
> >
> > The RDMA code has return-path handling code, but it's only enabled
> > if postcopy is enabled; if the 'return-path' migration
Hi Strahinja,
Looks good! I re-ran the tests on my machine, and they work fine:
ARMBIAN_ARTIFACTS_CACHED=yes AVOCADO_ALLOW_LARGE_STORAGE=yes
./build/tests/venv/bin/avocado --show=app,console run -t
machine:orangepi-pc -t machine:cubieboard
tests/avocado/boot_linux_console.py
...
|console: Tue
From: "Dr. David Alan Gilbert"
The RDMA code has return-path handling code, but it's only enabled
if postcopy is enabled; if the 'return-path' migration capability
is enabled, the return path is NOT setup but the core migration
code still tries to use it and breaks.
Enable the RDMA return path
Add 8.1 machine types for arm/i440fx/m68k/q35/s390x/spapr.
Signed-off-by: Cornelia Huck
---
hw/arm/virt.c | 9 -
hw/core/machine.c | 3 +++
hw/i386/pc.c | 3 +++
hw/i386/pc_piix.c | 16 +---
hw/i386/pc_q35.c | 14
On 14/03/2023 15.17, Peter Maydell wrote:
On Tue, 14 Mar 2023 at 14:14, Thomas Huth wrote:
On 14/03/2023 15.08, Peter Maydell wrote:
On Tue, 14 Mar 2023 at 14:01, Thomas Huth wrote:
On 14/03/2023 14.33, Peter Maydell wrote:
The postcopy/preempt tests seem to have a race which makes them
On Tue, Mar 14, 2023 at 05:15:58PM +, Dr. David Alan Gilbert (git) wrote:
> From: "Dr. David Alan Gilbert"
>
> The RDMA code has return-path handling code, but it's only enabled
> if postcopy is enabled; if the 'return-path' migration capability
> is enabled, the return path is NOT setup but
> -Original Message-
> From: Marco Liebel (QUIC)
> Sent: Monday, March 13, 2023 11:26 AM
> To: qemu-devel@nongnu.org
> Cc: Taylor Simpson ; Marco Liebel (QUIC)
>
> Subject: [PATCH] Use f-strings in python scripts
>
> Replace python 2 format string with f-strings
>
> Signed-off-by:
On 3/14/23 9:53 AM, Fan Ni wrote:
Replace the magic number 32 with CXL_RAS_ERR_HEADER_NUM for better code
readability and maintainability.
Signed-off-by: Fan Ni
Reviewed-by: Dave Jiang
---
include/hw/cxl/cxl_device.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
On Mon, 13 Mar 2023 at 20:02, wrote:
>
> From: Marc-André Lureau
>
> The following changes since commit 284c52eec2d0a1b9c47f06c3eee46762c5fc0915:
>
> Merge tag 'win-socket-pull-request' of
> https://gitlab.com/marcandre.lureau/qemu into staging (2023-03-13 13:44:17
> +)
>
> are available
ainer Ben Widawsky (2023-03-14 14:46:38 +0100)
>
>
> trivial branch pull request 20230314
>
> Update MAINTAINER file
> Fix typo in qemu-options.hx
>
>
Applied, thanks.
Please upd
-13 13:44:17
> +)
>
> are available in the Git repository at:
>
> https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20230314
>
> for you to fetch changes up to 0d581506de803204c5a321100afa270573382932:
>
> Fix incorrect register name in disassembler for
Am 14.03.23 um 12:50 schrieb Dorinda Bassey:
Hi Volker,
Thank you for the clarification. I see the problem now.
So is it safe to say that:
@@ -104,8 +104,9 @@ playback_on_process(void *data)
/* calculate the total no of bytes to read data from buffer */
req = b->requested *
> -Original Message-
> From: Taylor Simpson
> Sent: Dienstag, 14. März 2023 18:54
> To: Marco Liebel (QUIC) ; qemu-
> de...@nongnu.org
> Subject: RE: [PATCH] Use f-strings in python scripts
>
>
>
> > -Original Message-
> > From: Marco Liebel (QUIC)
> > Sent: Monday, March 13,
On 3/14/23 18:30, Cornelia Huck wrote:
Add 8.1 machine types for arm/i440fx/m68k/q35/s390x/spapr.
Signed-off-by: Cornelia Huck
For ppc,
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
hw/arm/virt.c | 9 -
hw/core/machine.c | 3 +++
hw/i386/pc.c
On 3/14/23 09:49, Daniel Henrique Barboza wrote:
All these generic CPUs are using the latest priv available, at this
moment PRIV_VERSION_1_12_0:
- riscv_any_cpu_init()
- rv32_base_cpu_init()
- rv64_base_cpu_init()
- rv128_base_cpu_init()
Create a new PRIV_VERSION_LATEST enum and use it in
On Tue, Mar 14, 2023 at 6:08 PM Peter Maydell
wrote:
> The cadence UART attempts to avoid allowing the guset to set invalid
> baud rate register values in the uart_write() function. However it
> does the "mask to the size of the register field" and "check for
> invalid values" in the wrong
Am 03.02.2023 um 14:17 hat Emanuele Giuseppe Esposito geschrieben:
> Just remove some AioContext lock in LinuxAioState and ThreadPool.
> Not related to anything specific, so I decided to send it as
> a separate patch.
>
> These patches are taken from Paolo's old draft series.
Thanks, applied to
From: Markus Armbruster
Ben is no longer with intel. He told me he expected to get back to
CXL, but it's not happening as quickly as he'd like, and that it's
best to remove him as maintainer. So let's do that.
Thank you for serving as maintainer, Ben!
Signed-off-by: Markus Armbruster
On 3/13/23 16:38, Ilya Leoshkevich wrote:
The code uses the wrong base for relative addressing: it should use the
target instruction address and not the EXECUTE's address.
Fix by storing the target instruction address in the new CPUS390XState
member and loading it from the code generated by
From: Damien Hedde
Also update mailmap
Signed-off-by: Damien Hedde
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Luc Michel
Message-Id: <20230213105227.2357-1-damien.he...@dahe.fr>
Signed-off-by: Laurent Vivier
---
.mailmap| 1 +
MAINTAINERS | 2 +-
2 files changed, 2 insertions(+),
The 03/03/2023 15:09, Jonathan Cameron wrote:
> Very simple implementation to allow testing of corresponding
> kernel code. Note that for now we track each 64 byte section
> independently. Whilst a valid implementation choice, it may
> make sense to fuse entries so as to prove out more complex
>
I am currently developing tests under avocado to help debugging.
And... it helps.
There is a bug here in s390_topology_set_cpus_entitlement for dedicated
CPUs.
On 3/9/23 13:15, Pierre Morel wrote:
[...]
--- a/hw/s390x/cpu-topology.c
+++ b/hw/s390x/cpu-topology.c
@@ -87,6 +87,84 @@ static
On 3/14/23 04:00, Ilya Leoshkevich wrote:
Generate specification exception if a reserved bit is set in the PSW
mask or if the PSW address is out of bounds dictated by the addresing
mode.
Reported-by: Nina Schoetterl-Glausch
Signed-off-by: Ilya Leoshkevich
---
target/s390x/cpu.c |
On Tue, Mar 14, 2023 at 10:11:53AM +, Dr. David Alan Gilbert wrote:
> OK, I think I kind of see what's happening here, one for Peter Xu.
> If I'm right it's a race something like:
> a) The test harness tells the source it wants to enter postcopy
> b) The harness then waits for the source
On 14/03/2023 14.33, Peter Maydell wrote:
The postcopy/preempt tests seem to have a race which makes them hang
on the s390x CI runner. Disable them for the moment, while we
investigate. As with the other disabled subtest, you can opt back in
by setting QEMU_TEST_FLAKY_TESTS=1 in your
On Mon, 13 Mar 2023 at 18:59, Richard Henderson
wrote:
>
> Version 3 fixes a rebase error from v2 affecting ARM BFC insn.
>
>
> r~
>
>
> The following changes since commit 29c8a9e31a982874ce4e2c15f2bf82d5f8dc3517:
>
> Merge tag 'linux-user-for-8.0-pull-request' of
>
The 03/03/2023 15:09, Jonathan Cameron wrote:
> Inject poison using qmp command cxl-inject-poison to add an entry to the
> poison list.
>
> For now, the poison is not returned CXL.mem reads, but only via the
> mailbox command Get Poison List.
>
> See CXL rev 3.0, sec 8.2.9.8.4.1 Get Poison list
We're now ready to split riscv_cpu_validate_set_extensions() in two.
None of these steps are going to touch env->misa_ext*.
riscv_cpu_validate_extensions() will take care of all validations based
on cpu->cfg values. cpu->cfg changes that are required for the
validation are being tolerated here.
write_misa() is able to use the same validation workflow
riscv_cpu_realize() uses. But it's still not capable of updating
cpu->cfg misa props yet.
We have no way of blocking future (and current) code from checking
env->misa_ext (via riscv_has_ext()) or reading cpu->cfg directly, so our
best
All these generic CPUs are using the latest priv available, at this
moment PRIV_VERSION_1_12_0:
- riscv_any_cpu_init()
- rv32_base_cpu_init()
- rv64_base_cpu_init()
- rv128_base_cpu_init()
Create a new PRIV_VERSION_LATEST enum and use it in those cases. I'll
make it easier to update everything
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