LTTng 2.0 Userspace Tracer (development files)
ii liblttng-ust0 2.0.2-0ubuntu1
LTTng 2.0 Userspace Tracer (libraries)
--
Alex Bennée
this as I was testing my Travis patches. Perhaps the .gitmodules should
always refer to the canonical upstream repo?
--
Alex Bennée
7149af13dd5600b27dac90235e60ff91d0468636
Author: Alex Bennée a...@bennee.com
Date: Tue Oct 1 16:51:38 2013 +0100
.gitmodules: use upstream SeaBIOS repo to fix submodule init
Currently master is broken as the wanted commit doesn't exist in
qemu's mirror of SeaBIOS.
diff --git a/.gitmodules
l...@redhat.com writes:
On 10/01/2013 04:37 PM, Alex Bennée wrote:
l...@redhat.com writes:
Hello:
In the daily qemu.git autotest run, I started to see the following
problem while checking out the qemu.git tree and checking out the
submodules:
Oh I just noticed that. Is this Stefan's
peter.mayd...@linaro.org writes:
On 3 October 2013 17:58, alex.ben...@linaro.org wrote:
From: Alex Bennée a...@bennee.com
Currently master is broken as the wanted commit doesn't exist in
qemu's mirror of SeaBIOS.
snip
This is wrong. QEMU's submodules should all point to
git.qemu.org
constant is used
twice and should it ever be changed there is a risk of one being missed
(although conceivably thumb encoding could be different?).
I appreciate the disassembler code is already a mass of magic constants
so it's not a major thing for me.
Cheers,
--
Alex Bennée
r...@twiddle.net writes:
There are free scheduling slots between the sequence of
comparison instructions. This requires changing the
register in use to avoid conflict with those compares.
Signed-off-by: Richard Henderson r...@twiddle.net
snip
Looks good to me.
Reviewed-by: Alex Bennée
r...@twiddle.net writes:
One of the two constraints we already checked via #if, but
the tlb offset distance was only checked at runtime.
Signed-off-by: Richard Henderson r...@twiddle.net
snip
Reviewed-by: Alex Bennée a...@bennee.com
--
Alex Bennée
Reviewed-by: Alex Bennée a...@bennee.com
--
Alex Bennée
.. Perhaps a few simple
examples could be added to the document so people can at least confirm
everything is working as it should be. Otherwise I'm happy.
Reviewed-by: Alex Bennée a...@bennee.com
Mohamad
Mohamad Gebai (3):
Fix configure script for LTTng 2.x
Modified the tracetool framework
with the following error:
snip
Isn't this the sort of think Make dependencies are for?
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Alex Bennée
probes but has only been tested with
--
Alex Bennée
peter.mayd...@linaro.org writes:
On 16 September 2013 13:50, alex.ben...@linaro.org wrote:
From: Alex Bennée a...@bennee.com
Commit 9b8c69243 broke the ability to boot the kernel as the value
returned by unassigned_mem_read returned non-zero and left the kernel
looping forever waiting
/distro specific?
--
Alex Bennée
to avoid getting a warning.
Signed-off-by: Mohamad Gebai mohamad.ge...@polymtl.ca
snip
Reviewed-by: Alex Bennée a...@bennee.com
--
Alex Bennée
-by: Alex Bennée a...@bennee.com
--
Alex Bennée
worth.
Reviewed-by: Alex Bennée a...@bennee.com
--
Alex Bennée
mohamad.ge...@gmail.com writes:
Signed-off-by: Mohamad Gebai mohamad.ge...@polymtl.ca
snip
Reviewed-by: Alex Bennée a...@bennee.com
--
Alex Bennée
if there is no special config for a given build target?
--
Alex Bennée
all these shim calls?
--
Alex Bennée
] = retval2;
+}
It's a shame ARM hasn't got some un-ambigious #define's for registers
snip
More #if 0's
+#if 0
+case EXCP0B_NOSEG:
+case EXCP0C_STACK:
snip
--
Alex Bennée
mohamad.ge...@polymtl.ca writes:
On 13-10-16 08:05 AM, Alex Bennée wrote:
Running this gives me:
quote
UST events:
-
None
/quote
Before or after running qemu. What is the mechanism lttng expects to
find out all these events?
Either the user should belong the group tracing
changes up to 90878d2c083629a4ee99b2d03158838b35e218c3:
.travis.yml | 69 +
1 file changed, 69 insertions(+)
create mode 100644 .travis.yml
Alex Bennée (1):
.travis.yml
From: Alex Bennée a...@bennee.com
Commit 9b8c69243 broke the ability to boot the kernel as the value
returned by unassigned_mem_read returned non-zero and left the kernel
looping forever waiting for it to change (see integrator_led_set in
the kernel code).
Relying on a varying implementation
peter.mayd...@linaro.org writes:
On 17 October 2013 17:12, Alex Bennée alex.ben...@linaro.org wrote:
From: Alex Bennée a...@bennee.com
Commit 9b8c69243 broke the ability to boot the kernel as the value
snip
Commit message, comment, overlength lines, lack of Copyright line
still all
mohamad.ge...@gmail.com writes:
Version 4
* Update documentation
Good stuff. I notice you haven't added my Reviewed-by tags to your
commits. See http://wiki.qemu.org/Contribute/SubmitAPatch.
Anyway it all looks good to me.
Reviewed-by: Alex Bennée a...@bennee.com
--
Alex Bennée
something?
Nope, I obviously had thoughts of tracking the actual LED/Switch state
and never added it in.
+} IntegratorDebugState;
Looks good otherwise.
thanks
-- PMM
--
Alex Bennée
peter.mayd...@linaro.org writes:
On 18 October 2013 12:45, alex.ben...@linaro.org wrote:
From: Alex Bennée a...@bennee.com
Commit 9b8c69243 (since reverted) broke the ability to boot the kernel
as the value returned by unassigned_mem_read returned non-zero and left
the kernel looping
it until the next event it has to deal with.
--
Alex Bennée
targets need to be built somehow.
Cheers,
--
Alex Bennée
peter.mayd...@linaro.org writes:
Our rules.mak adds '-rR' to MAKEFLAGS to indicate that we will be
explicitly specifying everything and not relying on any default
variables or rules.
s/sowe/so we/
Otherwise good.
Reviewed-by: Alex Bennée a...@bennee.com
--
Alex Bennée
?
On my 12.04 system (with the lttng PPA) it works fine:
$pkg-config --libs lttng-ust
-llttng-ust -ldl
$pkg-config --cflags lttng-ust
-I/usr/include/x86_64-linux-gnu
Is there a bug raised with the Ubuntu upstream to fix their stable LTTNG
package?
--
Alex Bennée
tests depending on Cross Compile support.
--
Alex Bennée
mohamad.ge...@gmail.com writes:
Signed-off-by: Mohamad Gebai mohamad.ge...@polymtl.ca
All looks good to me now.
Reviewed-by: Alex Bennée a...@bennee.com
--
Alex Bennée
these
softfloat functions against unintentional breakage? It would certainly
be worthwhile as soon as multiple arches use these functions as float
errors are often subtle and hard to track down.
--
Alex Bennée
peter.mayd...@linaro.org writes:
On 25 October 2013 12:34, Alex Bennée alex.ben...@linaro.org wrote:
Is it worth adding some sort of test into make check to defend these
softfloat functions against unintentional breakage? It would certainly
be worthwhile as soon as multiple arches use
mohamad.ge...@gmail.com writes:
Signed-off-by: Mohamad Gebai mohamad.ge...@polymtl.ca
---
snip
Tested on Ubuntu 12.04 with and without the LTTNG PPA and seems to work
well enough.
Reviewed-by: Alex Bennée a...@bennee.com
--
Alex Bennée
mohamad.ge...@polymtl.ca writes:
Signed-off-by: Mohamad Gebai mohamad.ge...@polymtl.ca
---
snip
Tested on Ubuntu 12.04 with and without the LTTNG PPA and seems to work
well enough.
Reviewed-by: Alex Bennée a...@bennee.com
Yes, the bug is actually only in the Ubuntu package (missing
these unused fields. I've done so
and added that slightly-edited patch to target-arm.next.
Doh, sorry about that. Thanks.
thanks
-- PMM
--
Alex Bennée
of issues while
building. They are mostly -Werror bits and pieces which I can work
through but as it doesn't build with the default QEMU build options I
thought I'd better check if that is the correct latest/greatest version
of the patch set.
Regards,
--
Alex Bennée
peter.mayd...@linaro.org writes:
On 29 October 2013 18:20, Alex Bennée alex.ben...@linaro.org wrote:
I'm currently at Linaro Connect and am looking at running the arm64
stuff through Peter's risu tool and getting an idea of the instruction
coverage. Alex pointed me to:
https://github.com
stefa...@gmail.com writes:
Looks useful. To get more code coverage, flesh out the build
environment:
Thanks. Am I dreaming or are there some system image tests somewhere as well?
--
Alex Bennée
afaer...@suse.de writes:
Am 18.09.2013 16:31, schrieb alex.ben...@linaro.org:
Looks okay in general, some minor nits below:
Thanks, I shall hopefully get those sorted out in the next week.
--
Alex Bennée
stefa...@gmail.com writes:
On Wed, Sep 18, 2013 at 03:35:07PM +0100, Alex Bennée wrote:
stefa...@gmail.com writes:
Looks useful. To get more code coverage, flesh out the build
environment:
Thanks. Am I dreaming or are there some system image tests somewhere as well?
Anthony
;-)
I'm currently pondering what the best way of supporting system images
(i.e. kernel+rootfs) would be to make system regression testing easier.
Unfortunately those images would be far too large to carry in the repo
although there may be some sub-module annex type thing I could try.
--
Alex Bennée
kw...@redhat.com writes:
Am 20.09.2013 um 11:10 hat Alex Bennée geschrieben:
jc...@redhat.com writes:
snip
I'm currently pondering what the best way of supporting system images
(i.e. kernel+rootfs) would be to make system regression testing easier.
Unfortunately those images would
your use case is? Aside from an exercise in
porting I don't know what else is to gain from going to NaCL. That's no
reason not to try of course!
--
Alex Bennée
the Travis tests
then the branch should probably not be merged.
--
Alex Bennée
stefa...@redhat.com writes:
On Mon, Sep 23, 2013 at 05:07:30PM +0100, alex.ben...@linaro.org wrote:
From: Alex Bennée a...@bennee.com
This only showed up when compiling with
--enable-trace-backend=stderr|ftrace at which point the compiler
complains with the following:
nsip
Stefan Weil
of stable API. I hunted around a
bit trying to get it working but realised the script needs fixing up as
well so gave up.
Really ust just needs to be ripped out for now unless someone else wants
to dig into to supporting multiple versions painlessly.
--
Alex Bennée
by: Alex Bennée a...@bennee.com
--
Alex Bennée
aren't to be used else where?
snip
--
Alex Bennée
to this or can it be merged into your maintainer tree?
--
Alex Bennée
munging is common
is there not an argument for having a common header for this case?
--
Alex Bennée
petar.jovano...@imgtec.com writes:
From: Alex Bennée [alex.ben...@linaro.org]
snip
There is an awful lot of similarity between a lot of the structures
while not being totally identical. Given the syscall munging is common
is there not an argument
time I ran it I found it had regressed also ;-)
--
Alex Bennée
?
--
Alex Bennée
patch has been started during Linaro Connect
by me and Alex Bennee.
snip
With the proviso of Richard's decode comment you can add:
Reviewed-by: Alex Bennée a...@bennee.com
Signed-of-by: Alex Bennée a...@bennee.com
--
Alex Bennée
should probably
warn the user about that.
--
Alex Bennée
(register) canonical for ORR (rn=31 shift_amount=0), and
MVN
(register) canonical for ORN (rn=31 shift_amount=0), and both therefore
also
worth a special case?
I suspect I'm being overly cheeky to expect the optimiser to detect and
optimise for that case as the ZR is a const ;-)
Cheers,
--
Alex
to do some performance analysis and come up with
some numbers before you made that assumption.
Cheers,
--
Alex Bennée
QEMU/KVM Hacker for Linaro
thought Xin was talking about caching translations between invocations
of QEMU.
I suspect address space randomisation would be another wrinkle in the
side of any such scheme though.
thanks
-- PMM
--
Alex Bennée
QEMU/KVM Hacker for Linaro
ldst patches did get a little gnarly thanks to the
structure of the original decoder and I wanted to avoid things like imm
fields being optionally chopped apart depending on the decode.
--
Alex Bennée
QEMU/KVM Hacker for Linaro
better as
tcg_gen_addi_i64(tcg_addr, tcg_addr,
(postindex ? offset : 0) - (1 size));
I'm not so sure it's easier to follow despite my general proclivity for
ternary operator.
?
r~
--
Alex Bennée
QEMU/KVM Hacker for Linaro
r...@twiddle.net writes:
On 12/09/2013 10:12 AM, Peter Maydell wrote:
From: Alex Bennée alex.ben...@linaro.org
snip
+static TCGv_i64 read_cpu_reg_sp(DisasContext *s, int reg, int sf)
+{
+TCGv_i64 v = new_tmp_a64(s);
+if (sf) {
+tcg_gen_mov_i64(v, cpu_X[reg
r...@twiddle.net writes:
On 12/09/2013 10:12 AM, Peter Maydell wrote:
From: Alex Bennée alex.ben...@linaro.org
This adds support for the load/store forms using a register offset.
snip
+/*
+ * C3.3.10 Load/store (register offset)
+ *
+ * 31 30 29 27 26 25 24 23 22 21 20 16 15 13
r...@twiddle.net writes:
On 12/10/2013 05:59 AM, Alex Bennée wrote:
+if (extend is_signed) {
+g_assert(size 3);
+tcg_gen_ext32u_i64(dest, dest);
+}
Is it worth noticing in size==2 !extend that is_signed can be forced
false
to avoid the extra extension
to issue a warning (when not --quiet) when it detects
creation of an image on a partition where performance may not be as
expected due to COW behaviour.
Cheers,
--
Alex Bennée
QEMU/KVM Hacker for Linaro
the information?
The hard dependency on glib has been in quite some time
(e18df14185e817ba735bce57ecdef9a55fb3d093) so I don't think you can
build without it.
However it should be possible to build glib for android and bundle it
with your qemu if needed.
Thanks,
Tervel
--
Alex Bennée
QEMU/KVM
r...@twiddle.net writes:
On 12/10/2013 06:16 AM, Alex Bennée wrote:
However my preference unless there is a strong objection would be to
clean that up in later patches. For one thing the more instructions each
patch handles the longer it takes to run the instruction validation on
the rather
catch. I suspect it never hits though (or risu doesn't generate
enough unallocated versions).
--
Alex Bennée
QEMU/KVM Hacker for Linaro
-memidx);
+tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx-memidx, MO_TEUL);
tcg_temp_free(addr);
snip
There seems to be a fix of tabs and spaces in that patch.
--
Alex Bennée
QEMU/KVM Hacker for Linaro
,then Service Hooks and selecting Travis.
Basically you just need to go to http://travis-ci.org and click the
Sign in with GitHub link and your up and running. It's super easy.
--
Alex Bennée
QEMU/KVM Hacker for Linaro
peter.mayd...@linaro.org writes:
On 18 December 2013 11:32, Alex Bennée alex.ben...@linaro.org wrote:
Now we have a .travis.yml merged into master can we enable Travis to run
in the QEMU mirror on github (https://github.com/qemu/qemu)? I'm happy
to talk who ever controls that repo through
Peter Maydell writes:
On 24 July 2014 16:52, Alex Bennée alex.ben...@linaro.org wrote:
+/* See: D4.7.2 TLB maintenance requirements and the TLB maintenance
instructions
+ * Page D4-1736 (DDI0487A.b) For TLB maintenance instructions that
+ * take an address, the maintenance of VA[63:56
/path/to/unique/file/name.log
Or am I misunderstanding what you want?
--
Alex Bennée
their config
include arm-softmmu.mak
# we explicitly disable ones that require old ARMv5 support
CONFIG_ARMV5_BOARDS=n
Signed-off-by: Alex Bennée alex.ben...@linaro.org
diff --git a/scripts/make_device_config.sh b/scripts/make_device_config.sh
index 7242707..b0d0b51 100644
--- a/scripts
Hi,
Not too much has changed:
* added a review tag
* fixed up review comments
* added some notes about benchmark results
* added a patch to disable ARMv5 in AArch64 build
The most important thing is I've measured a 25-30% improvement in
kernel and android boot time.
Alex Bennée (5
.
Signed-off-by: Alex Bennée alex.ben...@linaro.org
---
v2:
- fix AArch64 references
- add benchmark notes to commit msg
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index c83f249..83df513 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -1051,11 +1051,18 @@ bool
According to the ARM ARM we weren't correctly flushing the TLB entries
where bits 63:56 didn't match bit 55 of the virtual address. This
exposed a problem when we switched QEMU's internal TARGET_PAGE_BITS to
12 for aarch64.
Signed-off-by: Alex Bennée alex.ben...@linaro.org
Reviewed-by: Peter
If you attempt to run a system image which uses 1k pages in the
qemu-system-aarch64 build it will fail thanks to the change to 12 bit
pages. The boards are still available for the qemu-system-arm build.
Signed-off-by: Alex Bennée alex.ben...@linaro.org
diff --git a/default-configs/aarch64
Otherwise we break quickly when we change TARGET_PAGE_SIZE.
Signed-off-by: Alex Bennée alex.ben...@linaro.org
diff --git a/target-arm/helper.c b/target-arm/helper.c
index a0e57cd..aa5d267 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -4029,8 +4029,8 @@ int
When debugging stuff that occurs over several forks it would be useful
not to keep overwriting the one logfile you've set-up. This allows a
simple %d to be included once in the logfile parameter which is
substituted with getpid().
Signed-off-by: Alex Bennée alex.ben...@linaro.org
Reviewed
This allows the perf tool to map samples to each individual translation
block. This could be expanded for user space but currently it gives
enough information to find any hotblocks by other means.
Signed-off-by: Alex Bennée alex.ben...@linaro.org
---
v2:
- hoist up into translate-all.c
Each individual architecture needs to use the qemu_log_in_addr_range()
feature for enabling in_asm and marking blocks for op/opt_op output.
Signed-off-by: Alex Bennée alex.ben...@linaro.org
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index 33b5025..56b8534 100644
-0x9000,0xffc8+0x200,...
Then logging code can use the new qemu_log_in_addr_range() function to
decide if it will output logging information for the given range.
Signed-off-by: Alex Bennée alex.ben...@linaro.org
v2
- More clean-ups to the documentation
v3
- re-base
- use GArray
This ensures the code generation debug code will honour -dfilter if set.
For the exec tracing I've added a new inline macro for efficiency's
sake. I've not touched CPU_LOG_TB_OP as this is buried in each
individual target.
Signed-off-by: Alex Bennée alex.ben...@linaro.org
v2
This doesn't just dump CPU state on translation but on every block
entrance.
Signed-off-by: Alex Bennée alex.ben...@linaro.org
diff --git a/qemu-log.c b/qemu-log.c
index 797f2af..35bbb56 100644
--- a/qemu-log.c
+++ b/qemu-log.c
@@ -105,7 +105,7 @@ const QEMULogItem qemu_log_items
to compliment the tc_ptr (and the subject pc,
block size). This is set on code generation and then accessed directly
by all the people that need it.
I've also cleaned up some comments and removed un-used return variables.
Signed-off-by: Alex Bennée alex.ben...@linaro.org
---
v1
- checkpatch fixes
diff
chain flag
- move perf.map stuff up into translate-all.c
- include prolog/epilog in the perf.map dump
- include tc_size in TranslationBlock
- cleaned up documentation of the -dfilter params
- used GArray instead of GList for debug_regions
Alex Bennée (7):
tcg: add ability to dump /tmp
From: Peter Maydell peter.mayd...@linaro.org
Make qemu_log_mask() a macro which only calls the function to
do the actual work if the logging is enabled. This avoids making
a function call in possible fast paths where logging is disabled.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
[ffcdce70]
Trace 0x7fb7cc8235d0 [ffcdce70]
Abandoned execution of TB chain before 0x7fb7cc8235d0 [ffcdce70]
Trace 0x7fb7cc8235d0 [ffcdce70]
Trace 0x7fb7cc822fd0 [ffcdd52c]
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
Signed-off-by: Alex Bennée alex.ben...@linaro.org
the glue magic (not your fault
;-) we have in QEMU. However wouldn't it be simpler for the helper
pre-amble code to ensure the subject pc is updated in the CPU
environment?
Can QEMU only rectify the processor state from a TranlationBlock tc address?
--
Alex Bennée
);
cpu_watchpoint_remove_all(cs, BP_CPU);
--
Alex Bennée
{
+replay_state.skipping_instruction = 1;
+}
I'm not quite following what instructions_count means here. Is it an
actual count of instructions executed? Can you add a comment to the
header where it's defined?
--
Alex Bennée
Alex Bennée writes:
This makes the UST backend pay attention to the format string arguments
that are defined when defining payload data. With this you can now
ensure integers are reported in hex mode if you want.
snip
Ping Stefan, can this one at least be slurped up into your tracing tree
This makes the UST backend pay attention to the format string arguments
that are defined when defining payload data. With this you can now
ensure integers are reported in hex mode if you want.
Signed-off-by: Alex Bennée alex.ben...@linaro.org
---
v2
- remove silly debug statements
v3
- fix
complete tracing at the expense of
performance.
Signed-off-by: Alex Bennée alex.ben...@linaro.org
---
v2
- rebase
v3:
- checkpatch clean-ups
- add sign-off
- disable exec_tb by default
diff --git a/cpu-exec.c b/cpu-exec.c
index 38e5f02..d209568 100644
--- a/cpu-exec.c
+++ b/cpu-exec.c
Hi Stefan,
I've re-based these two on tracing-next. Otherwise now changes from
the last post.
Alex Bennée (2):
trace: teach lttng backend to use format strings
trace: add some tcg tracing support
cpu-exec.c | 6 ++
scripts/tracetool/__init__.py
Hi Stefan,
As v3 posted earlier today but with a format string fix which didn't
show up in the ust build I tested it on
Alex Bennée (2):
trace: teach lttng backend to use format strings
trace: add some tcg tracing support
cpu-exec.c | 6 ++
scripts
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