[Qemu-devel] [Bug 1243287] Re: [KVM/QEMU][ARM][SAUCY] fails to boot cloud-image due to host kvm fail

Peter, the config option is called: CONFIG_STRICT_DEVMEM And /dev/mem behaves differently between doing read() and doing mmap(). As Peter already hinted, the memory layout is different on native Midway (which has DRAM starting at 0) and mach-virt/vexpress (which start at 128MB / 2GB

[Qemu-devel] [PATCH v2 0/2] add initial Calxeda Midway A15 support

Herring rob.herr...@calxeda.com. Signed-off-by: Andre Przywara andre.przyw...@calxeda.com Andre Przywara (2): ARM/highbank: prepare for adding similar machines ARM/highbank: add support for Calxeda ECX-2000 / Midway hw/arm/highbank.c | 61

[Qemu-devel] [PATCH v2 1/2] ARM/highbank: prepare for adding similar machines

To allow the modelling of machines similar to Calxeda Highbank, introduce a parameter to the init function and call it from a wrapper. This allows to tweak the definition for individual machines later on. Signed-off-by: Andre Przywara andre.przyw...@calxeda.com --- hw/arm/highbank.c | 29

[Qemu-devel] [PATCH v2 2/2] ARM/highbank: add support for Calxeda ECX-2000 / Midway

specific part, since Midway does not have (and need) it. Signed-off-by: Andre Przywara andre.przyw...@calxeda.com --- hw/arm/highbank.c | 32 +++- 1 file changed, 27 insertions(+), 5 deletions(-) diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c index 2c32a2b..3c99a81

[Qemu-devel] [PATCH] highbank: add initial Calxeda Midway A15 support

. The use of: -M highbank -cpu cortex-a15 simply gives the new chip without the need for a new model. Signed-off-by: Rob Herring rob.herr...@calxeda.com Signed-off-by: Andre Przywara andre.przyw...@calxeda.com --- hw/arm/highbank.c | 19 +-- 1 file changed, 13 insertions(+), 6

Re: [Qemu-devel] [PATCH arm-devs v2 8/8] arm/highbank.c: Fix MPCore periphbase name

On 11/28/2013 08:41 PM, Peter Maydell wrote: (CCing Rob) On 28 November 2013 03:31, Peter Crosthwaite peter.crosthwa...@xilinx.com wrote: GIC_BASE_ADDR is not the base address of the GIC. Its clear from the code that this is the base address of the MPCore. Rename to MPCORE_PERIPHBASE

[Qemu-devel] [PATCH] kvm/x86: enlarge number of possible CPUID leaves

Currently the number of CPUID leaves KVM handles is limited to 40. My desktop machine (AthlonII) already has 35 and future CPUs will expand this well beyond the limit. Extend the limit to 80 to make room for future processors. Signed-off-by: Andre Przywara andre.przyw...@amd.com --- arch/x86

[Qemu-devel] Re: [PATCH] kvm/x86: enlarge number of possible CPUID leaves

Avi Kivity wrote: On 12/01/2010 01:17 PM, Andre Przywara wrote: Currently the number of CPUID leaves KVM handles is limited to 40. My desktop machine (AthlonII) already has 35 and future CPUs will expand this well beyond the limit. Extend the limit to 80 to make room for future processors

[Qemu-devel] Re: [PATCH] kvm/x86: enlarge number of possible CPUID leaves

KVM handles is limited to 40. My desktop machine (AthlonII) already has 35 and future CPUs will expand this well beyond the limit. Extend the limit to 80 to make room for future processors. Signed-off-by: Andre Przywara andre.przyw...@amd.com --- arch/x86/include/asm/kvm_host.h |2 +- 1 files

Re: [Qemu-devel] [RFC] Bug Day - June 1st, 2010

Michael Tokarev wrote: ... Also, thanks to Andre Przywara, whole winNT thing works but it requires -cpu qemu64,level=1 (or level=2 or =3), -- _not_ with default CPU. This is also testing, but it's not obvious what to do witht the result... Can't we use the file based CPU models

[Qemu-devel] [Bug 267542] Re: MINIX 3 won't boot in qemu 0.9.1

Is that still a problem? What was the exact error? I quickly tried the 3.1.2a on qemu 0.12.4 (with and without KVM) and I could easily login. ** Changed in: qemu Status: New = Incomplete -- MINIX 3 won't boot in qemu 0.9.1 https://bugs.launchpad.net/bugs/267542 You received this bug

Re: [Qemu-devel] [RFC] Bug Day - June 1st, 2010

Michael Tokarev wrote: 20.05.2010 02:30, Anthony Liguori wrote: On 05/19/2010 05:29 PM, Andre Przywara wrote: Michael Tokarev wrote: ... Also, thanks to Andre Przywara, whole winNT thing works but it requires -cpu qemu64,level=1 (or level=2 or =3), -- _not_ with default CPU. This [] It'd

[Qemu-devel] [PATCH] resent: fix CPUID vendor override

is to propagate the host's vendor - when explicitly requested via -cpu base,vendor=xxx obey this and use the specified vendor Signed-off-by: Andre Przywara andre.przyw...@amd.com --- target-i386/cpuid.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) Hi, this hasn't been picked

[Qemu-devel] [PATCH] resent: x86/cpuid: Add kvm32 CPU model

Create a kvm32 CPU model that describes a least common denominator for KVM capable guest CPUs. Useful for migration purposes. Signed-off-by: Andre Przywara andre.przyw...@amd.com --- target-i386/cpuid.c | 14 ++ 1 files changed, 14 insertions(+), 0 deletions(-) diff --git a/target

[Qemu-devel] [PATCH] resent: x86/cpuid: propagate further CPUID leafs when -cpu host

-cpu host currently only propagates the CPU's family/model/stepping, the brand name and the feature bits. Add a whitelist of safe CPUID leafs to let the guest see the actual CPU's cache details and other things. Signed-off-by: Andre Przywara andre.przyw...@amd.com --- target-i386/cpu.h |6

Re: [Qemu-devel] [PATCH] resent: x86/cpuid: propagate further CPUID leafs when -cpu host

Anthony Liguori wrote: On 05/21/2010 02:50 AM, Andre Przywara wrote: -cpu host currently only propagates the CPU's family/model/stepping, the brand name and the feature bits. Add a whitelist of safe CPUID leafs to let the guest see the actual CPU's cache details and other things. Signed-off

Re: [Qemu-devel] [PATCH] resent: x86/cpuid: propagate further CPUID leafs when -cpu host

Anthony Liguori wrote: On 05/25/2010 08:21 AM, Andre Przywara wrote: What's the benefit of exposing this information to the guest? That is mostly to propagate the cache size and organization parameters to the guest: +/* safe CPUID leafs to propagate to guest if -cpu host is specified

Re: [Qemu-devel] New Bitmap module ?

bitmap code, maybe you could leverage this (if not already done). Regards, Andre. -- Andre Przywara AMD-Operating System Research Center (OSRC), Dresden, Germany Tel: +49 351 448-3567-12 #ifndef __BITMAP_H__ #define __BITMAP_H__ #ifndef HOST_LONG_BITS #define HOST_LONG_BITS (sizeof(long) * 8

[Qemu-devel] Using Linux's CPUSET for KVM VCPUs

| +--/ kvm_guest_02 ... What do you think about it? It is worth implementing this? Regards, Andre. -- Andre Przywara AMD-Operating System Research Center (OSRC), Dresden, Germany Tel: +49 351 448-3567-12

Re: [Qemu-devel] cpuid problem in upstream qemu with kvm

-setup.c: #else /* CONFIG_X86_32 */ #define vdso32_sysenter() (boot_cpu_has(X86_FEATURE_SEP)) #define vdso32_syscall()(0) but that's probably minor compared to the cost of using emulated syscall on Intel hosts. Regards, Andre. -- Andre Przywara AMD-Operating System Research Center (OSRC

[Qemu-devel] [PATCH] osdep: Fix runtime failure on older Linux kernels

and returns the rather unspecific qemu_init_main_loop failed. This patch fixes this by checking the return values of these calls for EINVAL and ENOSYS and falling back to the older versions automatically. Signed-off-by: Andre Przywara andre.przyw...@amd.com --- osdep.c | 18 -- 1

Re: [Qemu-devel] [PATCH] osdep: Fix runtime failure on older Linux kernels

are. This was the untested part, because my glibc didn't have accept4. I only saw the SOCK_CLOEXEC name on this... Fixed patch follows... Regards, Andre. -- Andre Przywara AMD-OSRC (Dresden) Tel: x29712

[Qemu-devel] [PATCH v2] osdep: Fix runtime failure on older Linux kernels

and returns the rather unspecific qemu_init_main_loop failed. This patch fixes this by checking the return values of these calls for EINVAL and ENOSYS and falling back to the older versions automatically. Signed-off-by: Andre Przywara andre.przyw...@amd.com --- osdep.c | 18 -- 1

Re: [Qemu-devel] Re: SVM support in 0.12?

please try: $ qemu -m 500 -cpu qemu32,+svm,vendor=AuthenticAMD -cdrom ubuntu.iso (because the default vendor for qemu32 is Intel, for qemu64 AMD) Regards, Andre. -- Andre Przywara AMD-Operating System Research Center (OSRC), Dresden, Germany Tel: +49 351 448 3567 12 to satisfy European Law

Re: [Qemu-devel] Re: SVM support in 0.12?

Andre Przywara wrote: Jun Koi wrote: I am running latest Qemu 0.12-rc. My guest VM runs Linux kernel 2.6.31. Because Qemu now supports SVM, I expect to see the SVM flag in /proc/cpuinfo, but that is not the case. So it seems SVM support is not enabled by default configuration?? My host

Re: [Qemu-devel] cpuid problem in upstream qemu with kvm

, Nehalem (and maybe Phenom). -- Andre Przywara AMD-Operating System Research Center (OSRC), Dresden, Germany Tel: +49 351 448 3567 12 to satisfy European Law for business letters: Advanced Micro Devices GmbH Karl-Hammerschmidt-Str. 34, 85609 Dornach b. Muenchen Geschaeftsfuehrer: Andrew Bowd

Re: [Qemu-devel] [PATCH] Add definitions for current cpu models..

/msg01228.html Resending this patch set is on my plan for next week. What is the state of this patch? Will it go in soon? Then I'd rebase my patch set on top of it. Regards, Andre. -- Andre Przywara AMD-OSRC (Dresden) Tel: x29712

[Qemu-devel] [PATCH 00/13] i386 cpuid: cleanup and fixes

Hi, first: I know that this conflicts with John Cooper's latest patch, but I want to send this out for review and to help merging the stuff. This patchset cleans up the CPUID handling code in QEMU. The biggest change is obviously the move of the CPUID function to a separate file (cpuid.c). This

[Qemu-devel] [PATCH 02/13] cpuid: replace magic number with named constant

CPUID leaf Fn8000_0001.EDX contains a copy of many Fn_0001.EDX bits. Define a name for the mask to improve readability and avoid typos. Signed-off-by: Andre Przywara andre.przyw...@amd.com --- target-i386/cpuid.c | 11 ++- 1 files changed, 6 insertions(+), 5 deletions(-) diff

[Qemu-devel] [PATCH 05/13] cpuid: add missing CPUID feature flag names

-by: Andre Przywara andre.przyw...@amd.com --- target-i386/cpuid.c | 15 --- 1 files changed, 8 insertions(+), 7 deletions(-) diff --git a/target-i386/cpuid.c b/target-i386/cpuid.c index 0238718..19d58e1 100644 --- a/target-i386/cpuid.c +++ b/target-i386/cpuid.c @@ -52,11 +52,11

[Qemu-devel] [PATCH 08/13] cpuid: simplify CPUID flag search function

avoid code duplication and handle the CPUID flag name search in a loop. Signed-off-by: Andre Przywara andre.przyw...@amd.com --- target-i386/cpuid.c | 38 +- 1 files changed, 13 insertions(+), 25 deletions(-) diff --git a/target-i386/cpuid.c b/target-i386

[Qemu-devel] [PATCH 11/13] cpuid: Always expose 32 and 64-bit CPUs

Since 64-bit capability is just another CPUID bit we now properly mask, there is no reason anymore to hide the 64-bit capable CPU models from a 32-bit only QEMU. All 64-bit CPUs can be used perfectly in 32-bit legacy mode anyway, so these models also make sense for 32-bit. Signed-off-by: Andre

[Qemu-devel] [PATCH 10/13] cpuid: add TCG feature bit trimming

In KVM we trim the user provided CPUID bits to match the host CPU's one. Introduce a similar feature to QEMU/TCG. Create a mask of TCG's capabilities and apply it to the user bits. This allows to let the CPU models reflect their native archetypes. Signed-off-by: Andre Przywara andre.przyw

[Qemu-devel] [PATCH 03/13] cpuid: moved host_cpuid function and remove prototype

the host_cpuid function was located at the end of the file and had a prototype before it's first use. Move it up and remove the prototype. Signed-off-by: Andre Przywara andre.przyw...@amd.com --- target-i386/cpuid.c | 70 -- 1 files changed, 34

[Qemu-devel] [PATCH 09/13] cpuid: propagate further CPUID leafs when -cpu host

-cpu host currently only propagates the CPU's family/model/stepping, the brand name and the feature bits. Add a whitelist of safe CPUID leafs to let the guest see the actual CPU's cache details and other things. Signed-off-by: Andre Przywara andre.przyw...@amd.com --- target-i386/cpu.h |5

[Qemu-devel] [PATCH 04/13] cpuid: Replace strtok with get_opt_name

, bit IMO the least intrusive and smallest one. Signed-off-by: Andre Przywara andre.przyw...@amd.com --- target-i386/cpuid.c | 34 -- 1 files changed, 24 insertions(+), 10 deletions(-) diff --git a/target-i386/cpuid.c b/target-i386/cpuid.c index cc080f4..0238718

[Qemu-devel] [PATCH 07/13] cpuid: remove unnecessary kvm_trim function

Correct me if I am wrong, but kvm_trim looks like a really bloated implementation of a bitwise AND. So remove this function and replace it with the real stuff(TM). Signed-off-by: Andre Przywara andre.przyw...@amd.com --- target-i386/kvm.c | 27 ++- 1 files changed, 6

[Qemu-devel] [PATCH 06/13] cpuid: list all known x86 CPUID feature flags

-cpu ? currently gives us a list of known CPU models. Add host if using KVM and a list of known CPUID feature flags to the output. Signed-off-by: Andre Przywara andre.przyw...@amd.com --- target-i386/cpuid.c | 22 +- 1 files changed, 21 insertions(+), 1 deletions(-) diff

[Qemu-devel] [PATCH 12/13] cpuid: Add kvm32 CPU model

Create a kvm32 CPU model that describes a least common denominator for KVM capable guest CPUs. Useful for migration purposes. Signed-off-by: Andre Przywara andre.przyw...@amd.com --- target-i386/cpuid.c | 14 ++ 1 files changed, 14 insertions(+), 0 deletions(-) diff --git a/target

[Qemu-devel] [PATCH 13/13] cpuid: fix CPUID levels

Bump up the xlevel number for qemu32 to allow parsing of the processor name string for this model. Similiarly the 486 processor should have at least the feature bit leaf enabled. Signed-off-by: Andre Przywara andre.przyw...@amd.com --- target-i386/cpuid.c |4 ++-- 1 files changed, 2

[Qemu-devel] Re: [PATCH] Add cpu model configuration support.. (resend)

. -- Andre Przywara AMD-Operating System Research Center (OSRC), Dresden, Germany Tel: +49 351 448 3567 12 to satisfy European Law for business letters: Advanced Micro Devices GmbH Karl-Hammerschmidt-Str. 34, 85609 Dornach b. Muenchen Geschaeftsfuehrer: Andrew Bowd; Thomas M. McCoy; Giuliano

[Qemu-devel] [PATCH v3] TCG x86: implement lzcnt emulation

when the operand is 0). lzcnt is guarded by the ABM CPUID bit (Fn8000_0001:ECX_5). Signed-off-by: Andre Przywara andre.przyw...@amd.com --- target-i386/helper.h|1 + target-i386/op_helper.c | 14 -- target-i386/translate.c | 37 + 3

[Qemu-devel] [FOR 0.12][PATCH] cpuid: Fix multicore setup on Intel

from both places and always get the real vendor. This fixes KVM's multicore setup on Intel CPUs. Signed-off-by: Andre Przywara andre.przyw...@amd.com Reported-by: Dietmar Maurer diet...@proxmox.com --- target-i386/helper.c | 46 +++--- 1 files changed, 31

[Qemu-devel] [FOR 0.12][PATCH] cpuid: Update QEMU/TCG feature set

are left out. Signed-off-by: Andre Przywara andre.przyw...@amd.com --- target-i386/helper.c | 25 - 1 files changed, 12 insertions(+), 13 deletions(-) diff --git a/target-i386/helper.c b/target-i386/helper.c index f0ecd50..f1ff577 100644 --- a/target-i386/helper.c +++ b

[Qemu-devel] [PATCH] configure: fix --sysconfdir specification

--sysconfdir requires a parameter (the path), this should be reflected in the case pattern. Reported-by: Frank Arnold frank.arn...@amd.com Signed-off-by: Andre Przywara andre.przyw...@amd.com --- configure |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/configure b

[Qemu-devel] [PATCH] install: honor DESTDIR on sysconfdir population

When creating and populating $sysconfdir, we should prepend $DESTDIR as we do with all other paths. Reported-by: Frank Arnold frank.arn...@amd.com Signed-off-by: Andre Przywara andre.przyw...@amd.com --- Makefile |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git

[Qemu-devel] [PATCH 03/13] x86/cpuid: fix missing feature set bits

This one was accidently removed with commit bb0300dc57c10b3721451b0ff566a03f9276cc77 Signed-off-by: Andre Przywara andre.przyw...@amd.com --- target-i386/cpuid.c |1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/target-i386/cpuid.c b/target-i386/cpuid.c index 5e4f057

[Qemu-devel] [PATCH 00/13] x86/cpuid: cleanups and fixes

Hi, a rebased and refined version of my CPUID cleanup series. This should now apply on top of git head. Compared to the last post this leaves out the bits already done by John Cooper's patch. Also I added a separate patch to deal with an accidently removed line (patch 3/13). This patchset cleans

[Qemu-devel] [PATCH 06/13] x86/cpuid: add host to the list of supported CPU models

Signed-off-by: Andre Przywara andre.przyw...@amd.com --- target-i386/cpuid.c |3 +++ 1 files changed, 3 insertions(+), 0 deletions(-) diff --git a/target-i386/cpuid.c b/target-i386/cpuid.c index 56ae71a..1e1c25b 100644 --- a/target-i386/cpuid.c +++ b/target-i386/cpuid.c @@ -757,6 +757,9

[Qemu-devel] [PATCH 08/13] x86/cpuid: propagate further CPUID leafs when -cpu host

-cpu host currently only propagates the CPU's family/model/stepping, the brand name and the feature bits. Add a whitelist of safe CPUID leafs to let the guest see the actual CPU's cache details and other things. Signed-off-by: Andre Przywara andre.przyw...@amd.com --- target-i386/cpu.h |6

[Qemu-devel] [PATCH 12/13] x86/cpuid: fix CPUID levels

Bump up the xlevel number for qemu32 to allow parsing of the processor name string for this model. Similiarly the 486 processor should have at least the feature bit leaf enabled. Signed-off-by: Andre Przywara andre.przyw...@amd.com --- target-i386/cpuid.c |4 ++-- 1 files changed, 2

[Qemu-devel] [PATCH 09/13] x86/cpuid: add TCG feature bit trimming

In KVM we trim the user provided CPUID bits to match the host CPU's one. Introduce a similar feature to QEMU/TCG. Create a mask of TCG's capabilities and apply it to the user bits. This allows to let the CPU models reflect their native archetypes. Signed-off-by: Andre Przywara andre.przyw

[Qemu-devel] [PATCH 04/13] x86/cpuid: moved host_cpuid function and remove prototype

the host_cpuid function was located at the end of the file and had a prototype before it's first use. Move it up and remove the prototype. Signed-off-by: Andre Przywara andre.przyw...@amd.com --- target-i386/cpuid.c | 71 -- 1 files changed, 34

[Qemu-devel] [PATCH 13/13] x86/cpuid: Update qemu64/32 CPU models

Since we now have a real TCG feature set, use it to describe the artificial qemu CPUs (both 64 and 32-bit). If new features are added to TCG, the capability of qemu64/32 will automatically be adjusted. Signed-off-by: Andre Przywara andre.przyw...@amd.com --- target-i386/cpuid.c | 25

[Qemu-devel] [PATCH 02/13] x86/cpuid: replace magic number with named constant

CPUID leaf Fn8000_0001.EDX contains a copy of many Fn_0001.EDX bits. Define a name for this mask to improve readability and avoid typos. Signed-off-by: Andre Przywara andre.przyw...@amd.com --- target-i386/cpuid.c | 11 ++- 1 files changed, 6 insertions(+), 5 deletions(-) diff

[Qemu-devel] [PATCH 07/13] x86/cpuid: remove unnecessary kvm_trim function

Correct me if I am wrong, but kvm_trim looks like a really bloated implementation of a bitwise AND. So remove this function and replace it with the real stuff(TM). Signed-off-by: Andre Przywara andre.przyw...@amd.com --- target-i386/kvm.c | 27 ++- 1 files changed, 6

[Qemu-devel] [PATCH 05/13] x86/cpuid: add missing CPUID feature flag names

-by: Andre Przywara andre.przyw...@amd.com --- target-i386/cpuid.c | 16 1 files changed, 8 insertions(+), 8 deletions(-) diff --git a/target-i386/cpuid.c b/target-i386/cpuid.c index fa36942..56ae71a 100644 --- a/target-i386/cpuid.c +++ b/target-i386/cpuid.c @@ -42,14 +42,14

[Qemu-devel] [PATCH 11/13] x86/cpuid: Add kvm32 CPU model

Create a kvm32 CPU model that describes a least common denominator for KVM capable guest CPUs. Useful for migration purposes. Signed-off-by: Andre Przywara andre.przyw...@amd.com --- target-i386/cpuid.c | 14 ++ 1 files changed, 14 insertions(+), 0 deletions(-) diff --git a/target

[Qemu-devel] tainted Linux kernel in default SMP QEMU/KVM guests

patches for all solutions, but I'd like to get advice from people on which one to pursue. Regards, Andre. -- Andre Przywara AMD-Operating System Research Center (OSRC), Dresden, Germany Tel: +49 351 448-3567-12

[Qemu-devel] Re: [PATCH][STABLE] fix CPUID vendor override

Avi Kivity wrote: On 04/11/2010 10:21 PM, Andre Przywara wrote: the meaning of vendor_override is actually the opposite of how it is currently used :-( Fix it to allow KVM to export the non-native CPUID vendor if explicitly requested by the user. Signed-off-by: Andre Przywaraandre.przyw

[Qemu-devel] [PATCH][STABLE] fix CPUID vendor override

the meaning of vendor_override is actually the opposite of how it is currently used :-( Fix it to allow KVM to export the non-native CPUID vendor if explicitly requested by the user. Signed-off-by: Andre Przywara andre.przyw...@amd.com --- target-i386/helper.c |2 +- 1 files changed, 1

[Qemu-devel] Re: [PATCH][STABLE] fix CPUID vendor override

Avi Kivity wrote: On 04/11/2010 10:21 PM, Andre Przywara wrote: the meaning of vendor_override is actually the opposite of how it is currently used :-( Fix it to allow KVM to export the non-native CPUID vendor if explicitly requested by the user. Signed-off-by: Andre Przywaraandre.przyw

[Qemu-devel] [PATCH] x86/cpuid: Add kvm32 CPU model

Create a kvm32 CPU model that describes a least common denominator for KVM capable guest CPUs. Useful for migration purposes. Signed-off-by: Andre Przywara andre.przyw...@amd.com --- target-i386/cpuid.c | 14 ++ 1 files changed, 14 insertions(+), 0 deletions(-) diff --git a/target

Re: [Qemu-devel] Re: [PATCH][STABLE] fix CPUID vendor override

Aurelien Jarno wrote: On Sun, Apr 11, 2010 at 09:49:40PM +0200, Andre Przywara wrote: Avi Kivity wrote: On 04/11/2010 10:21 PM, Andre Przywara wrote: the meaning of vendor_override is actually the opposite of how it is currently used :-( Fix it to allow KVM to export the non-native CPUID

Re: [Qemu-devel] [PATCH] fix gcc4 compile warnings

andrzej zaborowski wrote: On 30/11/2007, Andre Przywara [EMAIL PROTECTED] wrote: These casts are not the right way to get rid of the warnings, as are some of the casts in other files in qemu_put_* and qemu_get_* arguments. In this case the warnings are true positives and the bugs

Re: [Qemu-devel] [PATCH] fix gcc4 compile warnings

this and apply other parts of your patch when I find a bit of time. Thanks for that, if I can help you with some boring work, tell me ;-) Regards, Andre. -- Andre Przywara AMD-Operating System Research Center (OSRC), Dresden, Germany Tel: +49 351 277-84917 to satisfy European Law for business letters

[Qemu-devel] [PATCH 1/5] gcc4 warnings: fix wrong signedness

This fixes the signedness of some variables to fit the signedness of the functions called. -- Andre Przywara AMD-Operating System Research Center (OSRC), Dresden, Germany Tel: +49 351 277-84917 to satisfy European Law for business letters: AMD Saxony Limited Liability Company Co. KG

[Qemu-devel] [PATCH 2/5] gcc4 warnings: fix char* signedness

Text strings are char*, buffers are usually uint8_t*, sometimes both are mixed, casts are mostly necessary here. -- Andre Przywara AMD-Operating System Research Center (OSRC), Dresden, Germany Tel: +49 351 277-84917 to satisfy European Law for business letters: AMD Saxony Limited Liability

[Qemu-devel] [PATCH 0/5] fix various gcc4 compile warnings

* signedness 3/5: qemu_put signedness fixes 4/5: fix bdrv_get_geometry to return uint64_t 5/5: miscellaneous minor things Compared to my last work post I tried to avoid casting as much as possible, only patch 2/5 still uses them. Comments welcome. Regards, Andre. -- Andre Przywara AMD-OSRC

[Qemu-devel] [PATCH 5/5] gcc4 warnings: miscellaneous minor things

in hw/pcnet.c -- Andre Przywara AMD-Operating System Research Center (OSRC), Dresden, Germany Tel: +49 351 277-84917 to satisfy European Law for business letters: AMD Saxony Limited Liability Company Co. KG, Wilschdorfer Landstr. 101, 01109 Dresden, Germany Register Court Dresden: HRA 4896

[Qemu-devel] [PATCH 4/5] gcc4 warnings: fix bdrv_get_geometry to return uint64_t

bdrv_get_geometry never returns a negative number, so I changed the return type to unsigned, changes quite a lot of declarations. -- Andre Przywara AMD-Operating System Research Center (OSRC), Dresden, Germany Tel: +49 351 277-84917 to satisfy European Law for business letters: AMD Saxony

[Qemu-devel] [PATCH 3/5] gcc4 warnings: qemu_put signedness fixes

why only the pointer version was used throughout all files, so I expect some resistance here... -- Andre Przywara AMD-Operating System Research Center (OSRC), Dresden, Germany Tel: +49 351 277-84917 to satisfy European Law for business letters: AMD Saxony Limited Liability Company Co. KG

Re: [Qemu-devel] Re: [kvm-ppc-devel] The default for char Literals differ in signedness between platforms causing us a lot of warnings

/qemu-devel/2007-12/msg00420.html http://lists.gnu.org/archive/html/qemu-devel/2007-12/msg00448.html http://lists.gnu.org/archive/html/qemu-devel/2007-12/msg00452.html [4] Xen devel post http://lists.xensource.com/archives/html/xen-devel/2008-01/msg00185.html -- Andre Przywara AMD-Operating System

Re: [Qemu-devel] [PATCH][RFC] To mount qemu disk image on the host

to implement it. Regards, Andre. -- Andre Przywara AMD-Operating System Research Center (OSRC), Dresden, Germany Tel: +49 351 277-84917 to satisfy European Law for business letters: AMD Saxony Limited Liability Company Co. KG, Wilschdorfer Landstr. 101, 01109 Dresden, Germany Register Court

[Qemu-devel] Re: CPU type qemu64 breaks guest code

to contribute to testing, if that plan sounds OK. -- Andre Przywara AMD-Operating System Research Center (OSRC), Dresden, Germany

Re: [Qemu-devel] [PATCH resend] vl.c: Don't limit node count by smp count

Przywara andre.przyw...@amd.com Regards, Andre. -- Andre Przywara AMD-Operating System Research Center (OSRC), Dresden, Germany

Re: [Qemu-devel] qemu -numa option and non-contiguous CPU ranges

. Regards, Andre. My question is: should we support this option format in qemu, or should we change libvirt to use another format (that has yet to be implemented, because currently there's no way to specify a non-contiguous set of CPUs for a NUMA node). Any suggestions? -- Andre Przywara AMD

Re: [Qemu-devel] Semantics of -cpu host (was Re: [PATCH 2/2] Expose tsc deadline timer cpuid to guest)

to figure out what are the expectations/requirements, to know _which_ changes will be needed. On Tue, Apr 24, 2012 at 02:19:25PM -0300, Eduardo Habkost wrote: (CCing Andre Przywara, in case he can help to clarify what's the expected meaning of -cpu host) [...] I am not sure I understand what

[Qemu-devel] [PATCH] i386/cpu: name new CPUID bits

, RDSeed and ADX. Sources where the AMD BKDG for Family 15h/Model 10h and the Linux kernel for the leaf 7 bits. Signed-off-by: Andre Przywara andre.przyw...@amd.com --- target-i386/cpu.c | 16 target-i386/cpu.h | 21 + 2 files changed, 29 insertions(+), 8

[Qemu-devel] [PATCH] vnc-tls: Fix compilation with newer versions of GNU-TLS

the header file in RHEL 5.0 (v1.4.1) seems to have it already. If someone finds a broken distribution, tell me and I insert some compat code. Signed-off-by: Andre Przywara andre.przyw...@amd.com --- ui/vnc-tls.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/ui/vnc-tls.c b/ui

Re: [Qemu-devel] [PATCH] i386/cpu: name new CPUID bits

On 10/18/12 18:33, Eduardo Habkost wrote: On Wed, Oct 17, 2012 at 11:17:26PM +0200, Andre Przywara wrote: Update QEMU's knowledge of CPUID bit names. This allows to enable/disable those new features on QEMU's command line when using KVM and prepares future feature enablement in QEMU

[Qemu-devel] [PATCH] fdt: update embedded header file from upstream to fix compilation

. This change also works with older installed versions of dtc. The upstream version got a GPL or BSD dual license header meanwhile. I retained the original GPL license header from QEMU, only added the original copyrights. Signed-off-by: Andre Przywara andre.przyw...@linaro.org --- include

Re: [Qemu-devel] [PATCH] fdt: update embedded header file from upstream to fix compilation

On 05/07/2013 02:44 PM, Peter Maydell wrote: On 7 May 2013 13:36, Andre Przywara andre.przyw...@linaro.org wrote: Upstream dtc.git introduced a change in libfdt_env.h, which breaks compilation with QEMU's version of it: CC arm-softmmu/device_tree.o In file included from /usr/include

Re: [Qemu-devel] [PATCH] fdt: update embedded header file from upstream to fix compilation

On 05/07/2013 03:24 PM, Peter Maydell wrote: On 7 May 2013 13:52, Andre Przywara andre.przyw...@linaro.org wrote: On 05/07/2013 02:44 PM, Peter Maydell wrote: I'm not entirely sure I understand why we need change. Have upstream really introduced a breaking change for everybody who uses libfdt

Re: [Qemu-devel] [kvm-unit-tests PATCH v4 03/11] arm/arm64: smp: support more than 8 cpus

Hi, On 09/11/16 11:57, Andrew Jones wrote: > On Wed, Nov 09, 2016 at 11:12:03AM +0000, Andre Przywara wrote: > [...] >>> diff --git a/lib/arm/setup.c b/lib/arm/setup.c >>> index 7e7b39f11dde..b6e2d5815e72 100644 >>> --- a/lib/arm/setup.c >>> +++ b/lib/

Re: [Qemu-devel] [kvm-unit-tests PATCH v4 09/11] arm/arm64: add initial gicv3 support

Hi, On 08/11/16 20:21, Andrew Jones wrote: > Signed-off-by: Andrew Jones > > --- > v4: > - only take defines from kernel we need now [Andre] > - simplify enable by not caring if we reinit the distributor [drew] > v2: > - configure irqs as NS GRP1 > --- >

Re: [Qemu-devel] [kvm-unit-tests PATCH v4 06/11] arm/arm64: add initial gicv2 support

Hi, On 08/11/16 20:21, Andrew Jones wrote: > Add some gicv2 support. This just adds init and enable > functions, allowing unit tests to start messing with it. > > Signed-off-by: Andrew Jones > > --- > v4: > - only take defines from kernel we need now [Andre] > - moved

Re: [Qemu-devel] [kvm-unit-tests PATCH v4 09/11] arm/arm64: add initial gicv3 support

Hi, On 09/11/16 13:08, Andrew Jones wrote: > On Wed, Nov 09, 2016 at 12:35:48PM +0000, Andre Przywara wrote: > [...] >>> diff --git a/lib/arm/asm/gic-v3.h b/lib/arm/asm/gic-v3.h >>> new file mode 100644 >>> index ..03321f8c860f >>> --

Re: [Qemu-devel] [kvm-unit-tests PATCH v4 08/11] libcflat: add IS_ALIGNED() macro, and page sizes

Hi, On 08/11/16 20:21, Andrew Jones wrote: > From: Peter Xu <pet...@redhat.com> > > These macros will be useful to do page alignment checks. Reviewed-by: Andre Przywara <andre.przyw...@arm.com> Cheers, Andre. > Signed-off-by: Peter Xu <pet...@redhat.com> > [

Re: [Qemu-devel] [kvm-unit-tests PATCH v4 03/11] arm/arm64: smp: support more than 8 cpus

Hi, On 08/11/16 20:21, Andrew Jones wrote: > By adding support for launching with gicv3 we can break the 8 vcpu > limit. This patch adds support to smp code and also selects the > vgic model corresponding to the host. The vgic model may also be > manually selected by adding e.g. -machine

[Qemu-devel] [RFC PATCH] kvm-unit-tests: arm/arm64: strip GIC headers

v3 GIC series (as in his github branch). Signed-off-by: Andre Przywara <andre.przyw...@arm.com> --- lib/arm/asm/arch_gicv3.h | 62 - lib/arm/asm/gic-v2.h | 22 - lib/arm/asm/gic-v3.h | 227 - lib/arm64/asm/arch_g

Re: [Qemu-devel] [kvm-unit-tests PATCH v5 10/11] arm/arm64: gicv3: add an IPI test

Hi, On 10/11/16 19:53, Alex Bennée wrote: > So I was re-basing my kvm-unit-tests against your GIC rework and found > myself copy and pasting a bunch of this into my tests that fire IRQs. So I take it you are working on (or already have) code to test SPIs, probably via GICD_ISPENDR? Just

Re: [Qemu-devel] [kvm-unit-tests PATCH v5 07/11] arm/arm64: gicv2: add an IPI test

Hi, more a comment loosely related to this patch ... > diff --git a/arm/unittests.cfg b/arm/unittests.cfg > index 3f6fa45c587e..68bf5cd6008f 100644 > --- a/arm/unittests.cfg > +++ b/arm/unittests.cfg > @@ -54,3 +54,10 @@ file = selftest.flat > smp = $MAX_SMP > extra_params = -append 'smp' >

Re: [Qemu-devel] [kvm-unit-tests PATCH v5 06/11] arm/arm64: add initial gicv2 support

Hi, On 11/11/16 14:52, Alex Bennée wrote: > > Andrew Jones writes: > >> Add some gicv2 support. This just adds init and enable >> functions, allowing unit tests to start messing with it. >> >> Signed-off-by: Andrew Jones >> >> --- >> v5: share/use only

Re: [Qemu-devel] [kvm-unit-tests PATCH v5 10/11] arm/arm64: gicv3: add an IPI test

Hi, On 11/11/16 14:53, Alex Bennée wrote: > > Andrew Jones writes: > >> On Fri, Nov 11, 2016 at 10:02:59AM +, Alex Bennée wrote: >>> >>> Andrew Jones writes: >>> On Thu, Nov 10, 2016 at 07:53:58PM +, Alex Bennée wrote: [...] >>

Re: [Qemu-devel] [kvm-unit-tests PATCH v5 03/11] arm/arm64: smp: support more than 8 cpus

Andre] Given that we address this in the future: Reviewed-by: Andre Przywara <andre.przyw...@arm.com>

Re: [Qemu-devel] [kvm-unit-tests PATCH v5 06/11] arm/arm64: add initial gicv2 support

[Andre] Thanks! That looks much better now. Reviewed-by: Andre Przywara <andre.przyw...@arm.com> > v4: > - only take defines from kernel we need now [Andre] > - moved defines to asm/gic.h so they'll be shared with v3 [drew] > - simplify enable by not caring if w

Re: [Qemu-devel] [kvm-unit-tests PATCH v4 00/11] arm/arm64: add gic framework

Hi, so is this actually v4 just resent? Or is this is a new version with s/5/4/? I can't spot any of the key changes quickly ... Cheers, Andre. On 10/11/16 16:07, Andrew Jones wrote: > v4: > - Eric's r-b's > - Andre's suggestion to only take defines we need > - several other changes listed

Re: [Qemu-devel] [kvm-unit-tests PATCH v3 07/10] arm/arm64: add initial gicv3 support

Hi Drew, On 15/07/16 14:00, Andrew Jones wrote: > Signed-off-by: Andrew Jones > > --- > v2: configure irqs as NS GRP1 > --- > lib/arm/asm/arch_gicv3.h | 184 ++ > lib/arm/asm/gic-v3.h | 321 > + >

Re: [Qemu-devel] [kvm-unit-tests PATCH v5 09/11] arm/arm64: add initial gicv3 support

Hi, On 10/11/16 17:21, Andrew Jones wrote: > Signed-off-by: Andrew Jones > > --- > v5: use modern register names [Andre] > v4: > - only take defines from kernel we need now [Andre] > - simplify enable by not caring if we reinit the distributor [drew] > v2: > - configure

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