Re: [Qemu-devel] u-boot on qemu-x86

Hi Saket, On Tue, May 5, 2015 at 10:11 PM, Saket Sinha saket.sinh...@gmail.com wrote: Hi, I am trying to run u-boot as a coreboot payload on qemu-x86.Currently facing some difficulty in the process. Has anyone tried running u-boot bare-metal or as a coreboot payload on qemu-x86 before?

Re: [Qemu-devel] [U-Boot] Support of latest qemux86-64

before the breaking one it works fine, stuff gets put onto stack. >>> Could it that be that stack itself is in this 'readonly' area? >>> >>> Thanks, >>> Anton Gerasimov >>> >>> On 11/09/2017 02:58 AM, Bin Meng wrote: >>>> On Wed, Nov 8, 2017 a

Re: [Qemu-devel] [U-Boot] Support of latest qemux86-64

+QEMU dev list On Fri, Nov 3, 2017 at 10:07 PM, Anton Gerasimov wrote: > Hi all, > > I'm trying to use u-boot (v2017.01) with qemu-system-x86_64 v2.10.0 and > run into a "trying to execute code outside of RAM or ROM at x" > issue. It happens both when I build and

Re: [Qemu-devel] [U-Boot] Support of latest qemux86-64

On Wed, Nov 8, 2017 at 9:05 PM, Anton Gerasimov wrote: > Adding Igor Mammedov to the loop. > Really add Igor Mammedov. Igor, can you help look at this? > On 11/08/2017 01:59 PM, Anton Gerasimov wrote: >> To whoever might be interested: I've bisected qemu and the

Re: [Qemu-devel] [PATCH v6 2/5] hw/riscv/virt: Connect the gpex PCIe

Hi, On Wed, Oct 31, 2018 at 6:22 AM Alistair Francis wrote: > > Connect the gpex PCIe device based on the device tree included in the > HiFive Unleashed ROM. > > Signed-off-by: Alistair Francis > --- > default-configs/riscv32-softmmu.mak | 6 +- > default-configs/riscv64-softmmu.mak | 6 +-

Re: [Qemu-devel] [PATCH v6 2/5] hw/riscv/virt: Connect the gpex PCIe

Hi Alistair, On Tue, Nov 6, 2018 at 3:47 AM Alistair Francis wrote: > > On Mon, Nov 5, 2018 at 5:24 AM Bin Meng wrote: > > > > Hi, > > > > On Wed, Oct 31, 2018 at 6:22 AM Alistair Francis > > wrote: > > > > > > Connect the gpex PCIe device

[Qemu-devel] [PATCH 1/2] riscv: sifive_uart: Generate TX interrupt

At present the sifive uart model only generates RX interrupt. This updates it to generate TX interrupt so that it is more useful. Note the TX fifo is still unimplemented. Signed-off-by: Bin Meng --- hw/riscv/sifive_uart.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git

[Qemu-devel] [PATCH 2/2] riscv: sifive_u: Correct UART0's IRQ in the device tree

The UART0's interrupt vector is wrongly set to 1 in the device tree. Use SIFIVE_U_UART0_IRQ instead. Signed-off-by: Bin Meng --- hw/riscv/sifive_u.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 7bc2582..57741c2 100644

Re: [Qemu-devel] [PATCH] hw/riscv/virt: re-add machine-specific compatible string to /soc/ node

Hi Lukas, On Sun, Mar 10, 2019 at 9:44 PM Auer, Lukas wrote: > > Hi Bin, > > On Sun, 2019-03-10 at 09:07 +0800, Bin Meng wrote: > > Hi Lukas, > > > > On Mon, Feb 11, 2019 at 6:13 AM Lukas Auer > > wrote: > > > Re-add the previous compatible string &q

Re: [Qemu-devel] [PATCH] hw/riscv/virt: re-add machine-specific compatible string to /soc/ node

Hi Lukas, On Tue, Mar 12, 2019 at 10:39 PM Auer, Lukas wrote: > > Hi Bin, > > On Mon, 2019-03-11 at 23:28 +0800, Bin Meng wrote: > > Hi Lukas, > > > > On Mon, Mar 11, 2019 at 2:03 AM Auer, Lukas > > wrote: > > > Hi Bin, > > > > > >

Re: [Qemu-devel] [PATCH] hw/riscv/virt: re-add machine-specific compatible string to /soc/ node

Hi Lukas, On Mon, Mar 11, 2019 at 2:03 AM Auer, Lukas wrote: > > Hi Bin, > > On Sun, 2019-03-10 at 22:57 +0800, Bin Meng wrote: > > Hi Lukas, > > > > On Sun, Mar 10, 2019 at 9:44 PM Auer, Lukas > > wrote: > > > Hi Bin, > > > > > >

Re: [Qemu-devel] [PATCH] hw/riscv/virt: re-add machine-specific compatible string to /soc/ node

Hi Lukas, On Fri, Mar 15, 2019 at 5:01 AM Auer, Lukas wrote: > > Hi Bin, > > On Wed, 2019-03-13 at 09:51 +0800, Bin Meng wrote: > > Hi Lukas, > > > > On Tue, Mar 12, 2019 at 10:39 PM Auer, Lukas > > wrote: > > > Hi Bin, > > > > > >

Re: [Qemu-devel] [PATCH] hw/riscv/virt: re-add machine-specific compatible string to /soc/ node

Hi Lukas, On Mon, Feb 11, 2019 at 6:13 AM Lukas Auer wrote: > > Re-add the previous compatible string "riscv-virtio-soc" to the soc > device tree node to allow U-Boot and Linux to bind machine-specific > drivers to it. The current compatible string "simple-bus" is retained. > > This is required

[Qemu-devel] [PATCH 2/2] riscv: sifive_u: Update the plic hart config to support multicore

At present the PLIC is instantiated to support only one hart, while the machine allows at most 4 harts to be created. When more than 1 hart is configured, PLIC needs to instantiated to support multicore, otherwise an SMP OS does not work. Signed-off-by: Bin Meng --- hw/riscv/sifive_u.c | 16

Re: [Qemu-devel] [PATCH] riscv: virt: Correct pci "bus-range" encoding

Hi Alistair, On Thu, May 30, 2019 at 11:14 AM Alistair Francis wrote: > > On Wed, May 29, 2019 at 1:52 AM Bin Meng wrote: > > > > The largest pci bus number should be calculated from ECAM size, > > instead of its base address. > > > > Signed-off-by: Bin Me

[Qemu-devel] [PATCH] riscv: virt: Correct pci "bus-range" encoding

The largest pci bus number should be calculated from ECAM size, instead of its base address. Signed-off-by: Bin Meng --- hw/riscv/virt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index fc4c6b3..d6132d9 100644 --- a/hw/riscv/virt.c

Re: [Qemu-devel] [PATCH] riscv: virt: Correct pci "bus-range" encoding

On Thu, May 30, 2019 at 11:36 AM Bin Meng wrote: > > Hi Alistair, > > On Thu, May 30, 2019 at 11:14 AM Alistair Francis > wrote: > > > > On Wed, May 29, 2019 at 1:52 AM Bin Meng wrote: > > > > > > The largest pci bus number should be calculated from

[Qemu-devel] [PATCH] riscv: sifive_test: Add reset functionality

This adds a reset opcode for sifive_test device to trigger a system reset for testing purpose. Signed-off-by: Bin Meng --- hw/riscv/sifive_test.c | 4 include/hw/riscv/sifive_test.h | 3 ++- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/hw/riscv/sifive_test.c b/hw

Re: [Qemu-devel] [PATCH v1 2/5] hw/riscv: Add support for loading a firmware

-by: Alistair Francis > --- > hw/riscv/boot.c | 26 ++ > hw/riscv/sifive_u.c | 4 > hw/riscv/virt.c | 4 > include/hw/riscv/boot.h | 2 ++ > 4 files changed, 36 insertions(+) > Reviewed-by: Bin Meng Tested-by: Bin Meng

Re: [Qemu-devel] [PATCH v1 4/5] roms: Add OpenSBI version 0.3

os/opensbi-riscv64-virt-fw_jump.bin > create mode 160000 roms/opensbi > Reviewed-by: Bin Meng Tested-by: Bin Meng

Re: [Qemu-devel] [PATCH v1 3/5] hw/riscv: Extend the kernel loading support

is > --- > hw/riscv/boot.c | 18 ++ > 1 file changed, 14 insertions(+), 4 deletions(-) > Reviewed-by: Bin Meng Tested-by: Bin Meng

Re: [Qemu-devel] [PATCH v1 5/5] hw/riscv: Load OpenSBI as the default firmware

changed, 84 insertions(+), 6 deletions(-) > Reviewed-by: Bin Meng Tested-by: Bin Meng

Re: [Qemu-devel] [RFC v1 3/5] hw/riscv: Extend the kernel loading support

On Wed, Jun 19, 2019 at 8:56 AM Alistair Francis wrote: > > Extend the RISC-V kernel loader to support uImage and Image files. > A Linux kernel can now be booted with: > > qemu-system-riscv64 -machine virt -bios fw_jump.elf -kernel Image > > Signed-off-by: Alistair Francis > --- >

Re: [Qemu-devel] [Qemu-riscv] [RFC v1 4/5] roms: Add OpenSBI version 0.3

On Wed, Jun 19, 2019 at 1:14 PM Anup Patel wrote: > > On Wed, Jun 19, 2019 at 6:24 AM Alistair Francis > wrote: > > > > Add OpenSBI version 0.3 as a git submodule and as a prebult binary. > > > > Signed-off-by: Alistair Francis > > --- > > .gitmodules | 3 +++ > >

Re: [Qemu-devel] [Qemu-riscv] [RFC v1 2/5] hw/riscv: Add support for loading a firmware

of RAM. > Yes, current kernel_translate() logic is tightly coupled to the kernel entry VA, and if we link kernel at some other address it will just fail. > Jonathan > > On Wed, Jun 19, 2019 at 11:16 AM Bin Meng wrote: >> >> On Wed, Jun 19, 2019 at 8:53 AM Alistair Francis >>

Re: [Qemu-devel] [RFC v1 0/5] RISC-V: Add firmware loading support and default

On Wed, Jun 19, 2019 at 10:30 PM Alistair Francis wrote: > > On Wed, Jun 19, 2019 at 7:26 AM Bin Meng wrote: > > > > On Wed, Jun 19, 2019 at 8:56 AM Alistair Francis > > wrote: > > > > > > This is an RFC as it will break ALL current users! See

Re: [Qemu-devel] [RFC v1 2/5] hw/riscv: Add support for loading a firmware

On Wed, Jun 19, 2019 at 8:53 AM Alistair Francis wrote: > > Add support for loading a firmware file for the virt machine and the > SiFive U. This can be run with the following command: > > qemu-system-riscv64 -machine virt -bios fw_jump.elf -kernel vmlinux > > Signed-off-by: Alistair Francis

Re: [Qemu-devel] [RFC v1 1/5] hw/riscv: Split out the boot functions

re that we still leave > + * enough room for a decent sized initrd, and on boards with large > + * amounts of RAM we must avoid the initrd being so far up in RAM > + * that it is outside lowmem and inaccessible to the kernel. > + * So for boards with less than 256MB of RAM we put the initrd > + * halfway into RAM, and for boards with 256MB of RAM or more we put > + * the initrd at 128MB. > + */ [snip] Reviewed-by: Bin Meng Tested-by: Bin Meng

Re: [Qemu-devel] [PATCH] riscv: sifive_test: Add reset functionality

Hi Alistair, On Tue, Jun 18, 2019 at 1:15 AM Alistair Francis wrote: > > On Fri, Jun 14, 2019 at 8:30 AM Bin Meng wrote: > > > > This adds a reset opcode for sifive_test device to trigger a system > > reset for testing purpose. > > > > Signed-off-by:

Re: [Qemu-devel] [RFC v1 0/5] RISC-V: Add firmware loading support and default

On Wed, Jun 19, 2019 at 8:56 AM Alistair Francis wrote: > > This is an RFC as it will break ALL current users! See below for details. > > This series consolidates the current RISC-V kernel loading > impelementation while also adding support for the -bios option and more > advanced kernel image

Re: [Qemu-devel] [PATCH] riscv: sifive_test: Add reset functionality

Hi Palmer, On Fri, Jun 21, 2019 at 10:53 AM Palmer Dabbelt wrote: > > On Wed, 19 Jun 2019 06:42:21 PDT (-0700), bmeng...@gmail.com wrote: > > Hi Alistair, > > > > On Tue, Jun 18, 2019 at 1:15 AM Alistair Francis > > wrote: > >> > >>

Re: [Qemu-devel] [Qemu-riscv] [RFC v1 4/5] roms: Add OpenSBI version 0.3

On Thu, Jun 20, 2019 at 2:30 AM Alistair Francis wrote: > > On Wed, Jun 19, 2019 at 8:18 AM Bin Meng wrote: > > > > On Wed, Jun 19, 2019 at 1:14 PM Anup Patel wrote: > > > > > > On Wed, Jun 19, 2019 at 6:24 AM Alistair Francis > > > wrote: >

Re: [Qemu-devel] [Qemu-riscv] [PATCH 2/2] riscv: sifive_u: Update the plic hart config to support multicore

Hi Fabien, On Tue, Jul 9, 2019 at 12:31 AM Fabien Chouteau wrote: > > Hi Bin, > > Thanks for this patch. > > I know I am very late to the game but I have a comment here. > > On 17/05/2019 17:51, Bin Meng wrote: > > +/* create PLIC hart

Re: [Qemu-devel] [PATCH] riscv: sifive_test: Add reset functionality

On Tue, Jul 9, 2019 at 5:48 PM Palmer Dabbelt wrote: > > On Fri, 14 Jun 2019 08:15:51 PDT (-0700), bmeng...@gmail.com wrote: > > This adds a reset opcode for sifive_test device to trigger a system > > reset for testing purpose. > > > > Signed-off-by: Bin M

Re: [Qemu-devel] [PATCH] riscv: virt: Correct pci "bus-range" encoding

Hi, On Fri, Jun 7, 2019 at 2:46 AM Alistair Francis wrote: > > On Thu, Jun 6, 2019 at 5:55 AM Bin Meng wrote: > > > > On Thu, May 30, 2019 at 11:36 AM Bin Meng wrote: > > > > > > Hi Alistair, > > > > > > On Thu, May 30, 2019 at 11:14 AM

Re: [Qemu-devel] [PATCH] riscv: sifive_test: Add reset functionality

2:21 PDT (-0700), bmeng...@gmail.com wrote: > >> > Hi Alistair, > >> > > >> > On Tue, Jun 18, 2019 at 1:15 AM Alistair Francis > >> > wrote: > >> >> > >> >> On Fri, Jun 14, 2019 at 8:30 AM Bin Meng wrote: >

Re: [Qemu-devel] [PATCH 1/2] riscv: sifive_u: Do not create hard-coded phandles in DT

Hi, On Sat, May 18, 2019 at 5:34 AM Alistair Francis wrote: > > On Fri, 2019-05-17 at 08:51 -0700, Bin Meng wrote: > > At present the cpu, plic and ethclk nodes' phandles are hard-coded > > to 1/2/3 in DT. If we configure more than 1 cpu for the machine, > > all cpu

Re: [Qemu-devel] [PATCH for 4.1 v3] target/riscv: Expose time CSRs when allowed by [m|s]counteren

Hi Palmer, On Tue, Jun 25, 2019 at 5:57 PM Palmer Dabbelt wrote: > > On Mon, 24 Jun 2019 16:03:20 PDT (-0700), finte...@gmail.com wrote: > > Apparently my previous message didn't make it out onto the list (sorry > > about all these email glitches!). I've included the message again below. > >

Re: [Qemu-devel] [PATCH for 4.1 v3] target/riscv: Expose time CSRs when allowed by [m|s]counteren

On Wed, Jun 26, 2019 at 4:23 AM Jonathan Behrens wrote: > > I just did some testing on a HiFive Unleashed board and can confirm what > you are saying. The low 5 bits of both mcounteren and scounteren are > writable (if you try to write 0x to them, they'll take on the value > 0x1F) but

Re: [Qemu-devel] [PATCH v2] target/riscv: Hardwire mcounter.TM and upper bits of [m|s]counteren

On Tue, Jul 2, 2019 at 8:20 AM Alistair Francis wrote: > > On Mon, Jul 1, 2019 at 8:56 AM wrote: > > > > From: Jonathan Behrens > > > > QEMU currently always triggers an illegal instruction exception when > > code attempts to read the time CSR. This is valid behavor, but only if > > the TM bit

[Qemu-devel] [PATCH v3] riscv: hmp: Add a command to show virtual memory mappings

. Signed-off-by: Bin Meng Acked-by: Dr. David Alan Gilbert --- Changes in v3: - print PTEs for all harts instead of just current hart Changes in v2: - promote ppn to hwaddr when doing page table address calculation hmp-commands-info.hx | 2 +- target/riscv/Makefile.objs | 4 + target

Re: [Qemu-devel] [PATCH] riscv: hmp: Add a command to show virtual memory mappings

g every valid PTE, the command compacts the > > output by merging all contiguous physical address mappings into > > one block and only shows the merged block mapping details. > > > > Signed-off-by: Bin Meng > > --- > > > > hmp-commands-info.hx |

Re: [Qemu-devel] [PATCH v2] riscv: rv32: Root page table address can be larger than 32-bit

Hi Palmer, On Sat, Aug 10, 2019 at 9:49 AM Alistair Francis wrote: > > On Wed, Aug 7, 2019 at 7:50 PM Bin Meng wrote: > > > > For RV32, the root page table's PPN has 22 bits hence its address > > bits could be larger than the maximum bits that target_ulong is > >

[Qemu-devel] [FOR 4.1 PATCH] riscv: roms: Fix make rules for building sifive_u bios

Currently the make rules are wrongly using qemu/virt opensbi image for sifive_u machine. Correct it. Signed-off-by: Bin Meng --- roms/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/roms/Makefile b/roms/Makefile index dc70fb5..775c963 100644 --- a/roms/Makefile

[Qemu-devel] [PATCH] riscv: sifive_e: Correct various SoC IP block sizes

Some of the SoC IP block sizes are wrong. Correct them according to the FE310 manual. Signed-off-by: Bin Meng --- hw/riscv/sifive_e.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index 2a499d8..9655847 100644 --- a/hw/riscv

Re: [Qemu-devel] [FOR 4.1 PATCH] riscv: roms: Fix make rules for building sifive_u bios

Hi Alistair/Palmer, On Sat, Aug 3, 2019 at 2:08 PM Bin Meng wrote: > > Currently the make rules are wrongly using qemu/virt opensbi image > for sifive_u machine. Correct it. > > Signed-off-by: Bin Meng > > --- > > roms/Makefile | 2 +- > 1 file changed, 1 insert

Re: [Qemu-devel] [PATCH v3 3/7] target/riscv: Create function to test if FP is enabled

/cpu_helper.c | 10 ++ > target/riscv/csr.c| 20 +++- > 3 files changed, 26 insertions(+), 10 deletions(-) > Reviewed-by: Bin Meng

Re: [Qemu-devel] [PATCH v3 7/7] target/riscv: Convert mip to target_ulong

deletion(-) > Reviewed-by: Bin Meng

[Qemu-devel] [PATCH 2/2] riscv: Resolve full path of the given bios image

At present when "-bios image" is supplied, we just use the straight path without searching for the configured data directories. Like "-bios default", we add the same logic so that "-L" actually works. Signed-off-by: Bin Meng --- hw/riscv/boot.c | 6 +++--- 1 fi

Re: [Qemu-devel] [PATCH v3 1/7] target/riscv: Don't set write permissions on dirty PTEs

where we aren't doing a store. > > Signed-off-by: Alistair Francis > --- > target/riscv/cpu_helper.c | 6 ++ > 1 file changed, 2 insertions(+), 4 deletions(-) > Reviewed-by: Bin Meng

Re: [Qemu-devel] [PATCH v3 2/7] riscv: plic: Remove unused interrupt functions

riscv/sifive_plic.h | 3 --- > 2 files changed, 15 deletions(-) > Reviewed-by: Bin Meng

Re: [Qemu-devel] [PATCH v3 4/7] target/riscv: Update the Hypervisor CSRs to v0.4

e changed, 18 insertions(+), 17 deletions(-) > Reviewed-by: Bin Meng

[Qemu-devel] [PATCH 1/2] riscv: Add a helper routine for finding firmware

This adds a helper routine for finding firmware. It is currently used only for "-bios default" case. Signed-off-by: Bin Meng --- hw/riscv/boot.c | 22 +++--- include/hw/riscv/boot.h | 1 + 2 files changed, 16 insertions(+), 7 deletions(-) diff --git a/hw/ri

[Qemu-devel] [PATCH 0/2] riscv: Fix "-L" not working for bios image search path

Currently when QEMU is given a bios image with only a file name and its file path passed in "-L", it still reports file not found. This series fixes the issue. This is especially helpful for creating distro QEMU packages. Bin Meng (2): riscv: Add a helper routine for finding firmwa

Re: [Qemu-devel] [PATCH v3 6/7] target/riscv: Fix mstatus dirty mask

On Fri, Aug 16, 2019 at 5:38 AM Alistair Francis wrote: > > Signed-off-by: Alistair Francis > --- > target/riscv/csr.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > Reviewed-by: Bin Meng

Re: [Qemu-devel] [PATCH v3 5/7] target/riscv: Use both register name and ABI name

> target/riscv/cpu.c | 19 +++ > 1 file changed, 11 insertions(+), 8 deletions(-) > Reviewed-by: Bin Meng

Re: [Qemu-devel] [PATCH 1/3] riscv: sifive_u: Add support for loading initrd

Hi Palmer, On Thu, Aug 15, 2019 at 1:06 AM Palmer Dabbelt wrote: > > On Mon, 12 Aug 2019 16:48:00 PDT (-0700), bmeng...@gmail.com wrote: > > Hi Palmer, > > > > On Tue, Aug 13, 2019 at 6:45 AM Palmer Dabbelt wrote: > >> > >> On Fri, 19 Jul 2019 06:40:43 PDT (-0700), li...@roeck-us.net wrote: >

[Qemu-devel] [PATCH v4 00/28] riscv: sifive_u: Improve the emulation fidelity of sifive_u machine

"interrupts-extended" property size - update the file header to indicate at least 2 harts are created - use create_unimplemented_device() to create the GEM management block instead of sifive_mmio_emulate() - add "phy-handle" property to the ethernet node Bin Meng (28): riscv

[Qemu-devel] [PATCH v4 04/28] riscv: hw: Change create_fdt() to return void

There is no need to return fdt at the end of create_fdt() because it's already saved in s->fdt. Signed-off-by: Bin Meng Reviewed-by: Chih-Min Chao Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis --- Changes in v4: - change create_fdt() to return void in sifive_u.c

[Qemu-devel] [PATCH v4 14/28] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC

. The cpu nodes in the generated DTS have been updated as well. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- Changes in v4: - changed to create clusters for each cpu type Changes in v3: - changed to use macros for management and compute cpu count Changes in v2: - fixed

[Qemu-devel] [PATCH v4 05/28] riscv: roms: Remove executable attribute of opensbi images

Like other binary files, the executable attribute of opensbi images should not be set. Signed-off-by: Bin Meng --- Changes in v4: - new patch to remove executable attribute of opensbi images Changes in v3: None Changes in v2: None pc-bios/opensbi-riscv32-virt-fw_jump.bin | Bin pc-bios

[Qemu-devel] [PATCH v4 19/28] riscv: sifive_u: Add PRCI block to the SoC

Add PRCI mmio base address and size mappings to sifive_u machine, and generate the corresponding device tree node. Signed-off-by: Bin Meng --- Changes in v4: None Changes in v3: None Changes in v2: None hw/riscv/sifive_u.c | 21 - include/hw/riscv/sifive_u.h | 1

[Qemu-devel] [PATCH v4 13/28] riscv: hart: Add a "hartid-base" property to RISC-V hart array

erty value. Signed-off-by: Bin Meng --- Changes in v4: - new patch to add a "hartid-base" property to RISC-V hart array Changes in v3: None Changes in v2: None hw/riscv/riscv_hart.c | 8 +--- include/hw/riscv/riscv_hart.h | 1 + 2 files changed, 6 insertions(+), 3 deletions

[Qemu-devel] [PATCH v4 08/28] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming

For hfxosccfg register programming, SIFIVE_E_PRCI_HFXOSCCFG_RDY and SIFIVE_E_PRCI_HFXOSCCFG_EN should be used. Signed-off-by: Bin Meng Acked-by: Alistair Francis Reviewed-by: Chih-Min Chao Reviewed-by: Philippe Mathieu-Daudé --- Changes in v4: None Changes in v3: None Changes in v2: None

[Qemu-devel] [PATCH v4 12/28] riscv: hart: Extract hart realize to a separate routine

says the RISC-V hart array holds the state of a heterogeneous array of RISC-V harts, which is not true. Update the comment to mention homogeneous array of RISC-V harts. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- Changes in v4: None Changes in v3: None Changes in v2: None hw/riscv

[Qemu-devel] [PATCH v4 24/28] riscv: sifive: Implement a model for SiFive FU540 OTP

This implements a simple model for SiFive FU540 OTP (One-Time Programmable) Memory interface, primarily for reading out the stored serial number from the first 1 KiB of the 16 KiB OTP memory reserved by SiFive for internal use. Signed-off-by: Bin Meng --- Changes in v4: - prefix all macros

[Qemu-devel] [PATCH v4 23/28] riscv: roms: Update default bios for sifive_u machine

With the support of heterogeneous harts and PRCI model, it's now possible to use the OpenSBI image (PLATFORM=sifive/fu540) built for the real hardware. Signed-off-by: Bin Meng --- Changes in v4: None Changes in v3: None Changes in v2: None pc-bios/opensbi-riscv64-sifive_u-fw_jump.bin | Bin

Re: [Qemu-devel] [PATCH v4] riscv: hmp: Add a command to show virtual memory mappings

On Wed, Aug 14, 2019 at 11:33 PM Bin Meng wrote: > > This adds 'info mem' command for RISC-V, to show virtual memory > mappings that aids debugging. > > Rather than showing every valid PTE, the command compacts the > output by merging all contiguous physical address mapping

Re: [Qemu-devel] [Qemu-riscv] [PATCH] riscv: sifive_e: Correct various SoC IP block sizes

Hi Palmer, On Wed, Aug 7, 2019 at 10:53 AM Bin Meng wrote: > > On Wed, Aug 7, 2019 at 5:06 AM Philippe Mathieu-Daudé > wrote: > > > > On 8/5/19 8:43 AM, Bin Meng wrote: > > > On Mon, Aug 5, 2019 at 2:14 PM Chih-Min Chao > > > wrote: > > >

Re: [Qemu-devel] [FOR 4.1 PATCH] riscv: roms: Fix make rules for building sifive_u bios

Hi Palmer, On Tue, Aug 6, 2019 at 1:04 AM Alistair Francis wrote: > > On Fri, Aug 2, 2019 at 11:08 PM Bin Meng wrote: > > > > Currently the make rules are wrongly using qemu/virt opensbi image > > for sifive_u machine. Correct it. > > > > Signed-off-by: B

[Qemu-devel] [PATCH v3 14/28] riscv: sifive: Implement PRCI model for FU540

This adds a simple PRCI model for FU540 (sifive_u). It has different register layout from the existing PRCI model for FE310 (sifive_e). Signed-off-by: Bin Meng --- Changes in v3: None Changes in v2: None hw/riscv/Makefile.objs | 1 + hw/riscv/sifive_u_prci.c | 163

[Qemu-devel] [PATCH v3 11/28] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}

Current SiFive PRCI model only works with sifive_e machine, as it only emulates registers or PRCI block in the FE310 SoC. Rename the file name to make it clear that it is for sifive_e. Signed-off-by: Bin Meng Reviewed-by: Chih-Min Chao --- Changes in v3: None Changes in v2: None hw/riscv

[Qemu-devel] [PATCH v3 22/28] riscv: sifive_u: Generate an aliases node in the device tree

The Linux kernel SiFive UART driver expects an aliases node to be present in the device tree, from which the driver extracts the port number from "serial#" in the aliases node. Signed-off-by: Bin Meng --- Changes in v3: None Changes in v2: None hw/riscv/sifive_u.c | 2 ++ 1 file

[Qemu-devel] [PATCH v3 18/28] riscv: hw: Implement a model for SiFive FU540 OTP

This implements a simple model for SiFive FU540 OTP (One-Time Programmable) Memory interface, primarily for reading out the stored serial number from the first 1 KiB of the 16 KiB OTP memory reserved by SiFive for internal use. Signed-off-by: Bin Meng --- Changes in v3: None Changes in v2: None

[Qemu-devel] [PATCH v3 08/28] riscv: sifive_u: Update PLIC hart topology configuration string

With heterogeneous harts config, the PLIC hart topology configuration string are "M,MS,.." because of the monitor hart #0. Suggested-by: Fabien Chouteau Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- Changes in v3: None Changes in v2: None hw/riscv/sifive_u.c | 7 -

[Qemu-devel] [PATCH v3 13/28] riscv: sifive_e: prci: Update the PRCI register block size

Currently the PRCI register block size is set to 0x8000, but in fact 0x1000 is enough, which is also what the manual says. Signed-off-by: Bin Meng Reviewed-by: Chih-Min Chao --- Changes in v3: None Changes in v2: None hw/riscv/sifive_e_prci.c | 2 +- include/hw/riscv/sifive_e_prci.h

[Qemu-devel] [PATCH v3 17/28] riscv: sifive_u: Change UART node name in device tree

...", causing U-Boot fail to find the serial node in DT. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- Changes in v3: None Changes in v2: None hw/riscv/sifive_u.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index c0

[Qemu-devel] [PATCH v3 03/28] riscv: Add a sifive_cpu.h to include both E and U cpu type defines

Group SiFive E and U cpu type defines into one header file. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé --- Changes in v3: None Changes in v2: None include/hw/riscv/sifive_cpu.h | 31 +++ include/hw/riscv/sifive_e.h

[Qemu-devel] [PATCH v3 04/28] riscv: hart: Extract hart realize to a separate routine

Currently riscv_harts_realize() creates all harts based on the same cpu type given in the hart array property. With current implementation it can only create symmetric harts. Exact the hart realize to a separate routine in preparation for supporting heterogeneous hart arrays. Signed-off-by: Bin

[Qemu-devel] [PATCH v3 00/28] riscv: sifive_u: Improve the emulation fidelity of sifive_u machine

eep the PLIC compatible string unchanged as OpenSBI uses that for DT fix up - drop patch "riscv: sifive: Move sifive_mmio_emulate() to a common place" - new patch "riscv: sifive_e: Drop sifive_mmio_emulate()" Bin Meng (28): riscv: hw: Remove superfluous "linux,phandl

[Qemu-devel] [PATCH v3 01/28] riscv: hw: Remove superfluous "linux, phandle" property

"linux,phandle" property is optional. Remove all instances in the sifive_u and virt machine device tree. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- Changes in v3: None Changes in v2: None hw/riscv/sifive_u.c | 3 --- hw/riscv/virt.c | 3 --- 2 files changed, 6

[Qemu-devel] [PATCH v3 06/28] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC

d DTS have been updated as well. Signed-off-by: Bin Meng --- Changes in v3: - changed to use macros for management and compute cpu count Changes in v2: - fixed the "interrupts-extended" property size hw/riscv/sifive_u.c | 40 +++- include

[Qemu-devel] [PATCH v3 10/28] riscv: sifive_u: Remove the unnecessary include of prci header

sifive_u machine does not use PRCI as of today. Remove the prci header inclusion. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- Changes in v3: None Changes in v2: None hw/riscv/sifive_u.c | 1 - 1 file changed, 1 deletion(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c

[Qemu-devel] [PATCH v3 16/28] riscv: sifive_u: Add PRCI block to the SoC

Add PRCI mmio base address and size mappings to sifive_u machine, and generate the corresponding device tree node. Signed-off-by: Bin Meng --- Changes in v3: None Changes in v2: None hw/riscv/sifive_u.c | 21 - include/hw/riscv/sifive_u.h | 1 + 2 files changed

[Qemu-devel] [PATCH v3 09/28] riscv: sifive_u: Update UART base addresses and IRQs

This updates the UART base address and IRQs to match the hardware. Signed-off-by: Bin Meng Reviewed-by: Jonathan Behrens Acked-by: Alistair Francis Reviewed-by: Chih-Min Chao --- Changes in v3: - update IRQ numbers of both UARTs to match hardware as well Changes in v2: None hw/riscv

[Qemu-devel] [PATCH v3 12/28] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming

It should use SIFIVE_PRCI_HFXOSCCFG_RDY and SIFIVE_PRCI_HFXOSCCFG_EN for hfxosccfg register programming. Signed-off-by: Bin Meng Acked-by: Alistair Francis Reviewed-by: Chih-Min Chao Reviewed-by: Philippe Mathieu-Daudé --- Changes in v3: None Changes in v2: None hw/riscv/sifive_e_prci.c

[Qemu-devel] [PATCH v3 02/28] riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell

Some of the properties only have 1 cell so we should use qemu_fdt_setprop_cell() instead of qemu_fdt_setprop_cells(). Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- Changes in v3: None Changes in v2: None hw/riscv/sifive_u.c | 16 hw/riscv/virt.c | 24

[Qemu-devel] [PATCH v3 05/28] riscv: hart: Support heterogeneous harts population

rt 0, and the second cpu type before delimiter is assigned to hart 1, and so on. If the total number of cpu types supplied in "cpu-type" property is less than number of maximum harts, the last cpu type in the property will be used to populate remaining harts. Signed-off-by: Bin Meng --

[Qemu-devel] [PATCH v3 07/28] riscv: sifive_u: Set the minimum number of cpus to 2

It is not useful if we only have one management CPU. Signed-off-by: Bin Meng --- Changes in v3: - use management cpu count + 1 for the min_cpus Changes in v2: - update the file header to indicate at least 2 harts are created hw/riscv/sifive_u.c | 5 +++-- 1 file changed, 3 insertions(+), 2

[Qemu-devel] [PATCH v3 23/28] riscv: sifive_u: Fix broken GEM support

ing to use the official name used by the upstream Linux kernel, and add the management block reg base & size to the property encoding. Tested with upstream U-Boot and Linux kernel MACB drivers. Signed-off-by: Bin Meng --- Changes in v3: None Changes in v2: - use create_unimplemented_device() to

[Qemu-devel] [PATCH v3 15/28] riscv: sifive_u: Generate hfclk and rtcclk nodes

To keep in sync with Linux kernel device tree, generate hfclk and rtcclk nodes in the device tree, to be referenced by PRCI node. Signed-off-by: Bin Meng --- Changes in v3: None Changes in v2: None hw/riscv/sifive_u.c | 23 +++ include/hw/riscv/sifive_u.h | 2

[Qemu-devel] [PATCH v3 21/28] riscv: sifive_u: Update UART and ethernet node clock properties

Now that we have added PRCI nodes, update existing UART and ethernet nodes to use PRCI as their clock sources, to keep in sync with the Linux kernel device tree. With above changes, the previously handcrafted "/soc/ethclk" node is no longer needed. Remove it. Signed-off-by

[Qemu-devel] [PATCH v3 19/28] riscv: sifive_u: Instantiate OTP memory with a serial number

This adds an OTP memory with a given serial number to the sifive_u machine. With such support, the upstream U-Boot for sifive_fu540 boots out of the box on the sifive_u machine. Signed-off-by: Bin Meng --- Changes in v3: None Changes in v2: None hw/riscv/sifive_u.c | 5 + include

[Qemu-devel] [PATCH v3 27/28] riscv: virt: Change create_fdt() to return void

There is no need to return fdt at the end of create_fdt() because it's already saved in s->fdt. Other machines (sifive_u, spike) don't do it neither. Signed-off-by: Bin Meng Reviewed-by: Chih-Min Chao Reviewed-by: Philippe Mathieu-Daudé --- Changes in v3: None Changes in v2: None hw/ri

[Qemu-devel] [PATCH v3 25/28] riscv: hw: Remove not needed PLIC properties in device tree

This removes "reg-names" and "riscv,max-priority" properties of the PLIC node from device tree. Signed-off-by: Bin Meng Reviewed-by: Jonathan Behrens --- Changes in v3: None Changes in v2: - keep the PLIC compatible string unchanged as OpenSBI uses that for DT fix up

[Qemu-devel] [PATCH v3 28/28] riscv: sifive_u: Update model and compatible strings in device tree

This updates model and compatible strings to use the same strings as used in the Linux kernel device tree (hifive-unleashed-a00.dts). Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- Changes in v3: None Changes in v2: None hw/riscv/sifive_u.c | 5 +++-- 1 file changed, 3 insertions

[Qemu-devel] [PATCH v3 24/28] riscv: sifive_u: Support loading initramfs

The loading of initramfs is currently not supported on 'sifive_u'. Add the support to make '-initrd' command line parameter useful. Signed-off-by: Bin Meng Reviewed-by: Chih-Min Chao --- Changes in v3: None Changes in v2: None hw/riscv/sifive_u.c | 13 - 1 file changed, 12

Re: [Qemu-devel] [PATCH v3 00/28] riscv: sifive_u: Improve the emulation fidelity of sifive_u machine

On Sun, Aug 11, 2019 at 4:07 PM Bin Meng wrote: > > As of today, the QEMU 'sifive_u' machine is a special target that does > not boot the upstream OpenSBI/U-Boot firmware images built for the real > SiFive HiFive Unleashed board. Hence OpenSBI supports a special platform > "q

Re: [Qemu-devel] RISCV: when will the CLIC be ready?

On Tue, Aug 20, 2019 at 3:09 AM Alistair Francis wrote: > > On Mon, Aug 19, 2019 at 6:44 AM liuzhiwei wrote: > > > > > > On 2019/8/17 上午1:29, Alistair Francis wrote: > > > On Thu, Aug 15, 2019 at 8:39 PM liuzhiwei wrote: > > >> Hi, Palmer > > >> > > >> When Michael Clark still was the

[Qemu-devel] [PATCH v4 03/28] riscv: hw: Remove not needed PLIC properties in device tree

This removes "reg-names" and "riscv,max-priority" properties of the PLIC node from device tree. Signed-off-by: Bin Meng Reviewed-by: Jonathan Behrens Reviewed-by: Alistair Francis --- Changes in v4: None Changes in v3: None Changes in v2: - keep the PLIC compati

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