8 -
> tcg/tcg-op-gvec.c | 35 ++
> 2 files changed, 52 insertions(+), 21 deletions(-)
>
> --
> 2.25.1
>
>
Thanks Richard, I will give it a try on my RVV 1.0.
Thanks for the quick fix.
Frank Chang
ce now between vsetvl and vsetvli is the format of zimm
and s2 fields.
But they have different formats and are queried by different functions,
i.e. s2 = tcg_const_tl(a->zimm); and gen_get_gpr(s2, a->rs2);
Is there any elegant way to retrieve the values of zimm and s2 by shared
common codes?
>
> r~
>
Thanks,
Frank Chang
On Wed, Sep 30, 2020 at 3:04 AM wrote:
> From: Frank Chang
>
> This patchset implements the vector extension v1.0 for RISC-V on QEMU.
>
> This patchset is sent as RFC because RVV v1.0 is still in draft state.
> v2 patchset was sent for RVV v0.9 and bumped to RVV v1.0
On Mon, Oct 5, 2020 at 10:00 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> On 10/5/20 2:12 AM, Frank Chang wrote:
> > I think you want to be sharing the code between vsetvl and vsetvli
> now. Just
> > pass in a TCGv value to a common help
On Mon, Aug 17, 2020 at 4:50 PM wrote:
> From: Frank Chang
>
> This patchset implements the vector extension v1.0 for RISC-V on QEMU.
>
> This patchset is sent as RFC because RVV v1.0 is still in draft state.
> v2 patchset was sent for RVV v0.9 and bumped to RVV v1.0
On Thu, Aug 27, 2020 at 12:56 AM Alistair Francis
wrote:
> On Tue, Aug 25, 2020 at 1:29 AM Frank Chang
> wrote:
> >
> > On Mon, Aug 17, 2020 at 4:50 PM wrote:
> >>
> >> From: Frank Chang
> >>
> >> This patchset implements the vector exte
On Thu, Aug 27, 2020 at 2:03 AM Alistair Francis
wrote:
> On Wed, Aug 26, 2020 at 10:39 AM Frank Chang
> wrote:
> >
> > On Thu, Aug 27, 2020 at 12:56 AM Alistair Francis
> wrote:
> >>
> >> On Tue, Aug 25, 2020 at 1:29 AM Frank Chang
> wrote:
>
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/cpu_bits.h | 7 +++
target/riscv/csr.c | 21 +
2 files changed, 28 insertions(+)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
From: Frank Chang
Implementations may have a writable misa.v field. Analogous to the way
in which the floating-point unit is handled, the mstatus.vs field may
exist even if misa.v is clear.
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/csr.c | 2 +-
1 file
From: Frank Chang
Add the following instructions:
* vzext.vf2
* vzext.vf4
* vzext.vf8
* vsext.vf2
* vsext.vf4
* vsext.vf8
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 14
target/riscv/insn32.decode | 8 +++
target
From: Frank Chang
Immediate value in translator function is extended not only
zero-extended and sign-extended but with more modes to be applicable
with multiple formats of vector instructions.
* IMM_ZX: Zero-extended
* IMM_SX: Sign-extended
* IMM_TRUNC_SEW: Truncate to log(SEW
From: Frank Chang
Add the following instructions:
* vlre.v
* vsr.v
Signed-off-by: Frank Chang
---
target/riscv/helper.h | 21
target/riscv/insn32.decode | 22
target/riscv/insn_trans/trans_rvv.inc.c | 72 +
target/riscv
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/insn_trans/trans_rvv.inc.c | 12
target/riscv/vector_helper.c| 14 +-
2 files changed, 21 insertions(+), 5 deletions(-)
diff --git a/target/riscv/insn_trans
From: Frank Chang
* Remove "vmv.s.x: dothing if rs1 == 0" constraint.
* Add vmv.x.s instruction.
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/insn32.decode | 3 +-
target/riscv/insn_trans/trans_rvv.inc.c | 45
From: Frank Chang
NaN-boxed the scalar floating-point register based on RVV 1.0's rules.
Signed-off-by: Frank Chang
---
target/riscv/insn_trans/trans_rvv.inc.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
b/target
From: Frank Chang
* Add vrgatherei16.vv instruction.
Signed-off-by: Frank Chang
---
target/riscv/helper.h | 4
target/riscv/insn32.decode | 1 +
target/riscv/insn_trans/trans_rvv.inc.c | 21 +++--
target/riscv/vector_helper.c
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 24 ++--
target/riscv/insn32.decode | 12 +++---
target/riscv/insn_trans/trans_rvv.inc.c | 12 +++---
target/riscv/vector_helper.c| 52
From: Frank Chang
Signed-off-by: Frank Chang
---
target/riscv/fpu_helper.c | 12 ++--
target/riscv/insn_trans/trans_rvv.inc.c | 18 +-
target/riscv/internals.h| 9 +
3 files changed, 24 insertions(+), 15 deletions(-)
diff --git
From: Frank Chang
Clear tail elements only if VTA is agnostic.
Signed-off-by: Frank Chang
---
target/riscv/insn32.decode | 20 ++--
target/riscv/insn_trans/trans_rvv.inc.c | 2 +-
target/riscv/vector_helper.c| 14 --
3 files changed, 15
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 22 ---
target/riscv/insn32.decode | 7 -
target/riscv/insn_trans/trans_rvv.inc.c | 9 --
target/riscv/vector_helper.c| 205
From: Frank Chang
Add the following instructions:
* vfcvt.rtz.xu.f.v
* vfcvt.rtz.x.f.v
Also adjust GEN_OPFV_TRANS() to accept multiple floating-point rounding
modes.
Signed-off-by: Frank Chang
---
target/riscv/helper.h | 6 ++
target/riscv/insn32.decode
From: Frank Chang
log(SEW) truncate vssra.vi immediate value.
Signed-off-by: Frank Chang
---
target/riscv/insn_trans/trans_rvv.inc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
b/target/riscv/insn_trans/trans_rvv.inc.c
index
From: Frank Chang
As GVEC only supports MAXSZ and OPRSZ in the range of: [8..256] bytes
and LMUL could be a fractional number. The maximum vector size can be
operated might be less than 8 bytes or larger than 256 bytes.
Skip to use GVEC if maximum vector size <= 8 or >= 256 bytes.
Sign
From: Hsiangkai Wang
Signed-off-by: Hsiangkai Wang
Signed-off-by: Frank Chang
---
gdb-xml/riscv-32bit-csr.xml | 11 ++-
gdb-xml/riscv-64bit-csr.xml | 11 ++-
target/riscv/gdbstub.c | 4 ++--
3 files changed, 14 insertions(+), 12 deletions(-)
diff --git a/gdb-xml/riscv
From: Frank Chang
This patchset implements the vector extension v1.0 for RISC-V on QEMU.
This patchset is sent as RFC because RVV v1.0 is still in draft state.
v2 patchset was sent for RVV v0.9 and bumped to RVV v1.0 since v3 patchset.
The port is available here:
https://github.com/sifive/qemu
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/vector_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 793af990673..43ba272c09b 100644
--- a/target/riscv
From: Frank Chang
Unlike other vector instructions, load/store vector instructions return
the maximum vector size calculated with EMUL.
For other vector instructions, return VLMAX as the maximum vector size.
Signed-off-by: Frank Chang
---
target/riscv/insn_trans/trans_rvv.inc.c | 57
From: Frank Chang
Replace ETYPE from signed int to unsigned int to prevent index overflow
issue, which would lead to wrong index address.
Signed-off-by: Frank Chang
---
target/riscv/vector_helper.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/riscv
From: Frank Chang
If VS field is off, accessing vector csr registers should raise an
illegal-instruction exception.
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/csr.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/target/riscv/csr.c b/target/riscv
From: Greentime Hu
Signed-off-by: Greentime Hu
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/cpu_bits.h | 1 +
target/riscv/csr.c | 7 +++
2 files changed, 8 insertions(+)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 7afdd4814bb
From: Frank Chang
Signed-off-by: Frank Chang
---
target/riscv/helper.h | 67
target/riscv/insn32.decode | 21 ++-
target/riscv/insn_trans/trans_rvv.inc.c | 193
target/riscv/vector_helper.c| 89 ++-
4 files
From: Frank Chang
Add the following instructions:
* vqmaccu.vv
* vqmaccu.vx
* vqmacc.vv
* vqmacc.vx
* vqmaccsu.vv
* vqmaccsu.vx
* vqmaccus.vx
Signed-off-by: Frank Chang
---
target/riscv/helper.h | 15
target/riscv/insn32.decode | 7 ++
target/riscv
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 24 ++--
target/riscv/insn32.decode | 12 +-
target/riscv/insn_trans/trans_rvv.inc.c | 30 -
target/riscv
From: Frank Chang
NaN-boxed the scalar floating-point register based on RVV 1.0's rules.
Signed-off-by: Frank Chang
---
target/riscv/insn32.decode | 4 +--
target/riscv/insn_trans/trans_rvv.inc.c | 42 ++---
2 files changed, 25 insertions(+), 21 deletions
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/vector_helper.c | 19 ---
1 file changed, 19 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index f80c13b0857..e6441f18465 100644
--- a/target
From: Frank Chang
* Sign-extend vmselu.vi and vmsgtu.vi immediate values.
* Remove "set tail elements to zeros" as tail elements can be unchanged
for either VTA to have undisturbed or agnostic setting.
Signed-off-by: Frank Chang
---
target/riscv/insn_trans/trans_rvv.inc.c | 4 ++
From: Frank Chang
Signed-off-by: Frank Chang
---
target/riscv/insn_trans/trans_rvv.inc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
b/target/riscv/insn_trans/trans_rvv.inc.c
index 41a60cf2fb9..2ebe2373237 100644
--- a/target
From: Frank Chang
Add the following instructions:
* vfwcvt.rtz.xu.f.v
* vfwcvt.rtz.x.f.v
Also adjust GEN_OPFV_WIDEN_TRANS() to accept multiple floating-point
rounding modes.
Signed-off-by: Frank Chang
---
target/riscv/helper.h | 6 +++
target/riscv/insn32.decode
From: Frank Chang
Signed-off-by: Frank Chang
---
target/riscv/vector_helper.c | 24
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 600d2b53353..4d9a1cf3651 100644
--- a/target/riscv
From: Frank Chang
Truncate vsll.vi, vsrl.vi, vsra.vi's immediate values to lg2(SEW) bits.
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/insn_trans/trans_rvv.inc.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/riscv/insn_trans
From: Hsiangkai Wang
Signed-off-by: Hsiangkai Wang
Signed-off-by: Frank Chang
---
gdb-xml/riscv-64bit-csr.xml | 7 ++
target/riscv/cpu.c | 1 +
target/riscv/cpu.h | 25 +++
target/riscv/gdbstub.c | 126 +++-
4 files changed, 157
From: Frank Chang
As in RVV 1.0 design, MLEN is hardcoded with value 1 (Section 4.5).
Thus, remove all MLEN related calculations.
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/insn_trans/trans_rvv.inc.c | 35 +---
target/riscv/internals.h| 9
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 10 +-
target/riscv/cpu.h | 2 +-
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/cpu.h| 6 ++
target/riscv/cpu_bits.h | 1 +
target/riscv/cpu_helper.c | 16 +++-
target/riscv/csr.c| 25 -
4 files
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/cpu_bits.h | 1 +
target/riscv/csr.c | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index
From: Frank Chang
Update check functions with RVV 1.0 rules.
Signed-off-by: Frank Chang
---
target/riscv/insn_trans/trans_rvv.inc.c | 708
1 file changed, 476 insertions(+), 232 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
b/target/riscv
From: Frank Chang
Signed-off-by: Frank Chang
---
target/riscv/helper.h | 129 +++---
target/riscv/insn32.decode | 43 +++--
target/riscv/insn_trans/trans_rvv.inc.c | 221 +++-
target/riscv/vector_helper.c| 188
From: Frank Chang
Add the following instructions:
* vaaddu.vv
* vaaddu.vx
* vasubu.vv
* vasubu.vx
Remove the following instructions:
* vadd.vi
Signed-off-by: Frank Chang
---
target/riscv/helper.h | 16 ++
target/riscv/insn32.decode | 13 +++--
target
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/insn32.decode | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 7a10fc27c5f..15afc469cb0 100644
--- a/target/riscv
From: Frank Chang
Add the following instructions:
* vmv1r.v
* vmv2r.v
* vmv4r.v
* vmv8r.v
Signed-off-by: Frank Chang
---
target/riscv/insn32.decode | 4
target/riscv/insn_trans/trans_rvv.inc.c | 25 +
2 files changed, 29 insertions(+)
diff --git
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/insn32.decode | 1 -
target/riscv/insn_trans/trans_rvv.inc.c | 23 ---
2 files changed, 24 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 6 --
target/riscv/insn32.decode | 2 --
target/riscv/insn_trans/trans_rvv.inc.c | 2 --
target/riscv/vector_helper.c| 13 -
4
From: Frank Chang
* Remove clear function from helper functions as the tail elements
are unchanged in RVV 1.0.
Signed-off-by: Frank Chang
---
target/riscv/vector_helper.c | 19 ---
1 file changed, 12 insertions(+), 7 deletions(-)
diff --git a/target/riscv/vector_helper.c b
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/insn_trans/trans_rvv.inc.c | 69 -
target/riscv/translate.c| 33
2 files changed, 90 insertions(+), 12 deletions(-)
diff
From: Frank Chang
* Remove VXRM and VXSAT fields from FCSR register as they are only
presented in VCSR register.
* Remove RVV loose check in fs() predicate function.
Signed-off-by: Frank Chang
---
target/riscv/csr.c | 13 -
1 file changed, 13 deletions(-)
diff --git a/target
From: Frank Chang
Signed-off-by: Frank Chang
---
target/riscv/helper.h | 100 +++---
target/riscv/insn32-64.decode | 18 +-
target/riscv/insn32.decode | 36 +++-
target/riscv/insn_trans/trans_rvv.inc.c | 220 ++
target/riscv
From: Frank Chang
* Add fp16 nan-box check generator function, if a 16-bit input is not
properly nanboxed, then the input is replaced with the default qnan.
* Add do_nanbox() helper function to utilize gen_check_nanbox_X() to
generate the NaN-boxed floating-point values based on SEW setting
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/insn32.decode | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 0992d6ac86d..7a10fc27c5f 100644
--- a/target/riscv
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/insn32.decode | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index c99575d1360..f142aa5d073 100644
--- a/target/riscv
From: Frank Chang
Signed-off-by: Frank Chang
---
target/riscv/cpu.c | 1 +
target/riscv/cpu.h | 1 +
target/riscv/translate.c | 2 ++
3 files changed, 4 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 085381fee00..8844975bf94 100644
--- a/target/riscv
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/insn32.decode | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index c4fe9767585..2e305d492d8 100644
--- a/target/riscv
From: Frank Chang
Update vext_get_vlmax() and MAXSZ() to take fractional LMUL into
calculation for RVV 1.0.
Signed-off-by: Frank Chang
---
target/riscv/cpu.h | 43 ++---
target/riscv/insn_trans/trans_rvv.inc.c | 12 ++-
2 files changed, 42
From: Frank Chang
Signed-off-by: Frank Chang
---
target/riscv/insn_trans/trans_rvv.inc.c | 3 ++-
target/riscv/vector_helper.c| 4
2 files changed, 2 insertions(+), 5 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
b/target/riscv/insn_trans/trans_rvv.inc.c
From: Frank Chang
Signed-off-by: Frank Chang
---
target/riscv/helper.h | 30 ++
target/riscv/insn32.decode | 15 +++--
target/riscv/insn_trans/trans_rvv.inc.c | 51 ++---
target/riscv/vector_helper.c| 76
From: Frank Chang
helper_set_rounding_mode() is responsible for SIGILL, and "round to odd"
should be an interface private to translation, so add a new independent
helper_set_rod_rounding_mode().
Signed-off-by: Frank Chang
---
target/riscv/fpu_helper.c | 5 +
target/riscv/helper
From: Greentime Hu
This patch adds vector support for rv32 gdb. It allows gdb client to access
vector registers correctly.
Signed-off-by: Greentime Hu
Signed-off-by: Frank Chang
---
gdb-xml/riscv-32bit-csr.xml | 7 +++
1 file changed, 7 insertions(+)
diff --git a/gdb-xml/riscv-32bit
From: Frank Chang
Signed-off-by: Frank Chang
---
target/riscv/vector_helper.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 15a646af361..00743cbce34 100644
--- a/target/riscv/vector_helper.c
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/insn32.decode | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index f142aa5d073..a800c989050 100644
--- a/target/riscv
From: Frank Chang
Signed-off-by: Frank Chang
---
target/riscv/helper.h | 27 +++-
target/riscv/insn32.decode | 14 +++
target/riscv/insn_trans/trans_rvv.inc.c | 31 --
target/riscv/vector_helper.c| 56
From: Frank Chang
Introduce the concepts of fractional LMUL for RVV 1.0.
In RVV 1.0, LMUL bits are contiguous in vtype register.
Signed-off-by: Frank Chang
---
target/riscv/cpu.h | 15 ---
target/riscv/translate.c | 16 ++--
target/riscv/vector_helper.c
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 2 +-
target/riscv/insn32.decode | 2 +-
target/riscv/insn_trans/trans_rvv.inc.c | 7 ---
target/riscv/vector_helper.c| 6 +++---
4 files
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 2 +-
target/riscv/insn32.decode | 2 +-
target/riscv/insn_trans/trans_rvv.inc.c | 4 ++--
target/riscv/vector_helper.c| 6 +++---
4 files changed
From: Frank Chang
Signed-off-by: Frank Chang
---
target/riscv/vector_helper.c | 8
1 file changed, 8 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index e6441f18465..766622d3878 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/insn32.decode | 6 +++---
target/riscv/insn_trans/trans_rvv.inc.c | 5 -
target/riscv/vector_helper.c| 4
3 files changed, 7 insertions(+), 8 deletions(-)
diff --git
From: Frank Chang
For some vector instructions (e.g. vmv.s.x), the element is loaded with
sign-extended.
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/insn_trans/trans_rvv.inc.c | 32 +
1 file changed, 22 insertions(+), 10 deletions
From: Frank Chang
Add the following instructions:
* vfslide1up.vf
* vfslide1down.vf
Signed-off-by: Frank Chang
---
target/riscv/helper.h | 7 ++
target/riscv/insn32.decode | 2 +
target/riscv/insn_trans/trans_rvv.inc.c | 4 +
target/riscv/vector_helper.c
From: Frank Chang
Sign-extend vsaddu.vi immediate value.
Signed-off-by: Frank Chang
---
target/riscv/insn_trans/trans_rvv.inc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
b/target/riscv/insn_trans/trans_rvv.inc.c
index
On Sat, Aug 15, 2020 at 2:36 AM Richard Henderson <
richard.hender...@linaro.org> wrote:
> On 8/13/20 7:48 PM, Frank Chang wrote:
> > esz is passed from e.g. GEN_VEXT_LD_STRIDE() macro:
> >
> >> #define GEN_VEXT_LD_STRIDE(NAME, ETYPE, LOAD_FN)\
> >>
On Sat, Aug 15, 2020 at 2:36 AM Richard Henderson <
richard.hender...@linaro.org> wrote:
> On 8/13/20 7:48 PM, Frank Chang wrote:
> > esz is passed from e.g. GEN_VEXT_LD_STRIDE() macro:
> >
> >> #define GEN_VEXT_LD_STRIDE(NAME, ETYPE, LOAD_FN)\
> >>
From: Frank Chang
Signed-off-by: Frank Chang
---
target/riscv/insn_trans/trans_rvv.c.inc | 32 +++--
target/riscv/vector_helper.c| 90 ++---
2 files changed, 74 insertions(+), 48 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target
From: Frank Chang
Add the following instructions:
* vzext.vf2
* vzext.vf4
* vzext.vf8
* vsext.vf2
* vsext.vf4
* vsext.vf8
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 14 +
target/riscv/insn32.decode | 8
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/insn32.decode | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 6c95a3460a..958914458d 100644
--- a/target/riscv/insn32
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 22 ---
target/riscv/insn32.decode | 7 -
target/riscv/insn_trans/trans_rvv.c.inc | 9 --
target/riscv/vector_helper.c| 205
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/insn32.decode | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 4517f8ed54..c75d728fc5 100644
--- a/target/riscv
From: Frank Chang
Add the following instructions:
* vfcvt.rtz.xu.f.v
* vfcvt.rtz.x.f.v
Also adjust GEN_OPFV_TRANS() to accept multiple floating-point rounding
modes.
Signed-off-by: Frank Chang
---
target/riscv/insn32.decode | 11 ++--
target/riscv/insn_trans/trans_rvv.c.inc
From: Frank Chang
This patchset implements the vector extension v1.0 for RISC-V on QEMU.
This patchset is sent as RFC because RVV v1.0 is still in draft state.
v2 patchset was sent for RVV v0.9 and bumped to RVV v1.0 since v3 patchset.
The port is available here:
https://github.com/sifive/qemu
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/insn32.decode | 6 +++---
target/riscv/insn_trans/trans_rvv.c.inc | 5 -
target/riscv/vector_helper.c| 4
3 files changed, 7 insertions(+), 8 deletions(-)
diff --git
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/helper.h | 2 +-
target/riscv/insn32.decode | 2 +-
target/riscv/insn_trans/trans_rvv.c.inc | 4 ++--
target/riscv/vector_helper.c| 6 +++---
4 files changed
From: Frank Chang
Add the following instructions:
* vfslide1up.vf
* vfslide1down.vf
Signed-off-by: Frank Chang
---
target/riscv/helper.h | 7 ++
target/riscv/insn32.decode | 2 +
target/riscv/insn_trans/trans_rvv.c.inc | 16 +++
target/riscv
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/insn_trans/trans_rvv.c.inc | 12 +---
target/riscv/vector_helper.c| 12 ++--
2 files changed, 15 insertions(+), 9 deletions(-)
diff --git a/target/riscv/insn_trans
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/fpu_helper.c | 12 ++--
target/riscv/insn_trans/trans_rvv.c.inc | 18 +-
target/riscv/internals.h| 9 +
3 files changed, 24 insertions
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 10 +-
target/riscv/cpu.h | 2 +-
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/cpu_bits.h | 1 +
target/riscv/csr.c | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index
From: Frank Chang
Update check functions with RVV 1.0 rules.
Signed-off-by: Frank Chang
---
target/riscv/insn_trans/trans_rvv.c.inc | 735
1 file changed, 502 insertions(+), 233 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv
From: Greentime Hu
Signed-off-by: Greentime Hu
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/cpu_bits.h | 1 +
target/riscv/csr.c | 7 +++
2 files changed, 8 insertions(+)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 0cf8a04dd8
From: Frank Chang
Replace ETYPE from signed int to unsigned int to prevent index overflow
issue, which would lead to wrong index address.
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/vector_helper.c | 8
1 file changed, 4 insertions(+), 4 deletions
From: Frank Chang
Add the following instructions:
* vlre.v
* vsr.v
Signed-off-by: Frank Chang
---
target/riscv/helper.h | 21
target/riscv/insn32.decode | 22
target/riscv/insn_trans/trans_rvv.c.inc | 69 +
target/riscv
From: Frank Chang
NaN-boxed the scalar floating-point register based on RVV 1.0's rules.
Signed-off-by: Frank Chang
---
target/riscv/insn_trans/trans_rvv.c.inc | 16 ++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/insn32.decode | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 44d35c0271..6c95a3460a 100644
--- a/target/riscv/insn32
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/insn32.decode | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 33b4612a69..c3b42b051c 100644
--- a/target/riscv/insn32
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