Hi,
basically pointing out what I pointed for v1.
On Thu, May 23, 2013 at 10:18 AM, Claudio Fontana
claudio.font...@huawei.com wrote:
add preliminary support for TCG target aarch64.
Signed-off-by: Claudio Fontana claudio.font...@huawei.com
---
include/exec/exec-all.h |5 +-
On Mon, May 27, 2013 at 12:13 PM, Claudio Fontana
claudio.font...@huawei.com wrote:
Hello,
On 27.05.2013 11:47, Laurent Desnogues wrote:
Hi,
basically pointing out what I pointed for v1.
On Thu, May 23, 2013 at 10:18 AM, Claudio Fontana
claudio.font...@huawei.com wrote:
add preliminary
On Monday, May 27, 2013, Richard Henderson r...@twiddle.net wrote:
On 2013-05-27 04:43, Claudio Fontana wrote:
Hmm, true. Although I'd been thinking more along the lines of
arranging the code such that we'd use movz to set the zero.
I think we need to keep treating zero specially if we want
Hello,
On Thu, May 23, 2013 at 10:14 AM, Claudio Fontana
claudio.font...@huawei.com wrote:
we will use the 26bit relative relocs in the aarch64 tcg target.
Is there really any point in adding all of the relocation types?
i386 doesn't, mips doesn't, x86_64 doesn't. I didn't check the
others.
On Tue, May 28, 2013 at 3:01 PM, Claudio Fontana
claudio.font...@huawei.com wrote:
On 27.05.2013 23:14, Laurent Desnogues wrote:
On Monday, May 27, 2013, Richard Henderson r...@twiddle.net
mailto:r...@twiddle.net wrote:
On 2013-05-27 04:43, Claudio Fontana wrote:
Hmm, true. Although I'd
Hi Claudio,
here are some minor tweaks and comments.
You work is very interesting and will form a good basis for further
improvements. Thanks!
diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c
new file mode 100644
index 000..da859c7
--- /dev/null
+++
On Sun, Sep 15, 2013 at 7:27 PM, Peter Maydell peter.mayd...@linaro.org wrote:
On 15 September 2013 17:41, Rob Landley r...@landley.net wrote:
Wait, incorporating C++ code into qemu was considered the _good_ solution?
What was the bad solution?
Not supporting disassembly at all, and/or
tested this patch series with a 3.9 kernel for Vexpress
with Cortex-A15. It works fine with the generic timer
correctly detected and used.
Note the 4th patch doesn't apply as is any more.
Tested-by: Laurent Desnogues laurent.desnog...@gmail.com
Thanks,
Laurent
claudio.font...@linaro.org
Signed-off-by: Alex Bennée a...@bennee.com
Reviewed-by: Alex Bennée a...@bennee.com
Reviewed-by: Laurent Desnogues laurent.desnog...@arm.com
Except for a few minor comments below (which probably don't
require a new patch).
By the way it might be nice to add some bit
On Mon, Nov 18, 2013 at 11:15 AM, Claudio Fontana
claudio.font...@linaro.org wrote:
Hello,
On 09/27/2013 08:25 PM, Richard Henderson wrote:
On 09/26/2013 05:48 PM, Alexander Graf wrote:
This patch adds emulation support for the orr instruction.
Signed-off-by: Alexander Graf ag...@suse.de
On Tue, Nov 26, 2013 at 12:56 PM, Claudio Fontana
claudio.font...@linaro.org wrote:
On 09/27/2013 09:42 PM, Richard Henderson wrote:
On 09/26/2013 05:48 PM, Alexander Graf wrote:
+if (setflags) {
+tcg_dst = cpu_reg(dest);
+} else {
+tcg_dst = cpu_reg_sp(dest);
+}
On Thu, Nov 28, 2013 at 3:27 AM, Xin Tong trent.t...@gmail.com wrote:
I am wondering what are some of the use cases for QEMU as an instruction set
emulator(not KVM). I know QEMU is used for the android emulator and QEMU is
used to host a few cycle accurate simulators ?
what else ?
QEMU can
the list of keys.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
Tested-by: Laurent Desnogues laurent.desnog...@gmail.com
Thanks,
Laurent
---
target-arm/helper.c | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
*at() functions).
Fix this by correctly cleaning up the sys_utimensat()
implementation and #defines, so that we always provide the
syscall if needed whether we're doing it via glibc or not.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
Tested-by: Laurent Desnogues laurent.desnog
On Thu, Dec 12, 2013 at 5:07 AM, Xin Tong trent.t...@gmail.com wrote:
see questions below.
On Tue, Dec 10, 2013 at 12:25 AM, Alex Bennée alex.ben...@linaro.org wrote:
trent.t...@gmail.com writes:
Does anyone have profiles on how much time QEMU spends in translating
instructions. QEMU does
Blue Swirl a écrit :
Doesn't this condition in addx and the corresponding line in subx need
similar
treatment?
They don't change the flags.
ADDX (now named ADDC in v9) doesn't change the flags, while ADDXcc
(ADDCcc) does. The cc versions also compute overflow.
cf. SPARC v9 on
Can you reveal to us what exactly your license prohibits, for example
by pasting that part of the license here?
Though probably different from the license CodeSourcery had to sign,
you can try to download ARMv7-M architecture pdf from ARM site to see
the kind of restriction on has to agree on.
All the information used to implement the current qemu Arm support is
available from other sources not covered by this licence. I'm confident I
could prove this if necessary.
True for ARMv6, probably not for ARMv7, be it -A, -R or -M.
In the thread you cited earlier, Wolfgang Schildbach
The idea is to create a SystemC wrapper file in hw dir, where there is the
code for connect via socket to a SystemC process in host machine. The
problem is that I write my simple hw, but instead use io address such as
0x378 i need to use memory address, so I can use it in every virtualizzation
b. Once a block is generated some ID should be assigned to it right ?
in which src file it is stored ?
c. The next time a src block with the same signature is encountered
the cached host binary is used right ? -- How does qemu detect that
is the same guest block ? md5sum or other
is anyone else experiencing this? Since some hours I get messages
dating from February, March and April again...
Some from June too :)
It's a real pain, but I guess we have to live with it.
Laurent
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Now, CPUs is where I have only a vague idea of what would be needed to
simulate. I know there are up to three levels of caches and main memory,
which all have different access times. The CPU itself has a pipeline and
branch prediction and such which could invalidate the contents of
The most complex thing to accurately simulate a modern
CPU (including ARMs) is the data cache and by far.
Hm... you have to elaborate on that one. Aren't those caches like other
caches, too? With well known algorithms like LRU?
Data caches typically do many things in one cycle; for
On top of that try to find a specification for data
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K. Richard Pixley a écrit :
Well, perhaps. Except that with gcc, we get to leverage the ongoing gcc
optimizations, bug fixes, new cpu support, debugger support, etc.
Granted, not all of these are going to be relevant to the qemu
environment, but in a contest between gcc generated code and
Johannes Schindelin a écrit :
And what system did you encounter this behaviour on?
Do a:
grep -wr DEFAULT_SIGNED_CHAR gcc/config
in a gcc source tree and you will get a list for gcc targets :)
Laurent
___
Qemu-devel
Paul Brook a écrit :
Replacing the pregenerated blocks with hand written assembly isn't feasible.
Each target has its own set of ops, and each host would need its own assembly
implementation of those ops. Multiply 11 targets by 11 hosts and you get a
unmaintainable mess :-)
Shouldn't you
Daniel Jacobowitz a écrit :
Straight qemu with my previously posted MIPS patches takes 6:13 to
start and reboot a MIPS userspace (through init, so lots of fork/exec).
Thiemo's patch, which flushes the whole jump buffer, cuts it to 1:40.
A patch which finds the entries which need to be flushed
Even Rouault a écrit :
TODO list :
- implement correctly full OpenGL API
Did you consider taking a look at how Wine wraps OpenGL and/or
how Mesa makes its dispatchers? I think they may be of use,
and their license should be compatible :)
Laurent
This looks real and funny :)
http://www.ps3scene.com/news/static/WindowsXPonPS3viaQemuonLinux-1164389620.php
Laurent
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Paul Brook a écrit :
I suggest you check again. I'm fairly sure the arm926 implements the Base
Restored abort model.
Yes, but arm7 is Based Updated IIRC. What particular implementation
does Qemu target?
There are so many IMPLEMENTATION DEFINED and UNPREDICTABLE in the
architecture (that
The target doesn't really
matter, I'm just interested in the process of building a linux sytem for
arm and emulate it with Qemu.
You can perhaps look here:
http://www.linux-arm.org/LinuxDevTools/ScratchBoxQEMU
I have not tested it myself.
Laurent
On Fri, Dec 11, 2009 at 4:18 AM, Jun Koi junkoi2...@gmail.com wrote:
Another question: I look at tcg_gen_callN() to see how the helper is
executed. We put the helper opcode into the TCG code buffer, and put
helper's params into gen_opparam_buf.
However, then when TCG generates code to
On Fri, Dec 11, 2009 at 7:33 PM, Aurelien Jarno aurel...@aurel32.net wrote:
On Fri, Dec 11, 2009 at 05:54:06PM +0900, Jun Koi wrote:
Hi,
Thanks to everybody helping me to have more understanding on QEmu
internals. This community is great!
This trivial patch removes some unused params in
On Mon, Dec 14, 2009 at 1:07 PM, Paul Brook p...@codesourcery.com wrote:
- uint32_t VF; /* V is the bit 31. All other bits are undefined */
+ uint32_t VF; /* V is the bit 28. */
No. The original comment is correct.
And so that the answer is at least a bit useful: these fields
are not
On Mon, Dec 14, 2009 at 7:02 PM, Richard Henderson r...@twiddle.net wrote:
One of the other folks here (I'm sorry, I've forgotten who as I misplaced
the mail) passed me a preliminary patch to tackle the missing fp rounding
mode support. That patch added helpers to change the rounding mode, and
On Tue, Dec 15, 2009 at 4:50 AM, Richard Henderson r...@twiddle.net wrote:
On 12/14/2009 04:31 PM, Richard Henderson wrote:
On 12/14/2009 12:11 PM, Laurent Desnogues wrote:
I'll take a closer look at your patch tomorrow.
For the record, I believe this finishes what I had in mind
to do its jobs.
gcc-4.4 does not need this, but is still not standard on all platforms.
Signed-off-by: Stefan Weil w...@mail.berlios.de
Acked-by: Laurent Desnogues laurent.desnog...@gmail.com
---
target-alpha/helper.c | 1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git
On Thu, Dec 17, 2009 at 4:32 PM, malc av1...@comtv.ru wrote:
[...]
Some:
a. It breaks tcg on PPC[1]:
...qemu/tcg/tcg.c:1378: tcg fatal error
What a surprise :-)
I can provide a similar patch for ARM (I already have one
for my own implementation of setcond), but I'll wait for this
patch
On Thu, Dec 17, 2009 at 8:32 PM, Richard Henderson r...@twiddle.net wrote:
funny how you seem to follow the same paths I did months ago :-)
Heh. They are the obvious points for improvement in the emulation.
Hopefully we can get them finished this time, so that some third
person doesn't go
On Thu, Dec 17, 2009 at 6:27 PM, Richard Henderson r...@twiddle.net wrote:
Defines setcond and movcond for implementing conditional moves at
the tcg opcode level. 64-bit-on-32-bit is expanded via a setcond2
primitive plus other operations.
Signed-off-by: Richard Henderson r...@twiddle.net
On Thu, Dec 17, 2009 at 6:28 PM, Richard Henderson r...@twiddle.net wrote:
It is very handy to have a reliable mapping of a condition to its inverse.
This will be used in several patches to follow.
Signed-off-by: Richard Henderson r...@twiddle.net
Acked-by: Laurent Desnogues laurent.desnog
On Thu, Dec 17, 2009 at 6:32 PM, Richard Henderson r...@twiddle.net wrote:
Implement conditional moves in the x86_64 backend.
Signed-off-by: Richard Henderson r...@twiddle.net
---
tcg/x86_64/tcg-target.c | 65 --
1 files changed, 62
On Thu, Dec 17, 2009 at 7:38 PM, Richard Henderson r...@twiddle.net wrote:
Split out tcg_out_cond from tcg_out_brcond. Add small arguments
to all branch functions for completeness. Unify all the calls to
generate branches within brcond2 and pass on the small flag.
Signed-off-by: Richard
On Thu, Dec 17, 2009 at 6:55 PM, Richard Henderson r...@twiddle.net wrote:
There are places, like brcond2, where we know that the destination
of a forward branch will be within 127 bytes. Add the R_386_PC8
relocation type to support this, and add a flag to tcg_out_jxx to
generate it. Set the
On Fri, Dec 18, 2009 at 6:11 PM, Richard Henderson r...@twiddle.net wrote:
Also note that tcg_out_modrm will generate an unneeded prefix
for some registers. cf. the patch I sent to the list months ago.
Huh. Didn't notice since the disassembler printed what I expected to see.
Is fixing this
On Fri, Dec 18, 2009 at 10:38 PM, Richard Henderson r...@twiddle.net wrote:
On 12/18/2009 03:37 AM, Laurent Desnogues wrote:
tcg: Generic support for conditional set and conditional move.
Needs cosmetics changes.
Fixed, attachment 1.
tcg-x86_64: Implement setcond and movcond.
Some
On Sat, Dec 19, 2009 at 7:44 PM, Richard Henderson r...@twiddle.net wrote:
There are places, like brcond2, where we know that the destination
of a forward branch will be within 127 bytes.
Add the R_386_PC8 relocation type to support this. Add a flag to
tcg_out_jxx and tcg_out_brcond* to
On Mon, Dec 21, 2009 at 3:00 AM, Richard Henderson r...@twiddle.net wrote:
[...]
I *am* convinced that to remove either VTRUE or VFALSE as arguments to the
movcond primitive (implementing dest = (cond ? vtrue : dest) would do too
much violence to both the liveness analysis and the register
On Mon, Dec 21, 2009 at 10:47 AM, Paolo Bonzini pbonz...@redhat.com wrote:
On 12/21/2009 10:13 AM, Laurent Desnogues wrote:
Which front-ends would need it and would the cost to generate
code for it on some (most?) back-ends be amortized?
The ARM front-end could definitely use a backend's
On Mon, Dec 21, 2009 at 9:28 PM, Richard Henderson r...@twiddle.net wrote:
On 12/21/2009 01:13 AM, Laurent Desnogues wrote:
The question for the generalized movcond is how useful is it?
Which front-ends would need it and would the cost to generate
code for it on some (most?) back-ends
On Mon, Dec 21, 2009 at 11:50 PM, Richard Henderson r...@twiddle.net wrote:
[...]
Even if movcond was quick to generate
host code, for instance for ARM, you'd have to explicitly detect
conditional moves
One of us is confused. Why would I have to explicitly detect conditional
moves?
Most
On Sat, Dec 19, 2009 at 7:01 PM, Richard Henderson r...@twiddle.net wrote:
Defines setcond_{i32,i64} and setcond2_i32 for 64-on-32-bit.
Signed-off-by: Richard Henderson r...@twiddle.net
---
tcg/README | 20 +++-
tcg/tcg-op.h | 47
On Sun, Dec 20, 2009 at 12:11 AM, Aurelien Jarno aurel...@aurel32.net wrote:
On Sat, Dec 19, 2009 at 10:46:38AM -0800, Richard Henderson wrote:
Signed-off-by: Richard Henderson r...@twiddle.net
This looks ok, though I would appreciate someone else to review it in
details.
It looks good to me
On Tue, Dec 22, 2009 at 1:02 AM, Richard Henderson r...@twiddle.net wrote:
On 12/21/2009 03:08 PM, Laurent Desnogues wrote:
If you wanted to use movcond, you'd have to make
cond + move a special case...
You'd certainly want the ARM front-end to use movcond more often than
On Tue, Dec 22, 2009 at 3:46 PM, Laurent Desnogues
laurent.desnog...@gmail.com wrote:
On Tue, Dec 22, 2009 at 1:02 AM, Richard Henderson r...@twiddle.net wrote:
On 12/21/2009 03:08 PM, Laurent Desnogues wrote:
If you wanted to use movcond, you'd have to make
cond + move a special case
On Wed, Dec 23, 2009 at 11:04 AM, Nigel Horne n...@bandsman.co.uk wrote:
I get this error on my Debian box:
...
CC alpha-linux-user/fpu/softfloat.o
In file included from /home/njh/src/qemu/fpu/softfloat.h:523,
from /home/njh/src/qemu/fpu/softfloat.c:35:
...
On Wed, Dec 23, 2009 at 11:44 AM, Nigel Horne n...@bandsman.co.uk wrote:
Laurent Desnogues wrote:
On Wed, Dec 23, 2009 at 11:04 AM, Nigel Horne n...@bandsman.co.uk wrote:
I get this error on my Debian box:
...
CC alpha-linux-user/fpu/softfloat.o
In file included from /home/njh/src/qemu
On Sun, Dec 27, 2009 at 12:37 PM, Michael S. Tsirkin m...@redhat.com wrote:
[...]
2. When a change is committed to the tree, often no notification is sent
to the author.
Why is it a good idea to ask everyone to subscribe to qemu commits
list as well? Can 'applied thanks' mail be sent to
On Sun, Jan 10, 2010 at 9:46 PM, Blue Swirl blauwir...@gmail.com wrote:
On Sun, Jan 10, 2010 at 8:20 PM, Palle Lyckegaard pa...@lyckegaard.dk wrote:
Hi,
The tcg mulu2 operation is apparently missing for the sparc target
(tcg/sparc/tcg-target.c function tcg_out_op())
Is anyone else working
Since you wanted a no, because... there's at least
one :-)
On Tue, Dec 1, 2009 at 9:41 PM, Filip Navara filip.nav...@gmail.com wrote:
While most of the ARMv5 instructions are backward compatible with ARMv4, there
are few important differences. Most notably the stack pop and load
instructions
Acked-by: Laurent Desnogues laurent.desnog...@gmail.com
Laurent
---
fpu/softfloat-native.c | 20
fpu/softfloat-native.h | 7 ---
2 files changed, 0 insertions(+), 27 deletions(-)
diff --git a/fpu/softfloat-native.c b/fpu/softfloat-native.c
index 8d64f4e
On Wed, Jan 20, 2010 at 9:14 PM, Juan Quintela quint...@redhat.com wrote:
Signed-off-by: Juan Quintela quint...@redhat.com
---
linux-user/mmap.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/linux-user/mmap.c b/linux-user/mmap.c
index c1c7e48..25fc0b2 100644
---
On Tue, Jan 26, 2010 at 5:00 PM, Riku Voipio riku.voi...@iki.fi wrote:
From: Riku Voipio riku.voi...@nokia.com
If you compile applications with gcc -mtp=cp15, __thread
access's will generate an abort. Implement accessing allowed
cp15.c13 registers on ARMv6K+ in linux-user.
Signed-off-by:
On Tue, Jan 26, 2010 at 5:00 PM, Riku Voipio riku.voi...@iki.fi wrote:
From: Riku Voipio riku.voi...@nokia.com
Change the system-emulation code also to only support accessing
the cp15.c13 Thread ID registers on ARMv6K and newer.
Signed-off-by: Riku Voipio riku.voi...@nokia.com
---
riku.voi...@nokia.com
Acked-by: Laurent Desnogues laurent.desnog...@gmail.com
Laurent
---
target-arm/helper.c | 16 --
target-arm/translate.c | 55
2 files changed, 55 insertions(+), 16 deletions(-)
diff --git a/target
On Thu, Jan 28, 2010 at 11:44 AM, Bastien ROUCARIES
roucaries.bast...@gmail.com wrote:
Forget to cc
On Sat, Jan 23, 2010 at 11:40 PM, Anthony Liguori anth...@codemonkey.ws
wrote:
On 01/21/2010 10:27 AM, Bastien ROUCARIES wrote:
Hi,
What is the step in order to get qemu android merged
On Sat, Jan 30, 2010 at 12:04 AM, Stefan Weil w...@mail.berlios.de wrote:
[...]
that was a good suggestion. bntest raises a segmentation fault
(NULL pointer, p == 0, see below) with qemu-x86_64 on a x86_64 host.
Compile bntest statically and it should work.
x86_64 user mode is completely
On Sat, Jan 30, 2010 at 10:30 AM, Stefan Weil w...@mail.berlios.de wrote:
Laurent Desnogues schrieb:
On Sat, Jan 30, 2010 at 12:04 AM, Stefan Weil w...@mail.berlios.de
wrote:
[...]
that was a good suggestion. bntest raises a segmentation fault
(NULL pointer, p == 0, see below) with qemu
On Sat, Jan 30, 2010 at 10:30 AM, Stefan Weil w...@mail.berlios.de wrote:
Laurent Desnogues schrieb:
On Sat, Jan 30, 2010 at 12:04 AM, Stefan Weil w...@mail.berlios.de
wrote:
[...]
that was a good suggestion. bntest raises a segmentation fault
(NULL pointer, p == 0, see below) with qemu
On Wed, Feb 3, 2010 at 11:10 AM, Taimoor Mirza mooni_mi...@hotmail.com wrote:
Hi all,
I have been trying to use VGA card and LCD for integrator 926. I've built my
kernel PLUS with graphics support. I used following command to run my PLUS
application on qemu:
qemu-system-arm -M integratorcp
On Wed, Feb 3, 2010 at 5:53 PM, Utkarsh Sopan utkarsh.so...@coe.dce.edu wrote:
I am trying to add support for MIPS 64 as Host machine as my academic
project.
Note that some work has already been done for MIPS host
support.
I am new to QEMU.
Problem is I dont have a MIPS 64 machine to test
On Thu, Feb 4, 2010 at 6:26 PM, Utkarsh Sopan utkarsh.so...@coe.dce.edu wrote:
Can you tell me what is the status of adding MIPS64 support?
as at the wiki page it showed Red earlier.
Look here: http://git.aurel32.net/?p=qemu.git;a=summary
Laurent
On Fri, Feb 5, 2010 at 11:57 PM, Stefan Weil w...@mail.berlios.de wrote:
Laurent Desnogues schrieb:
[...]
I'm still struggling with bntest and other x86_64-linux-user software
calling any of the vsyscall functions.
Laurent, your vsyscall patch only works on x86_64 hosts.
A lot of software
On Sat, Feb 6, 2010 at 8:49 AM, Stefan Weil w...@mail.berlios.de wrote:
[...]
I tested two different hosts with x86_64-linux-user:
* 32 bit Intel (i386) - does not work with your patch
For me x86_64 on i386 has always failed without
even calling vsyscall :-)
* 64 bit AMD (x86_64) - works
On Sun, Feb 7, 2010 at 1:22 AM, Jamie Lokier ja...@shareable.org wrote:
[...]
How would you achieve that? Your guest OS
doesn't necessarily have the code mapped. I
think this has to be considered as other syscalls,
though slightly different.
There is no guest OS when doing -user
On Fri, Feb 5, 2010 at 4:52 PM, Riku Voipio riku.voi...@iki.fi wrote:
From: Riku Voipio riku.voi...@nokia.com
The rounding/truncating options were inverted. truncating
was done when rounding was meant and vice verse.
Signed-off-by: Riku Voipio riku.voi...@nokia.com
Acked-by: Laurent
juha.riihim...@nokia.com
Signed-off-by: Riku Voipio riku.voi...@nokia.com
Acked-by: Laurent Desnogues laurent.desnog...@gmail.com
Laurent
---
target-arm/translate.c | 1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/target-arm/translate.c b/target-arm/translate.c
On Fri, Feb 5, 2010 at 4:52 PM, Riku Voipio riku.voi...@iki.fi wrote:
From: Juha Riihimäki juha.riihim...@nokia.com
add an extra check in two registers and a shift to ensure element
size decoding logic cannot fail.
Signed-off-by: Juha Riihimäki juha.riihim...@nokia.com
Signed-off-by: Riku
On Sun, Feb 7, 2010 at 1:54 PM, Laurent Desnogues
laurent.desnog...@gmail.com wrote:
On Fri, Feb 5, 2010 at 4:52 PM, Riku Voipio riku.voi...@iki.fi wrote:
From: Juha Riihimäki juha.riihim...@nokia.com
add an extra check in two registers and a shift to ensure element
size decoding logic cannot
On Mon, Feb 8, 2010 at 12:47 PM, Riku Voipio riku.voi...@iki.fi wrote:
On Sun, Feb 07, 2010 at 02:02:31PM +0100, Laurent Desnogues wrote:
On Sun, Feb 7, 2010 at 1:54 PM, Laurent Desnogues
laurent.desnog...@gmail.com wrote:
On Fri, Feb 5, 2010 at 4:52 PM, Riku Voipio riku.voi...@iki.fi wrote
On Wed, Feb 10, 2010 at 10:38 PM, Damion Yates dam...@google.com wrote:
I've grabbed the latest stable qemu and compiled under scratchbox. I
hit an issue compiling it, with no __builtin__clear_cache() so linked in
a kludge.c containing a call to __clear_cache() with the params passed
as they
On Wed, Feb 10, 2010 at 10:38 PM, Damion Yates dam...@google.com wrote:
[...]
Should clone()/fork() work? Has anyone been able to run wine ./blah.exe
under user-linux mode of qemu on arm or indeed any other non x86 based
CPU ?
I forgot to mention NPTL is not supported for x86 which
will be an
On 2/21/08, Andrew Warkentin [EMAIL PROTECTED] wrote:
Why does it matter if it is 64-bit or not? Most programs at the moment
don't benefit from being compiled 64-bit. I don't get the obsession with
64-bitness that most Linux and BSD people seem to have.
I have programs that run
On 2/24/08, claude vittoria [EMAIL PROTECTED] wrote:
So in qemu I don't get the same comportement. The add of lr = pc + 4
gives lr = pc + 8 into qemu.
I think that s-pc += 4 at start of disas_arm_insn alters the result.
Could you confirm ?
0x7caddlr, pc, #4
0x80ldrpc,
On Sat, Jul 11, 2009 at 5:14 PM, Laurent Desnogues
laurent.desnog...@gmail.com wrote:
Hello,
the attached patch implements two of the three x86_64 vsyscall's.
Also attached is a test that demonstrates the issue and hopefully
the fix.
Note there is a trick in there: since vsyscall functions
Hi Edgar,
On Sat, Oct 17, 2009 at 9:57 PM, Edgar E. Iglesias
edgar.igles...@gmail.com wrote:
It feels a bit strange to have the CPU model know about linux vsyscalls.
Did you consider having the linux-user loader pass a qemu version of the
x86_64 vdso to the guest through the auxvector? That
On Sun, Oct 18, 2009 at 4:47 AM, Jamie Lokier ja...@shareable.org wrote:
Laurent Desnogues wrote:
A recent compiler (gcc 4.4.0) produces this code for a statically
compiled program:
005779e0 time:
5779e0: 48 83 ec 08 sub $0x8,%rsp
5779e4: 48 c7 c0 00 04 60
On Sun, Oct 18, 2009 at 5:09 AM, Jamie Lokier ja...@shareable.org wrote:
[...]
Please don't do that. Some code traces instructions through the
vsyscall/vdso page, and will be surprised if a syscall instruction
does not do what's expected based on the registers at that point.
Also I don't
+395,7 @@ uint32_t HELPER(uxtb16)(uint32_t x)
uint32_t HELPER(clz)(uint32_t x)
{
- int count;
- for (count = 32; x; count--)
- x = 1;
- return count;
+ return clz32(x);
}
int32_t HELPER(sdiv)(int32_t num, int32_t den)
--
1.6.1.3
Acked-by: Laurent Desnogues
den)
{
if (den == 0)
return 0;
+ if (num == INT_MIN den == -1)
+ return INT_MIN;
return num / den;
}
--
1.6.1.3
Acked-by: Laurent Desnogues laurent.desnog...@gmail.com
That is provided we accept the behaviour for division by zero is
not strictly conforming
On Thu, Oct 15, 2009 at 11:51 PM, Aurelien Jarno aurel...@aurel32.net wrote:
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
target-arm/translate.c | 4
1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/target-arm/translate.c b/target-arm/translate.c
index
On Mon, Oct 19, 2009 at 8:23 AM, juha.riihim...@nokia.com wrote:
I think I have a couple of other fixes and patches on top of that as
well, but I'd rather wait until you get this bunch committed and then
format the patches against the new mainline so that they apply.
It's already been
juha.riihim...@nokia.com
Acked-by: Laurent Desnogues laurent.desnog...@gmail.com
---
diff --git a/target-arm/translate.c b/target-arm/translate.c
index bda105e..3ea9d51 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -310,22 +310,6 @@ static TCGv_i64 gen_muls_i64_i32(TCGv
On Wed, Oct 21, 2009 at 12:17 PM, juha.riihim...@nokia.com wrote:
Shift immediate value is incorrectly overwritten by a temporary
variable in the processing of NEON vsri, vshl and vsli instructions.
Signed-off-by: Juha Riihimäki juha.riihim...@nokia.com
---
diff --git
On Wed, Oct 21, 2009 at 12:18 PM, juha.riihim...@nokia.com wrote:
Use native rotation if possible instead of a simulated one.
From: Filip Navara filip.nav...@gmail.com
Signed-off-by: Juha Riihimäki juha.riihim...@nokia.com
Acked-by: Laurent Desnogues laurent.desnog...@gmail.com
---
diff
On Mon, Oct 19, 2009 at 1:44 PM, juha.riihim...@nokia.com wrote:
Current ARM translator code has several places where it leaves
temporary TCG variables alive. This patch removes all such instances I
have found so far. Sorry for the mangled inlined patch, the mailserver
I use doesn't like
On Thu, Oct 22, 2009 at 9:33 AM, juha.riihim...@nokia.com wrote:
On Oct 22, 2009, at 10:18, ext Laurent Desnogues wrote:
On Thu, Oct 22, 2009 at 8:49 AM, juha.riihim...@nokia.com wrote:
On Oct 21, 2009, at 13:46, ext Laurent Desnogues wrote:
@@ -4624,31 +4624,31 @@ static int
On Wed, Oct 21, 2009 at 1:01 PM, juha.riihim...@nokia.com wrote:
Current code is broken at least on gcc 4.2, the result of a comparison
-1 = sizeof(type) * 8 results true and causes wrong code path to be
taken. The fix utilizes abs() function where applicable and otherwise
adds a test to
On Wed, Oct 21, 2009 at 12:17 PM, juha.riihim...@nokia.com wrote:
Add support for neon vld1.64 instruction.
From: Riku Voipio riku.voi...@iki.fi
Signed-off-by: Juha Riihimäki juha.riihim...@nokia.com
---
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 3ea9d51..d027572
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