On 19/11/2022 8:28 pm, Dongli Zhang wrote:
This patchset is to fix two svm pmu virtualization bugs.
1. The 1st bug is that "-cpu,-pmu" cannot disable svm pmu virtualization.
To use "-cpu EPYC" or "-cpu host,-pmu" cannot disable the pmu
virtualization. There is still below at the VM linux side .
To remove usages of global smp variables arch by arch,
a bisect friendly way is introduced to initialize struct
CpuTopology with duplicate ones; no semantic changes.
Suggested-by: Igor Mammedov
Suggested-by: Eduardo Habkost
Signed-off-by: Like Xu
---
include/hw/boards.h | 15
Following the replace rules, the global smp variables in hppa/mips/openrisc
/sparc*/xtensa are replaced with smp machine properties. No semantic changes.
Signed-off-by: Like Xu
---
hw/alpha/dp264.c | 1 +
hw/hppa/machine.c | 2 ++
hw/mips/boston.c | 2 +-
hw/mips
Following the replace rules, the global smp variables in riscv
are replaced with smp machine properties. No semantic changes.
Signed-off-by: Like Xu
---
hw/riscv/sifive_e.c| 6 --
hw/riscv/sifive_plic.c | 3 +++
hw/riscv/sifive_u.c| 6 --
hw/riscv/spike.c | 2 ++
hw/riscv
Following the replace rules, the global smp variables in s390x
are replaced with smp machine properties. No semantic changes.
Signed-off-by: Like Xu
---
hw/s390x/s390-virtio-ccw.c | 3 ++-
hw/s390x/sclp.c| 2 +-
target/s390x/cpu.c | 3 +++
target/s390x/excp_helper.c | 5
It's recommended to access smp variables via MachineState
as an incoming parameter. This approach applies on legacy
smbios_*_tables*(), *_machine_reset(), *__hot_add_cpu()
and related *_create_cpu() for later smp variables usages.
Suggested-by: Igor Mammedov
Signed-off-by: Like Xu
---
h
ntext. No semantic changes.
Signed-off-by: Like Xu
---
accel/kvm/kvm-all.c | 4 ++--
backends/hostmem.c | 6 --
cpus.c | 6 --
exec.c | 3 ++-
gdbstub.c| 4
hw/cpu/core.c
Following the replace rules, the global smp variables in arm
are replaced with smp machine properties. The init_cpus() and
xlnx_zynqmp_create_rpu() are refactored to pass MachineState.
No semantic changes.
Signed-off-by: Like Xu
---
hw/arm/fsl-imx6.c | 6 +-
hw/arm/fsl-imx6ul.c
s few calls as possible and delay other related refactoring efforts.
Like Xu (10):
hw/boards: add struct CpuTopology to MachineState
cpu/topology: related call chains refactoring to pass MachineState
cpu/topology: replace global smp variables by MachineState in general path
cpu/topology
Following the replace rules, the global smp variables in ppc
are replaced with smp machine properties. No semantic changes.
Signed-off-by: Like Xu
---
hw/ppc/e500.c | 3 +++
hw/ppc/mac_newworld.c | 3 ++-
hw/ppc/mac_oldworld.c | 3 ++-
hw/ppc/pnv.c | 6 --
hw/ppc/prep.c
: Like Xu
---
hw/arm/vexpress.c | 4 ++--
hw/i386/acpi-build.c | 13 -
hw/i386/kvmvapic.c| 7 +--
hw/i386/pc.c | 24 +++-
hw/i386/xen/xen-hvm.c | 4
target/i386/cpu.c | 4 +++-
6 files changed, 37 insertions(+), 19 deletions
At the end of this smp refactoring series, the global ones are removed
and only smp machine properties are fully applied and enabled.
Signed-off-by: Like Xu
---
vl.c | 53 ++---
1 file changed, 26 insertions(+), 27 deletions(-)
diff --git a/vl.c
On 2019/5/6 16:33, Like Xu wrote:
This patch series make existing cores/threads/sockets into machine
properties and get rid of global smp_* variables they use currently.
The purpose of getting rid of globals is disentangle layer violations and
let's do it one step at a time by replacin
On 2019/6/6 16:20, Greg Kurz wrote:
On Thu, 6 Jun 2019 13:07:32 +1000
David Gibson wrote:
On Wed, Jun 05, 2019 at 11:54:56PM -0300, Eduardo Habkost wrote:
On Wed, Jun 05, 2019 at 11:52:41PM -0300, Eduardo Habkost wrote:
On Sun, May 19, 2019 at 04:54:22AM +0800, Like Xu wrote:
The global
On 2019/6/6 11:32, Eduardo Habkost wrote:
On Tue, May 21, 2019 at 12:50:52AM +0800, Like Xu wrote:
The die-level as the first PC-specific cpu topology is added to the
leagcy cpu topology model which only covers sockets/cores/threads.
In the new model with die-level support, the total number of
configured
again by the last adjusted cpuid_min_level value.
If a user wants to expose CPUID.1F by passing dies > 1 for any reason without
host support, a per-cpu smp topology warning will appear but it's not blocked.
Signed-off-by: Like Xu
---
target/i386/kvm.c | 24 +++
-by: Dr. David Alan Gilbert
Signed-off-by: Like Xu
---
hmp.c | 3 +++
hw/core/machine.c | 12
hw/i386/pc.c | 14 ++
include/hw/i386/topology.h | 2 ++
qapi/misc.json | 6 --
target/i386/cpu.c | 2
called pc_smp_parse() has been added to hw/i386/pc.c, which in
this patch changes nothing against the default one .
Suggested-by: Eduardo Habkost
Signed-off-by: Like Xu
---
hw/core/machine.c| 77
hw/i386/pc.c | 76
d.
Suggested-by: Eduardo Habkost
Signed-off-by: Like Xu
---
hw/i386/pc.c | 16 +++-
1 file changed, 11 insertions(+), 5 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 9e9a42f007..af2e95a1b9 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -1520,12 +1520,16 @@ void pc_acpi_sm
nr_dies
- Based on "[PATCH v3 00/10] Refactor cpu topo into machine properties"
- Rebase to commit 2259637b95bef3116cc262459271de08e038cc66
v1: https://patchwork.kernel.org/cover/10876667/
Like Xu (9):
i386: Add die-level cpu topology to x86CPU on PCMachine
hw/i386: Adjust nr_die
offline) on board will be calculated as:
#cpus = #sockets * #dies * #cores * #threads
and considering compatibility, the default value for #dies would be
initialized to one in x86_cpu_initfn() and pc_machine_initfn().
Signed-off-by: Like Xu
---
hw/i386/pc.c | 9 +++--
include/hw/i386
umber of dies per package is less than 2, the qemu will not
expose CPUID.1F regardless of whether the host supports CPUID.1F.
Signed-off-by: Like Xu
---
target/i386/cpu.c | 37 +
target/i386/cpu.h | 4
target/i386/kvm.c | 12
3 files change
The corresponding topo_bits tests are updated to support die configurations.
Signed-off-by: Like Xu
---
tests/test-x86-cpuid.c | 84 ++
1 file changed, 45 insertions(+), 39 deletions(-)
diff --git a/tests/test-x86-cpuid.c b/tests/test-x86-cpuid.c
index
CPUIDs such as 0x3 for L3 cache should be mapping to die_offset.
Signed-off-by: Like Xu
---
hw/i386/pc.c | 29 ++-
include/hw/i386/topology.h | 76 +++---
target/i386/cpu.c | 13 ---
3 files changed, 81 insertions(+), 37 deletions
computing.
Signed-off-by: Like Xu
---
hw/i386/pc.c| 32 ++--
qemu-options.hx | 17 +
vl.c| 3 +++
3 files changed, 30 insertions(+), 22 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 63b44bd2bd..8a5da4f0c1 100644
--- a/hw/i386/
Hi,
On 2019/8/16 2:38, Eduardo Habkost wrote:
The error message for die-id range validation is incorrect. Example:
$ qemu-system-x86_64 -smp 1,sockets=6,maxcpus=6 \
-device qemu64-x86_64-cpu,socket-id=1,die-id=1,core-id=0,thread-id=0
qemu-system-x86_64: -device
qemu64-x86_64-cpu,so
On 2019/8/16 21:49, Eduardo Habkost wrote:
On Fri, Aug 16, 2019 at 09:04:16AM +0800, Like Xu wrote:
Hi,
On 2019/8/16 2:38, Eduardo Habkost wrote:
The error message for die-id range validation is incorrect. Example:
$ qemu-system-x86_64 -smp 1,sockets=6,maxcpus=6 \
-device qemu64
guest perf performace by LBR MSR
passthrough so it requires guest cpu model matches that of host's, i.e.,
Would you help add live migration support across host/guest CPU models when
hosts at both ends have the same number of LBR entries and the same lbr-fmt ?
Thanks,
Like Xu
only -cpu ho
On 18/7/2022 11:22 am, Zhenzhong Duan wrote:
Since below KVM commit, KVM hided BTS as it's not supported yet.
b9181c8ef356 ("KVM: x86/pmu: Avoid exposing Intel BTS feature")
After below KVM commit, it gave control of MSR_IA32_MISC_ENABLES to userspace.
9fc222967a39 ("KVM: x86: Give host userspac
On 20/7/2022 2:53 am, Sean Christopherson wrote:
On Tue, Jul 19, 2022, Paolo Bonzini wrote:
On 7/18/22 22:12, Sean Christopherson wrote:
On Mon, Jul 18, 2022, Paolo Bonzini wrote:
This needs to be fixed in the kernel because old QEMU/new KVM is supported.
I can't object to adding a quirk for
whether to disable guest pmu using
vm ioctl KVM_CAP_PMU_CAPABILITY. Introducing a new property is not too
acceptable if there are other options.
>
> Cc: Joe Jin
> Cc: Like Xu
> Signed-off-by: Dongli Zhang
> ---
> Changed since v1:
> - In version 1 we did not introduce the new
s (MSR
> c0010200 is 530076)
>
> 5. In a worse case, the active kvm_pmc->perf_event is still able to
> inject unknown NMIs randomly to the VM kernel.
>
> [...] Uhhuh. NMI received for unknown reason 30 on CPU 0.
>
> The patch is to fix the issue by resetting AMD pmu re
I think we've been stuck here too long. Sorry Dongli.
+zhenyu, could you get someone to follow up on this, or I will start working on
that.
On 9/1/2023 9:19 am, Dongli Zhang wrote:
Ping?
About [PATCH v2 2/2], the bad thing is that the customer will not be able to
notice the issue, that is, t
The new generic DEFINE_PROP_BITMASK_UINT64 could be used to ensure
that a user-provided property value complies with its bitmask rule
and the default value is recommended to be set in instance_init().
Signed-off-by: Like Xu
---
hw/core/qdev-properties.c| 19 +++
include/hw
- the user-provided lbr-fmt value should not violate its bitmask (0x3f)
and it should be the same as the host lbr_fmt value or just use the
QEMU option "-cpu host,migratable=no" to enable guest LBR.
Signed-off-by: Like Xu
---
v2-v3 Changelog:
- Add a new generic property macro to valid
When cs->nr_dies is larger than 1, the CPUID.1F should be generated
and is added to cpuid_data.entries for guest awareness. This patch
provides a return option in kvm_has_cpuid_1f for default choice.
Signed-off-by: Like Xu
---
target/i386/kvm.c |
: Like Xu
---
cpus.c| 1 +
include/qom/cpu.h | 1 +
include/sysemu/cpus.h | 1 +
qapi/misc.json| 1 +
target/i386/cpu.h | 5 +
5 files changed, 9 insertions(+)
diff --git a/cpus.c b/cpus.c
index b09b702..503558d 100644
--- a/cpus.c
+++ b/cpus.c
@@ -2066,6
This patch updates the check rules on legeacy -smp parse from user command
and it's designed to obey the same restrictions as socket/core/thread model.
Signed-off-by: Like Xu
---
hmp.c | 3 +++
hw/core/machine.c | 12
vl.c
2 ecx=0x0201 edx=0x0001
0x001f 0x02: eax=0x0002 ebx=0x0004 ecx=0x0502 edx=0x0003
0x001f 0x03: eax=0x ebx=0x ecx=0x0003 edx=0x0001
Like Xu (5):
cpu: introduce die, the new cpu toppolgy emulation level
vl.c: add -smp,dies=* command line su
This patch rewrites the width/offset-apicid calculation with compatibility.
It keeps the original symmetry as a default method and sets the die_id
as well as node_id for leageacy numde_node auto-configuration.
Signed-off-by: Like Xu
---
hw/i386/pc.c | 37
This patch uses the new socket/die/core/thread model to generate
cpuid.1f eax/ebx/ecx/edx values especially the subleaf 2 which
keeps die level information and adds an option in the cpu_x86_cpuid.
Signed-off-by: Like Xu
---
target/i386/cpu.c | 57
On 2019/1/17 2:26, Daniel P. Berrangé wrote:
On Mon, Jan 14, 2019 at 06:51:34PM -0200, Eduardo Habkost wrote:
On Mon, Jan 14, 2019 at 08:24:56PM +0800, Like Xu wrote:
This patch updates the check rules on legeacy -smp parse from user command
and it's designed to obey the same restrictio
On 2019/1/17 22:24, Igor Mammedov wrote:
On Mon, 14 Jan 2019 20:24:54 +0800
Like Xu wrote:
As we know, die is a rectangular piece of a semiconductor wafer. It's very
common
that chip manufacturers put a multi-core die in one package and one die always
has
a one-to-one relationship wit
Anyone to help review this change?
Thanks,
Like Xu
On 2020/3/17 13:54, Like Xu wrote:
In the Intel SDM, "Table 18-2. Association of Fixed-Function
Performance Counters with Architectural Performance Events",
we may have a new fixed counter 'TOPDOWN.SLOTS' (since Icelak
On 2020/3/27 2:48, Paolo Bonzini wrote:
On 17/03/20 06:54, Like Xu wrote:
In the Intel SDM, "Table 18-2. Association of Fixed-Function
Performance Counters with Architectural Performance Events",
we may have a new fixed counter 'TOPDOWN.SLOTS' (since Icelake),
which
arcel Apfelbaum
Cc: Marcelo Tosatti
Cc: qemu-devel@nongnu.org
Signed-off-by: Like Xu
---
hw/i386/pc.c | 1 +
target/i386/cpu.c | 24 ++--
target/i386/cpu.h | 2 ++
target/i386/kvm.c | 7 ++-
4 files changed, 31 insertions(+), 3 deletions(-)
diff --git a/hw/i386
Hi John,
Thanks for your comment.
On 2021/3/5 7:53, John Snow wrote:
On 2/28/21 9:39 PM, Like Xu wrote:
Hi Genius,
I am a user of QEMU v4.2.0 and stuck in an interesting bug, which may
still exist in the mainline.
Thanks in advance to heroes who can take a look and share understanding
- the configured lbr-fmt value is the same as the host lbr_fmt value
or use the QEMU option "-cpu host,migratable=no".
Cc: Eduardo Habkost
Cc: Paolo Bonzini
Signed-off-by: Like Xu
---
target/i386/cpu.c | 16
target/i386/cpu.h | 10 ++
target/i386
Instead of hardcoding the PERF_CAPABILITIES rules in this loop,
this could become a FeatureWordInfo field. It would be very useful
for other features like intel-pt, where we need some bits to match
the host bits too.
Suggested-by: Eduardo Habkost
Signed-off-by: Like Xu
---
target/i386/cpu.c
On 2021/4/26 21:30, Daniel P. Berrangé wrote:
On Mon, Apr 26, 2021 at 10:08:52AM +0800, caodon...@kingsoft.com wrote:
Change the criteria for the initial CPU topology and maxcpus, user can
have more settings
Can you provide a better explanation of why this is needed. What
valid usage scenario
- the configured lbr-fmt value is the same as the host lbr_fmt value
OR use the QEMU option "-cpu host,migratable=no".
Signed-off-by: Like Xu
---
target/i386/cpu.c | 34 ++
target/i386/cpu.h | 10 ++
target/i386/kvm/kvm.c | 10 --
Hi Eduardo,
On 2021/4/24 5:20, Eduardo Habkost wrote:
Hi,
Sorry for missing the previous submission of this series, and
thanks for resubmitting.
Long time no see and thanks for your comments.
On Fri, Apr 23, 2021 at 10:20:36AM +0800, Like Xu wrote:
The last branch recording (LBR) is a
Hi Eduardo,
Thanks for your detailed comments.
On 2021/4/29 5:19, Eduardo Habkost wrote:
On Tue, Apr 27, 2021 at 04:09:48PM +0800, Like Xu wrote:
The last branch recording (LBR) is a performance monitor unit (PMU)
feature on Intel processors that records a running trace of the most
recent
Hi Genius,
I am a user of QEMU v4.2.0 and stuck in an interesting bug, which may still
exist in the mainline.
Thanks in advance to heroes who can take a look and share understanding.
The qemu main thread endlessly hangs in the handle of the qmp statement:
{'execute': 'human-monitor-command', '
Hi Paolo & Eduardo,
Do we have any comment for the QEMU LBR enabling patches?
https://lore.kernel.org/qemu-devel/20210201045453.240258-1-like...@linux.intel.com/
On 2021/2/1 12:54, Like Xu wrote:
The last branch recording (LBR) is a performance monitor unit (PMU)
feature on Intel proces
Eduardo has a suggestion: instead of hardcoding the
PERF_CAPABILITIES rules in this loop, this could become a
FeatureWordInfo field. It would be very useful for other
features like intel-pt, where we need some bits to match the
host too.
Suggested-by: Eduardo Habkost
Signed-off-by: Like Xu
- the configured lbr-fmt value is the same as the host lbr_fmt value
or use the QEMU option "-cpu host,migratable=no".
Cc: Eduardo Habkost
Cc: Paolo Bonzini
Signed-off-by: Like Xu
---
target/i386/cpu.c | 16
target/i386/cpu.h | 10 ++
target/i386
Ping for timely review.
On 2019/6/12 16:40, Like Xu wrote:
Multi-chip packaging technology allows integration of multi-cores in one die
and multi-dies in one single package, for example Intel CLX-AP or AMD EPYC.
This patch series extend the CPU topology to the socket/dies/core/thread model
On 2019/6/20 7:36, Eduardo Habkost wrote:
On Wed, Jun 19, 2019 at 04:15:46PM -0300, Eduardo Habkost wrote:
On Wed, Jun 12, 2019 at 04:41:02PM +0800, Like Xu wrote:
In guest CPUID generation process, the cpuid_min_level would be adjusted to
the maximum passed value for basic CPUID configuration
called pc_smp_parse() has been added to hw/i386/pc.c, which in
this patch changes nothing against the default one .
Suggested-by: Eduardo Habkost
Signed-off-by: Like Xu
Reviewed-by: Eduardo Habkost
---
hw/core/machine.c| 76 ++
hw/i386/pc.c | 79
s://patchwork.kernel.org/cover/10876667/
Like Xu (3):
target/i386: Add CPUID.1F generation support for multi-dies PCMachine
machine: Refactor smp_parse() in vl.c as MachineClass::smp_parse()
vl.c: Add -smp, dies=* command line support and update doc
hw/core/machine.c| 76 +++
computing.
Signed-off-by: Like Xu
---
hw/i386/pc.c| 30 +-
qemu-options.hx | 17 +
vl.c| 3 +++
3 files changed, 29 insertions(+), 21 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 092bd10d4d..2ed1b3f8de 100644
--- a/hw/i386/
umber of dies per package is greater than 1, the cpuid_min_level
would be adjusted to 0x1f regardless of whether the host supports CPUID.1F.
Likewise, the CPUID.1F wouldn't be exposed if env->nr_dies < 2.
Suggested-by: Eduardo Habkost
Signed-off-by: Like Xu
---
target
On 2019/6/20 22:52, Eduardo Habkost wrote:
On Sun, May 19, 2019 at 04:54:23AM +0800, Like Xu wrote:
The global smp variables in riscv are replaced with smp machine properties.
A local variable of the same name would be introduced in the declaration
phase if it's used widely in the conte
it 6017608936 in the kernel tree.
Signed-off-by: Like Xu
---
target/i386/cpu.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 576f309bbf..ec2b67d425 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1185,7 +1185,7 @@ typed
IA32_PERF_CAPABILITIES is enumerated by CPUID.1:ECX[15].
Cc: Paolo Bonzini
Cc: Richard Henderson
Cc: Eduardo Habkost
Cc: Marcelo Tosatti
Cc: qemu-devel@nongnu.org
Signed-off-by: Like Xu
---
target/i386/cpu.c | 29 +
target/i386/cpu.h | 3 +++
target/i386/kvm.c | 20
ent_machine), &error_abort);" in vl.c;
- or in the context with '#ifdef CONFIG_USER_ONLY';
Thanks,
Like Xu
From: Like Xu
If KVM is enabled, use the supported number of address space identifiers
(ASIDs) by the CPUID Fn8000_000A_EBX instead of hard-coding it to 0x10.
Signed-off-by: Like Xu
---
target/i386/cpu.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/target/i386
On 2019/3/29 17:22, Alex Bennée wrote:
Like Xu writes:
Signed-off-by: Like Xu
---
include/hw/arm/virt.h | 2 +-
include/hw/boards.h | 8
include/sysemu/sysemu.h | 2 +-
vl.c| 7 ++-
4 files changed, 16 insertions(+), 3 deletions(-)
diff --git a
On 2019/3/30 7:01, Alistair Francis wrote:
On Fri, Mar 29, 2019 at 1:59 AM Like Xu wrote:
Signed-off-by: Like Xu
---
hw/openrisc/openrisc_sim.c | 1 +
hw/riscv/sifive_e.c| 4
hw/riscv/sifive_plic.c | 3 +++
hw/riscv/sifive_u.c| 4
hw/riscv/spike.c
On 2019/3/29 19:20, Philippe Mathieu-Daudé wrote:
Le ven. 29 mars 2019 10:27, Alex Bennée a écrit :
Like Xu writes:
Signed-off-by: Like Xu
---
hw/arm/fsl-imx6.c | 5 +
hw/arm/fsl-imx6ul.c| 5 +
hw/arm/fsl-imx7.c | 5 +
hw/arm/highbank.c | 1 +
hw/arm
On 2019/3/29 17:27, Alex Bennée wrote:
Like Xu writes:
Signed-off-by: Like Xu
---
hw/arm/fsl-imx6.c | 5 +
hw/arm/fsl-imx6ul.c| 5 +
hw/arm/fsl-imx7.c | 5 +
hw/arm/highbank.c | 1 +
hw/arm/mcimx6ul-evk.c | 1 +
hw/arm/mcimx7d-sabre.c | 3 +++
hw/arm
On 2019/4/2 7:38, Eduardo Habkost wrote:
On Mon, Apr 01, 2019 at 10:56:30AM +0800, Like Xu wrote:
On 2019/3/29 17:27, Alex Bennée wrote:
[...]
@@ -1713,6 +1717,9 @@ static void cortex_a9_initfn(Object *obj)
#ifndef CONFIG_USER_ONLY
static uint64_t a15_l2ctlr_read(CPUARMState *env, const
On 2019/4/2 12:45, Peter Maydell wrote:
On Tue, 2 Apr 2019 at 09:46, Like Xu wrote:
On 2019/4/2 7:38, Eduardo Habkost wrote:
On Mon, Apr 01, 2019 at 10:56:30AM +0800, Like Xu wrote:
On 2019/3/29 17:27, Alex Bennée wrote:
[...]
@@ -1713,6 +1717,9 @@ static void cortex_a9_initfn(Object *obj
This patch makes the remaining dozen or so uses of the global
current_machine outside vl.c use qdev_get_machine() instead,
and then make current_machine local to vl.c instead of global.
Signed-off-by: Like Xu
---
accel/kvm/kvm-all.c | 6 --
device-hotplug.c| 3 ++-
device_tree.c
This patch makes the remaining dozen or so uses of the global
current_machine outside vl.c use qdev_get_machine() instead,
and then make current_machine local to vl.c instead of global.
Signed-off-by: Like Xu
---
Changes in v2:
- make the variable current_machine "static" (T
On 2019/4/2 19:27, Markus Armbruster wrote:
Like Xu writes:
This patch makes the remaining dozen or so uses of the global
current_machine outside vl.c use qdev_get_machine() instead,
and then make current_machine local to vl.c instead of global.
Signed-off-by: Like Xu
You effectively
On 2019/3/29 18:21, Igor Mammedov wrote:
On Fri, 29 Mar 2019 16:48:36 +0800
Like Xu wrote:
This patch series make existing cores/threads/sockets into machine
properties and get rid of global variables they use currently.
Thanks for looking into it!
Its long overdue and rather desired
On 2019/4/3 0:13, Markus Armbruster wrote:
Igor Mammedov writes:
On Tue, 2 Apr 2019 21:09:39 +0800
Like Xu wrote:
On 2019/4/2 19:27, Markus Armbruster wrote:
Like Xu writes:
This patch makes the remaining dozen or so uses of the global
current_machine outside vl.c use
On 2019/4/8 21:26, Igor Mammedov wrote:
On Thu, 4 Apr 2019 11:26:09 +0800
Like Xu wrote:
On 2019/3/29 18:21, Igor Mammedov wrote:
On Fri, 29 Mar 2019 16:48:36 +0800
Like Xu wrote:
This patch series make existing cores/threads/sockets into machine
properties and get rid of global
uot;static" (Thomas Huth)
Like Xu (2):
vl.c: refactor current_machine as non-global variable
core/qdev: refactor qdev_get_machine() with type assertion
accel/kvm/kvm-all.c| 6 --
device-hotplug.c | 3 ++-
device_tree.c | 3 ++-
exec.c | 6 --
To avoid the misuse of qdev_get_machine() if machine hasn't been created yet,
this patch uses qdev_get_machine_uncheck() for obj-common (share with user-only
mode) and adds type assertion to qdev_get_machine() in system-emulation mode.
Suggested-by: Igor Mammedov
Signed-off-by: Like Xu
--
This patch makes the remaining dozen or so uses of the global
current_machine outside vl.c use qdev_get_machine() instead,
and then make current_machine local to vl.c instead of global.
Suggested-by: Peter Maydell
Signed-off-by: Like Xu
---
accel/kvm/kvm-all.c | 6 --
device-hotplug.c
On 2019/5/19 4:54, Like Xu wrote:
This patch series make existing cores/threads/sockets into machine
properties and get rid of global smp_* variables they use currently.
The purpose of getting rid of globals is disentangle layer violations and
let's do it one step at a time by replacin
On 2019/5/22 1:12, Dr. David Alan Gilbert wrote:
* Like Xu (like...@linux.intel.com) wrote:
Following the legacy smp check rules, the die_id validity is added to
the same contexts as leagcy smp variables such as hmp_hotpluggable_cpus(),
machine_set_cpu_numa_node(), cpu_slot_to_string() and
Ping for [PATCH v3 00/10] Refactor cpu topo into machine properties.
On 2019/5/26 21:51, Like Xu wrote:
On 2019/5/19 4:54, Like Xu wrote:
This patch series make existing cores/threads/sockets into machine
properties and get rid of global smp_* variables they use currently.
The purpose of
netperf TCP STREAM guest to host - no regression
Contact: MST
---
I am trying to make some contributions to improving netperf TCP_RR.
Could you please share more ideas or plans or implemental details to
make it happen?
Thanks,
Like Xu
On 2019/7/11 21:05, Alex Bennée wrote:
Commit a5e0b3311 removed these in favour of querying machine
properties. Remove the extern declarations as well.
Signed-off-by: Alex Bennée
Cc: Like Xu
Reviewed-by: Like Xu
---
include/sysemu/sysemu.h | 2 --
1 file changed, 2 deletions(-)
diff
Signed-off-by: Like Xu
---
.gitignore | 1 +
docs/COLO-FT.txt | 2 +-
docs/amd-memory-encryption.txt | 2 +-
docs/can.txt | 2 +-
docs/colo-proxy.txt| 6 +++---
docs/cpu-hotplug.rst | 2 +-
docs/qcow2-cache.txt
Signed-off-by: Like Xu
---
docs/COLO-FT.txt | 2 +-
docs/amd-memory-encryption.txt | 2 +-
docs/can.txt | 2 +-
docs/colo-proxy.txt| 6 +++---
docs/cpu-hotplug.rst | 2 +-
docs/qcow2-cache.txt | 2 +-
docs/qemu-block-drivers.texi
On 2019/2/20 11:09, Eric Blake wrote:
On 2/20/19 2:55 AM, Like Xu wrote:
Signed-off-by: Like Xu
This feels like two independent patches - the .gitignore change is
different from typo fixes.
Actually, for .gitignore, you could just as easily do:
echo '*.patch' >> .git/info/
On 2019/2/19 17:02, Gerd Hoffmann wrote:
What happens if you remove "try-alsa" from the configure line?
This issue could be fixed by passing "export QEMU_AUDIO_DRV=none" to
shell env when alsa support form host kernel is unavailable.
I would work around this issue
by applying "export QEMU_AUDIO_DRV=none" to shell before we run the qemu
command.
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1816052
Title:
qemu system emulator f
On 2019/4/8 20:54, Igor Mammedov wrote:
On Fri, 29 Mar 2019 16:48:39 +0800
Like Xu wrote:
here should be a commit message explaining what patch does
in more detail.
Signed-off-by: Like Xu
Generic note, try not call qdev_get_machine() every time
you replace smp_cpus or other variables
On 2019/4/18 1:10, Eduardo Habkost wrote:
On Wed, Apr 17, 2019 at 07:14:10AM +0200, Markus Armbruster wrote:
Eduardo Habkost writes:
On Mon, Apr 15, 2019 at 03:59:45PM +0800, Like Xu wrote:
To avoid the misuse of qdev_get_machine() if machine hasn't been created yet,
this patch
On 2019/4/25 1:21, Eduardo Habkost wrote:
On Tue, Apr 23, 2019 at 03:59:31PM +0800, Like Xu wrote:
On 2019/4/18 1:10, Eduardo Habkost wrote:
On Wed, Apr 17, 2019 at 07:14:10AM +0200, Markus Armbruster wrote:
Eduardo Habkost writes:
On Mon, Apr 15, 2019 at 03:59:45PM +0800, Like Xu wrote
On 2019/4/26 4:00, Eduardo Habkost wrote:
This series moves some qdev code outside qdev.o, so it can be
compiled only in CONFIG_SOFTMMU.
The code being moved includes two qdev_get_machine() calls, so
this will make it easier to move qdev_get_machine() to
CONFIG_SOFTMMU later.
After this series,
On 2019/4/4 22:25, Igor Mammedov wrote:
On Fri, 29 Mar 2019 16:48:38 +0800
Like Xu wrote:
diff --git a/cpus.c b/cpus.c
index e83f72b..834a697 100644
--- a/cpus.c
+++ b/cpus.c
@@ -2067,6 +2067,10 @@ static void qemu_dummy_start_vcpu(CPUState *cpu)
void qemu_init_vcpu(CPUState *cpu
Suggested-by: Igor Mammedov
Signed-off-by: Like Xu
---
hw/arm/fsl-imx6.c | 13 +++--
hw/arm/fsl-imx6ul.c | 12 ++--
hw/arm/fsl-imx7.c | 15 +++
3 files changed, 20 insertions(+), 20 deletions(-)
diff --git a/hw/arm/fsl-imx6.c b/hw/arm/fsl-imx6.c
index 7b7b97f..1
Signed-off-by: Like Xu
---
hw/s390x/s390-virtio-ccw.c | 2 ++
hw/s390x/sclp.c | 1 +
target/openrisc/sys_helper.c | 5 +
target/s390x/cpu.c | 3 +++
target/s390x/excp_helper.c | 6 ++
5 files changed, 17 insertions(+)
diff --git a/hw/s390x/s390-virtio-ccw.c b
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