Re: [Qemu-devel] [sw-dev] RFC: QEMU RISC-V modular ISA decoding

2017-07-26 Thread Michael Clark
> On 27 Jul 2017, at 8:58 AM, kr...@berkeley.edu wrote: > > > Given that one of the goals of RISC-V is extensibility, it would be > nice if the QEMU port was done in a way to make it easier to extend by > third parties, including other automated tools. I'm sure that, over > time, the

Re: [Qemu-devel] [PATCH v8 11/35] RISC-V: Mark ROM read-only after copying in code

2018-05-04 Thread Michael Clark
On Sat, May 5, 2018 at 11:54 AM, Alistair Francis <alistai...@gmail.com> wrote: > On Fri, May 4, 2018 at 4:44 PM Alistair Francis <alistai...@gmail.com> > wrote: > > > On Thu, May 3, 2018 at 6:45 PM Michael Clark <m...@sifive.com> wrote: > > > >

Re: [Qemu-devel] [PATCH v1 1/4] hw/riscv/sifive_u: Create a U54 SoC object

2018-05-04 Thread Michael Clark
On Sat, May 5, 2018 at 8:12 AM, Alistair Francis wrote: > Create a SiFive Unleashed U54 SoC and use that in the sifive_u machine. > > We leave the SoC, RAM, device tree and reset/fdt loading as part of the > machine. All the other device creation has been moved to the

Re: [Qemu-devel] [PULL 0/3] RISC-V: QEMU 2.13 Minor Fixes

2018-05-08 Thread Michael Clark
On Wed, May 9, 2018 at 8:49 AM, Peter Maydell <peter.mayd...@linaro.org> wrote: > On 8 May 2018 at 21:07, Michael Clark <m...@sifive.com> wrote: > > The following changes since commit c8b7e627b4269a3bc3ae41d9f42054 > 7a47e6d9b9: > > > > Merge remote-tracking

[Qemu-devel] [PULL 1/3] riscv: spike: allow base == 0

2018-05-08 Thread Michael Clark
From: KONRAD Frederic <frederic.kon...@adacore.com> The sanity check on base doesn't allow htif to be mapped @0. Check if the symbol exists instead so we can map it where we want. Reviewed-by: Michael Clark <m...@sifive.com> Signed-off-by: KONRAD Frederic <frederic.kon...@adacore.

Re: [Qemu-devel] [PULL 0/3] RISC-V: QEMU 2.13 Minor Fixes

2018-05-08 Thread Michael Clark
On Wed, May 9, 2018 at 4:05 AM, Peter Maydell <peter.mayd...@linaro.org> wrote: > On 8 May 2018 at 00:14, Michael Clark <m...@sifive.com> wrote: > > The following changes since commit c8b7e627b4269a3bc3ae41d9f42054 > 7a47e6d9b9: > > > > Merge remote-tracking

[Qemu-devel] [PULL 2/3] riscv: htif: increase the priority of the htif subregion

2018-05-08 Thread Michael Clark
00-0200 (prio 0, i/o): riscv.sifive.clint 8000-87ff (prio 0, ram): riscv.spike.ram Reviewed-by: Michael Clark <m...@sifive.com> Signed-off-by: KONRAD Frederic <frederic.kon...@adacore.com> Signed-off-by: Michael Clark <m...@sifive.com> Message-Id:

Re: [Qemu-devel] [PATCH] RISC-V: Remove unnecessary header include

2018-05-08 Thread Michael Clark
On Wed, May 9, 2018 at 2:42 AM, Philippe Mathieu-Daudé <f4...@amsat.org> wrote: > Signed-off-by: Philippe Mathieu-Daudé <f4...@amsat.org> > Reviewed-by: Michael Clark <m...@sifive.com> --- > hw/riscv/riscv_htif.c | 1 - > hw/riscv/sifive_e.c | 1 - > hw/ris

[Qemu-devel] [PULL 3/3] riscv: requires libfdt

2018-05-08 Thread Michael Clark
rned 1 exit status make[1]: *** [qemu-system-riscv64] Error 1 make: *** [subdir-riscv64-softmmu] Error 2 Reviewed-by: Bastian Koppelmann <kbast...@mail.uni-paderborn.de> Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org> Reviewed-by: Michael Clark <m...@sifive.com> Signed

[Qemu-devel] [PULL 0/3] RISC-V: QEMU 2.13 Minor Fixes

2018-05-08 Thread Michael Clark
The following changes since commit c8b7e627b4269a3bc3ae41d9f420547a47e6d9b9: Merge remote-tracking branch 'remotes/ericb/tags/pull-nbd-2018-05-04' into staging (2018-05-04 14:42:46 +0100) are available in the git repository at: https://github.com/riscv/riscv-qemu.git

Re: [Qemu-devel] [PULL 00/20] RISC-V: QEMU 2.13 Privileged ISA emulation updates

2018-05-08 Thread Michael Clark
On Wed, May 9, 2018 at 1:22 AM, Peter Maydell <peter.mayd...@linaro.org> wrote: > On 6 May 2018 at 00:35, Michael Clark <m...@sifive.com> wrote: > > The following changes since commit c8b7e627b4269a3bc3ae41d9f42054 > 7a47e6d9b9: > > > > Merge remote-tracking

[Qemu-devel] [PULL 2/3] riscv: htif: increase the priority of the htif subregion

2018-05-07 Thread Michael Clark
00-0200 (prio 0, i/o): riscv.sifive.clint 8000-87ff (prio 0, ram): riscv.spike.ram Reviewed-by: Michael Clark <m...@sifive.com> Signed-off-by: KONRAD Frederic <frederic.kon...@adacore.com> Message-Id: <1525360636-18229-3-git-send-email-frederic.kon...

[Qemu-devel] [PULL 1/3] riscv: spike: allow base == 0

2018-05-07 Thread Michael Clark
From: KONRAD Frederic <frederic.kon...@adacore.com> The sanity check on base doesn't allow htif to be mapped @0. Check if the symbol exists instead so we can map it where we want. Reviewed-by: Michael Clark <m...@sifive.com> Signed-off-by: KONRAD Frederic <frederic.kon...@adacor

[Qemu-devel] [PULL 0/3] RISC-V: QEMU 2.13 Minor Fixes

2018-05-07 Thread Michael Clark
The following changes since commit c8b7e627b4269a3bc3ae41d9f420547a47e6d9b9: Merge remote-tracking branch 'remotes/ericb/tags/pull-nbd-2018-05-04' into staging (2018-05-04 14:42:46 +0100) are available in the git repository at: https://github.com/riscv/riscv-qemu.git

[Qemu-devel] [PULL 3/3] riscv: requires libfdt

2018-05-07 Thread Michael Clark
rned 1 exit status make[1]: *** [qemu-system-riscv64] Error 1 make: *** [subdir-riscv64-softmmu] Error 2 Reviewed-by: Bastian Koppelmann <kbast...@mail.uni-paderborn.de> Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org> Reviewed-by: Michael Clark <m...@sifive.com> Signed

[Qemu-devel] [PATCH v1] RISC-V: Add misa to DisasContext

2018-05-09 Thread Michael Clark
aderborn.de> Cc: Alistair Francis <alistair.fran...@wdc.com> Cc: Emilio G. Cota <c...@braap.org> Signed-off-by: Michael Clark <m...@sifive.com> --- target/riscv/translate.c | 74 ++-- 1 file changed, 40 insertions(+), 34 deletions(-) d

Re: [Qemu-devel] [PATCH 18/18] target/riscv: convert to TranslatorOps

2018-05-09 Thread Michael Clark
On Sat, Apr 21, 2018 at 6:55 AM, Emilio G. Cota <c...@braap.org> wrote: > Reviewed-by: Richard Henderson <richard.hender...@linaro.org> > Cc: Michael Clark <m...@sifive.com> > Cc: Palmer Dabbelt <pal...@sifive.com> > Cc: Sagar Karandikar <sag...@eecs.berkel

[Qemu-devel] [PATCH v1 2/6] translator: merge max_insns into DisasContextBase

2018-05-09 Thread Michael Clark
From: "Emilio G. Cota" While at it, use int for both num_insns and max_insns to make sure we have same-type comparisons. Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota --- accel/tcg/translator.c | 21

[Qemu-devel] [PULL 3/3] riscv: requires libfdt

2018-05-09 Thread Michael Clark
rned 1 exit status make[1]: *** [qemu-system-riscv64] Error 1 make: *** [subdir-riscv64-softmmu] Error 2 Cc: qemu-sta...@nongnu.org Reviewed-by: Bastian Koppelmann <kbast...@mail.uni-paderborn.de> Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org> Reviewed-by: Michael Clark <m...@s

Re: [Qemu-devel] [PATCH 01/18] translator: merge max_insns into DisasContextBase

2018-05-09 Thread Michael Clark
lio G. Cota <c...@braap.org> > Reviewed-by: Michael Clark <m...@sifive.com> > --- > accel/tcg/translator.c | 21 ++--- > include/exec/translator.h | 8 > target/alpha/translate.c | 6 ++ > target/arm/translate-a64.c | 8 +++- &g

[Qemu-devel] [PATCH v1 4/6] target/riscv: convert to DisasContextBase

2018-05-09 Thread Michael Clark
>cflags readers to tb_cflags(). Reviewed-by: Richard Henderson <richard.hender...@linaro.org> Cc: Michael Clark <m...@sifive.com> Cc: Palmer Dabbelt <pal...@sifive.com> Cc: Sagar Karandikar <sag...@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbast...@mail.uni-p

[Qemu-devel] [PATCH v1 3/6] target/riscv: convert to DisasJumpType

2018-05-09 Thread Michael Clark
From: "Emilio G. Cota" <c...@braap.org> Reviewed-by: Bastian Koppelmann <kbast...@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <richard.hender...@linaro.org> Cc: Michael Clark <m...@sifive.com> Cc: Palmer Dabbelt <pal...@sifive.com> Cc: Sagar

[Qemu-devel] [PULL 1/3] riscv: spike: allow base == 0

2018-05-09 Thread Michael Clark
From: KONRAD Frederic <frederic.kon...@adacore.com> The sanity check on base doesn't allow htif to be mapped @0. Check if the symbol exists instead so we can map it where we want. Reviewed-by: Michael Clark <m...@sifive.com> Signed-off-by: KONRAD Frederic <frederic.kon...@adacore.

[Qemu-devel] [PULL 2/3] riscv: htif: increase the priority of the htif subregion

2018-05-09 Thread Michael Clark
00-0200 (prio 0, i/o): riscv.sifive.clint 8000-87ff (prio 0, ram): riscv.spike.ram Reviewed-by: Michael Clark <m...@sifive.com> Signed-off-by: KONRAD Frederic <frederic.kon...@adacore.com> Signed-off-by: Michael Clark <m...@sifive.com> Message-Id:

[Qemu-devel] [PULL 0/3] RISC-V: QEMU 2.13 Minor Fixes

2018-05-09 Thread Michael Clark
The following changes since commit c8b7e627b4269a3bc3ae41d9f420547a47e6d9b9: Merge remote-tracking branch 'remotes/ericb/tags/pull-nbd-2018-05-04' into staging (2018-05-04 14:42:46 +0100) are available in the git repository at: https://github.com/riscv/riscv-qemu.git

[Qemu-devel] [PATCH v1 0/6] Translation loop conversion for riscv

2018-05-09 Thread Michael Clark
Cc: Bastian Koppelmann <kbast...@mail.uni-paderborn.de> Cc: Alistair Francis <alistair.fran...@wdc.com> Cc: Emilio G. Cota <c...@braap.org> Signed-off-by: Michael Clark <m...@sifive.com> Emilio G. Cota (5): target/riscv: avoid integer overflow in next_page PC

[Qemu-devel] [PATCH v1 1/6] target/riscv: avoid integer overflow in next_page PC check

2018-05-09 Thread Michael Clark
viewed-by: Richard Henderson <richard.hender...@linaro.org> Reviewed-by: Michael Clark <m...@sifive.com> Acked-by: Bastian Koppelmann <kbast...@mail.uni-paderborn.de> Cc: Michael Clark <m...@sifive.com> Cc: Palmer Dabbelt <pal...@sifive.com> Cc: Sagar Karandikar <sag...

[Qemu-devel] [PATCH v1 6/6] target/riscv: add misa to DisasContext

2018-05-09 Thread Michael Clark
keley.edu> Cc: Bastian Koppelmann <kbast...@mail.uni-paderborn.de> Cc: Alistair Francis <alistair.fran...@wdc.com> Cc: Emilio G. Cota <c...@braap.org> Signed-off-by: Michael Clark <m...@sifive.com> --- target/riscv/translate.c | 77 ++-

[Qemu-devel] [PATCH v1 5/6] target/riscv: convert to TranslatorOps

2018-05-09 Thread Michael Clark
From: "Emilio G. Cota" <c...@braap.org> Reviewed-by: Richard Henderson <richard.hender...@linaro.org> Cc: Michael Clark <m...@sifive.com> Cc: Palmer Dabbelt <pal...@sifive.com> Cc: Sagar Karandikar <sag...@eecs.berkeley.edu> Cc: Bastian Koppelmann <

Re: [Qemu-devel] [PATCH 00/10] Avoid integer overflow in next_page_start

2018-05-08 Thread Michael Clark
On Thu, Apr 12, 2018 at 11:56 AM, Richard Henderson < richard.hender...@linaro.org> wrote: > On 04/12/2018 01:29 AM, Emilio G. Cota wrote: > > To ease an eventual merge I'll be updating the patches' R-b tags as > > they come in this branch: > >

Re: [Qemu-devel] [PULL 0/3] RISC-V: QEMU 2.13 Minor Fixes

2018-05-09 Thread Michael Clark
On Wed, 9 May 2018 at 11:14 PM, Peter Maydell <peter.mayd...@linaro.org> wrote: > On 8 May 2018 at 23:05, Michael Clark <m...@sifive.com> wrote: > > > > > > On Wed, May 9, 2018 at 8:49 AM, Peter Maydell <peter.mayd...@linaro.org> > > wrote: >

Re: [Qemu-devel] [PATCH v8 22/35] RISC-V: Use atomic_cmpxchg to update PLIC bitmaps

2018-04-27 Thread Michael Clark
On Fri, Apr 27, 2018 at 12:14 PM, Richard Henderson < richard.hender...@linaro.org> wrote: > On 04/25/2018 01:45 PM, Michael Clark wrote: > > +uint32_t old, new; > > +do { > > +old = atomic_read(>pending[word]); > > +new = (old &

Re: [Qemu-devel] [PATCH 5/9] target/riscv: Use new atomic min/max expanders

2018-04-27 Thread Michael Clark
On Fri, Apr 27, 2018 at 12:26 PM, Richard Henderson < richard.hender...@linaro.org> wrote: > Cc: Michael Clark <m...@sifive.com> > Cc: Palmer Dabbelt <pal...@sifive.com> > Cc: Sagar Karandikar <sag...@eecs.berkeley.edu> > Cc: Bastian Koppelmann <kbast

Re: [Qemu-devel] [PATCH v2 1/7] hw/riscv/sifive_u: Create a U54 SoC object

2018-05-12 Thread Michael Clark
lace the prefix "riscv_sifive_u54" to "riscv_sifive_u_soc" - Rename TYPE_RISCV_U54_SOC to TYPE_RISCV_U_SOC - Rename SiFiveU54State SiFiveUSOC (I don't think we need the State suffix for the SOC) Assuming we can do the renames to keep the SiFive U Series machine/SOC general: Reviewed-by: Michae

Re: [Qemu-devel] [PATCH v2 7/7] hw/riscv/sifive_u: Connect the Cadence GEM Ethernet device

2018-05-12 Thread Michael Clark
On Sat, May 12, 2018 at 11:28 AM, Alistair Francis <alistair.fran...@wdc.com > wrote: > Connect the Cadence GEM ethernet device. This also requires us to > expose the plic interrupt lines. > > Signed-off-by: Alistair Francis <alistair.fran...@wdc.com> > Re

Re: [Qemu-devel] [PATCH v2 5/7] hw/riscv/sifive_u: Set the interrupt controler number of interrupts

2018-05-12 Thread Michael Clark
iscv/virt.c we have removed hardcoding a few more constants using in the device tree. e.g. we allocate and resolve phandles vs hardcoding them. We can alwauys make a follow up commits to move some of these magic numbers into constants in the headers, preferably with enum vs #define. Re

Re: [Qemu-devel] [PATCH v2 6/7] hw/riscv/sifive_u: Move the uart device tree node under /soc/

2018-05-12 Thread Michael Clark
On Sat, May 12, 2018 at 11:28 AM, Alistair Francis <alistair.fran...@wdc.com > wrote: > Signed-off-by: Alistair Francis <alistair.fran...@wdc.com> > Reviewed-by: Michael Clark <m...@sifive.com> > --- > hw/riscv/sifive_u.c | 2 +- > 1 file changed, 1 insertion

Re: [Qemu-devel] [PATCH v2 20/27] target/riscv: Remove floatX_maybe_silence_nan from conversions

2018-05-12 Thread Michael Clark
On Sat, May 12, 2018 at 12:43 PM, Richard Henderson < richard.hender...@linaro.org> wrote: > This is now handled properly by the generic softfloat code. > > Cc: Michael Clark <m...@sifive.com> > Cc: Palmer Dabbelt <pal...@sifive.com> > Cc: Sagar Karandikar <sag

[Qemu-devel] [PULL 02/20] RISC-V: Make virt board description match spike

2018-05-05 Thread Michael Clark
This makes 'qemu-system-riscv64 -machine help' output more tidy and consistent. Cc: Sagar Karandikar <sag...@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbast...@mail.uni-paderborn.de> Signed-off-by: Michael Clark <m...@sifive.com> Signed-off-by: Palmer Dabbelt <pal...

[Qemu-devel] [PULL 01/20] RISC-V: Replace hardcoded constants with enum values

2018-05-05 Thread Michael Clark
The RISC-V device-tree code has a number of hard-coded constants and this change moves them into header enums. Cc: Sagar Karandikar <sag...@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbast...@mail.uni-paderborn.de> Signed-off-by: Michael Clark <m...@sifive.com> Signed-off-by: P

[Qemu-devel] [PULL 00/20] RISC-V: QEMU 2.13 Privileged ISA emulation updates

2018-05-05 Thread Michael Clark
ups * Replacing hard-coded constants with enums * Dead-code elimination This is an incremental pull that contains 20 reviewed changes out of 38 changes currently queued in the qemu-2.13-for-upstream branch. ---- Michael Clark

[Qemu-devel] [PULL 09/20] RISC-V: Make virt header comment title consistent

2018-05-05 Thread Michael Clark
Cc: Sagar Karandikar <sag...@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbast...@mail.uni-paderborn.de> Signed-off-by: Michael Clark <m...@sifive.com> Signed-off-by: Palmer Dabbelt <pal...@sifive.com> Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org>

[Qemu-devel] [PULL 12/20] RISC-V: Update E and I extension order

2018-05-05 Thread Michael Clark
.@wdc.com> Signed-off-by: Michael Clark <m...@sifive.com> Reviewed-by: Alistair Francis <alistair.fran...@wdc.com> --- target/riscv/cpu.c | 2 +- target/riscv/cpu.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 5a527fbba0

[Qemu-devel] [PULL 17/20] RISC-V: Add mcycle/minstret support for -icount auto

2018-05-05 Thread Michael Clark
instructions will return the instruction count. Cc: Sagar Karandikar <sag...@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbast...@mail.uni-paderborn.de> Cc: Palmer Dabbelt <pal...@sifive.com> Cc: Alistair Francis <alistair.fran...@wdc.com> Signed-off-by: Michael Clark &l

[Qemu-devel] [PULL 19/20] RISC-V: No traps on writes to misa, minstret, mcycle

2018-05-05 Thread Michael Clark
rn.de> Cc: Palmer Dabbelt <pal...@sifive.com> Cc: Alistair Francis <alistair.fran...@wdc.com> Signed-off-by: Michael Clark <m...@sifive.com> --- target/riscv/op_helper.c | 25 + 1 file changed, 13 insertions(+), 12 deletions(-) diff --git a/target/ri

Re: [Qemu-devel] [PATCH] device_tree: Add qemu_fdt_totalsize function

2018-05-05 Thread Michael Clark
t_resize(void *fdt, void *buf, int bufsize) { ... headsize = fdt_off_dt_struct(fdt); tailsize = fdt_size_dt_strings(fdt); if ((headsize + tailsize) > bufsize) return -FDT_ERR_NOSPACE; ... return 0; } > > > thanks > > -- PMM > > > > On 4 May 2018 at 02:19, Michael Clark &

[Qemu-devel] [PULL 07/20] RISC-V: Fix missing break statement in disassembler

2018-05-05 Thread Michael Clark
r.fran...@wdc.com> Cc: Peter Maydell <peter.mayd...@linaro.org> Signed-off-by: Michael Clark <m...@sifive.com> Reviewed-by: Richard Henderson <richard.hender...@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org> --- disas/riscv.c | 3 ++- 1 file changed, 2

[Qemu-devel] [PULL 20/20] RISC-V: Mark ROM read-only after copying in code

2018-05-05 Thread Michael Clark
; Cc: Palmer Dabbelt <pal...@sifive.com> Cc: Alistair Francis <alistair.fran...@wdc.com> Signed-off-by: Michael Clark <m...@sifive.com> Reviewed-by: Alistair Francis <alistair.fran...@wdc.com> --- hw/riscv/sifive_e.c | 20 +++- hw/riscv/sifive_u.c | 51 +

[Qemu-devel] [PULL 16/20] RISC-V: Use [ms]counteren CSRs when priv ISA >= v1.10

2018-05-05 Thread Michael Clark
t; Cc: Palmer Dabbelt <pal...@sifive.com> Cc: Alistair Francis <alistair.fran...@wdc.com> Signed-off-by: Michael Clark <m...@sifive.com> --- target/riscv/cpu.h | 6 ++--- target/riscv/op_helper.c | 62 +--- 2 files changed, 50 ins

[Qemu-devel] [PULL 11/20] RISC-V: Remove erroneous comment from translate.c

2018-05-05 Thread Michael Clark
Cc: Sagar Karandikar <sag...@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbast...@mail.uni-paderborn.de> Cc: Palmer Dabbelt <pal...@sifive.com> Cc: Alistair Francis <alistair.fran...@wdc.com> Signed-off-by: Michael Clark <m...@sifive.com> Reviewed-by: Palmer Dabbel

[Qemu-devel] [PULL 15/20] RISC-V: Allow S-mode mxr access when priv ISA >= v1.10

2018-05-05 Thread Michael Clark
: Bastian Koppelmann <kbast...@mail.uni-paderborn.de> Cc: Palmer Dabbelt <pal...@sifive.com> Cc: Alistair Francis <alistair.fran...@wdc.com> Signed-off-by: Michael Clark <m...@sifive.com> Reviewed-by: Alistair Francis <alistair.fran...@wdc.com> --- target/riscv/op_

Re: [Qemu-devel] [PATCH] device_tree: Add qemu_fdt_totalsize function

2018-05-05 Thread Michael Clark
FYI - I've dropped this patch to qemu/include/sysemu/device_tree.h and qemu/device_tree.c in favor of calling fdt_pack() and fdt_totalsize(). On Sun, May 6, 2018 at 9:59 AM, Michael Clark <m...@sifive.com> wrote: > > > On Sat, May 5, 2018 at 11:48 PM, David Gibson <da...@gib

[Qemu-devel] [PULL 03/20] RISC-V: Use ROM base address and size from memmap

2018-05-05 Thread Michael Clark
Another case of replacing hard coded constants, this time referring to the definition in the virt machine's memmap. Cc: Sagar Karandikar <sag...@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbast...@mail.uni-paderborn.de> Signed-off-by: Michael Clark <m...@sifive.com> Signed-off-

[Qemu-devel] [PULL 04/20] RISC-V: Remove identity_translate from load_elf

2018-05-05 Thread Michael Clark
; Signed-off-by: Michael Clark <m...@sifive.com> Signed-off-by: Palmer Dabbelt <pal...@sifive.com> Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org> Reviewed-by: Alistair Francis <alistair.fran...@wdc.com> --- hw/riscv/sifive_e.c | 7 +-- hw/riscv/sifive_u.c

[Qemu-devel] [PULL 05/20] RISC-V: Remove unused class definitions

2018-05-05 Thread Michael Clark
unnecessary. Cc: Sagar Karandikar <sag...@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbast...@mail.uni-paderborn.de> Signed-off-by: Michael Clark <m...@sifive.com> Signed-off-by: Palmer Dabbelt <pal...@sifive.com> Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org>

[Qemu-devel] [PULL 08/20] RISC-V: Make some header guards more specific

2018-05-05 Thread Michael Clark
Cc: Sagar Karandikar <sag...@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbast...@mail.uni-paderborn.de> Signed-off-by: Michael Clark <m...@sifive.com> Signed-off-by: Palmer Dabbelt <pal...@sifive.com> Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org>

[Qemu-devel] [PULL 06/20] RISC-V: Include instruction hex in disassembly

2018-05-05 Thread Michael Clark
This was added to help debug issues using -d in_asm. It is useful to see the instruction bytes, as one can detect if one is trying to execute ASCII or device-tree magic. Cc: Sagar Karandikar <sag...@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbast...@mail.uni-paderborn.de> Signed-off

[Qemu-devel] [PULL 14/20] RISC-V: Clear mtval/stval on exceptions without info

2018-05-05 Thread Michael Clark
sag...@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbast...@mail.uni-paderborn.de> Cc: Palmer Dabbelt <pal...@sifive.com> Cc: Alistair Francis <alistair.fran...@wdc.com> Signed-off-by: Michael Clark <m...@sifive.com> Reviewed-by: Alistair Francis <alistair.fran...@wdc.com> --- t

[Qemu-devel] [PULL 10/20] RISC-V: Remove EM_RISCV ELF_MACHINE indirection

2018-05-05 Thread Michael Clark
Pointless indirection. Other ports use EM_ constants directly. Cc: Sagar Karandikar <sag...@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbast...@mail.uni-paderborn.de> Signed-off-by: Michael Clark <m...@sifive.com> Signed-off-by: Palmer Dabbelt <pal...@sifive.com> Revie

[Qemu-devel] [PULL 18/20] RISC-V: Make mtvec/stvec ignore vectored traps

2018-05-05 Thread Michael Clark
) fields is to drop writes to unsupported bits. Cc: Sagar Karandikar <sag...@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbast...@mail.uni-paderborn.de> Cc: Palmer Dabbelt <pal...@sifive.com> Cc: Alistair Francis <alistair.fran...@wdc.com> Signed-off-by: Michael Clark <m

[Qemu-devel] [PULL 13/20] RISC-V: Hardwire satp to 0 for no-mmu case

2018-05-05 Thread Michael Clark
and more complex trap handling code). Cc: Sagar Karandikar <sag...@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbast...@mail.uni-paderborn.de> Cc: Palmer Dabbelt <pal...@sifive.com> Cc: Alistair Francis <alistair.fran...@wdc.com> Signed-off-by: Michael Clark <m...@sifive

Re: [Qemu-devel] [PATCH 4/9] target/riscv: Introduce cpu_riscv_get_fcsr

2018-05-17 Thread Michael Clark
On Fri, May 11, 2018 at 3:52 PM, Richard Henderson < richard.hender...@linaro.org> wrote: > Cc: Michael Clark <m...@sifive.com> > Cc: Palmer Dabbelt <pal...@sifive.com> > Cc: Sagar Karandikar <sag...@eecs.berkeley.edu> > Cc: Bastian Koppelmann <kbast

Re: [Qemu-devel] [PATCH] RISC-V: make it possible to alter default reset vector

2018-05-17 Thread Michael Clark
rt in a SiFive tree. I'll leave the RFC proper for another email. This is just an abstract. BTW - there are plently of others you can get to accept this patch ;-) See the 'Cc. Signed-off-by: Antony Pavlov <antonynpav...@gmail.com> > Cc: Michael Clark <m...@sifive.com> > Cc: Palmer Dabbel

[Qemu-devel] [PATCH v1 16/30] RISC-V: Use riscv prefix consistently on cpu helpers

2018-05-22 Thread Michael Clark
riscv_set_mode to riscv_cpu_set_mode Cc: Sagar Karandikar <sag...@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbast...@mail.uni-paderborn.de> Cc: Palmer Dabbelt <pal...@sifive.com> Cc: Alistair Francis <alistair.fran...@wdc.com> Signed-off-by: Michael Clark <m...@sifive.com> ---

[Qemu-devel] [PATCH v1 12/30] RISC-V: Mark mstatus.fs dirty

2018-05-22 Thread Michael Clark
t;alistair.fran...@wdc.com> Cc: Richard Henderson <richard.hender...@linaro.org> Signed-off-by: Michael Clark <m...@sifive.com> Reviewed-by: Michael Clark <m...@sifive.com> Co-authored-by: Richard Henderson <richard.hender...@linaro.org> Co-authored-by: Michael C

[Qemu-devel] [PATCH v1 21/30] RISC-V: Add misa.MAFD checks to translate

2018-05-22 Thread Michael Clark
lmann <kbast...@mail.uni-paderborn.de> Cc: Alistair Francis <alistair.fran...@wdc.com> Cc: Emilio G. Cota <c...@braap.org> Signed-off-by: Michael Clark <m...@sifive.com> --- target/riscv/translate.c | 158 +++ 1 file changed, 15

[Qemu-devel] [PATCH v1 18/30] RISC-V: Add missing free for plic_hart_config

2018-05-22 Thread Michael Clark
Cc: Palmer Dabbelt <pal...@sifive.com> Cc: Sagar Karandikar <sag...@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbast...@mail.uni-paderborn.de> Cc: Alistair Francis <alistair.fran...@wdc.com> Signed-off-by: Michael Clark <m...@sifive.com> --- hw/riscv/virt.c | 2 ++

[Qemu-devel] [PATCH v1 26/30] RISC-V: Remove unnecessary disassembler constraints

2018-05-22 Thread Michael Clark
an...@wdc.com> Signed-off-by: Michael Clark <m...@sifive.com> --- disas/riscv.c | 138 -- 1 file changed, 138 deletions(-) diff --git a/disas/riscv.c b/disas/riscv.c index 7fd1019623ee..27546dd7902c 100644 --- a/disas/riscv.c +++ b/

[Qemu-devel] [PATCH v1 03/30] RISC-V: Use atomic_cmpxchg to update PLIC bitmaps

2018-05-22 Thread Michael Clark
as the count of pending interrupts is not used. Cc: Sagar Karandikar <sag...@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbast...@mail.uni-paderborn.de> Cc: Palmer Dabbelt <pal...@sifive.com> Cc: Alistair Francis <alistair.fran...@wdc.com> Signed-off-by: Michael Clark &l

[Qemu-devel] [PATCH v1 20/30] RISC-V: Add misa to DisasContext

2018-05-22 Thread Michael Clark
aderborn.de> Cc: Alistair Francis <alistair.fran...@wdc.com> Cc: Emilio G. Cota <c...@braap.org> Signed-off-by: Michael Clark <m...@sifive.com> Reviewed-by: Richard Henderson <richard.hender...@linaro.org> --- target/riscv/translate.c | 78 ++

[Qemu-devel] [PATCH v1 22/30] RISC-V: Add misa runtime write support

2018-05-22 Thread Michael Clark
.@wdc.com> Signed-off-by: Michael Clark <m...@sifive.com> --- target/riscv/cpu.c | 2 +- target/riscv/cpu.h | 4 +++- target/riscv/cpu_bits.h | 11 +++ target/riscv/csr.c | 52 - 4 files changed, 66 insertions(+), 3 del

[Qemu-devel] [PATCH v1 17/30] RISC-V: Replace __builtin_popcount with ctpop8 in PLIC

2018-05-22 Thread Michael Clark
cis <alistair.fran...@wdc.com> Signed-off-by: Michael Clark <m...@sifive.com> --- hw/riscv/sifive_plic.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/riscv/sifive_plic.c b/hw/riscv/sifive_plic.c index b267ff88902d..dc6f4924e282 100644 --- a/hw/risc

[Qemu-devel] [PATCH v1 05/30] RISC-V: Allow setting and clearing multiple irqs

2018-05-22 Thread Michael Clark
<kbast...@mail.uni-paderborn.de> Cc: Palmer Dabbelt <pal...@sifive.com> Cc: Alistair Francis <alistair.fran...@wdc.com> Signed-off-by: Michael Clark <m...@sifive.com> --- hw/riscv/sifive_clint.c | 8 hw/riscv/sifive_plic.c | 4 ++-- target/riscv/cpu.h | 22 ++

[Qemu-devel] [PATCH v1 14/30] RISC-V: Add public API for the CSR dispatch table

2018-05-22 Thread Michael Clark
.@wdc.com> Signed-off-by: Michael Clark <m...@sifive.com> --- target/riscv/cpu.h | 18 ++ target/riscv/csr.c | 35 ++- 2 files changed, 36 insertions(+), 17 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 242

[Qemu-devel] [PATCH v1 28/30] RISC-V: linux-user support for RVE ABI

2018-05-22 Thread Michael Clark
Palmer Dabbelt <pal...@sifive.com> Cc: Sagar Karandikar <sag...@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbast...@mail.uni-paderborn.de> Cc: Alistair Francis <alistair.fran...@wdc.com> Co-authored-by: Kito Cheng <kito.ch...@gmail.com> Co-authored-by: Michael Clark <

[Qemu-devel] [PATCH v1 08/30] RISC-V: Implement modular CSR helper interface

2018-05-22 Thread Michael Clark
<kbast...@mail.uni-paderborn.de> Cc: Palmer Dabbelt <pal...@sifive.com> Cc: Alistair Francis <alistair.fran...@wdc.com> Signed-off-by: Michael Clark <m...@sifive.com> --- target/riscv/Makefile.objs | 2 +- target/riscv/cpu.h | 18 +- target/riscv/cpu_helper.c

[Qemu-devel] [PATCH v1 00/30] QEMU 2.13 RISC-V updates

2018-05-22 Thread Michael Clark
board test (HiFive1 binaries): pass * sifive_u board test (HiFive Unleashed): pass * riscv-tests: pass * checkpatch: pass Kito Cheng (1): RISC-V: linux-user support for RVE ABI Michael Clark (27): RISC-V: Update address bits to support sv39 and sv48 RISC-V: Improve page table walker spec

[Qemu-devel] [PATCH v1 02/30] RISC-V: Improve page table walker spec compliance

2018-05-22 Thread Michael Clark
for PTE X flag and mstatus.mxr - Use memory_region_is_ram in pte update Cc: Sagar Karandikar <sag...@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbast...@mail.uni-paderborn.de> Cc: Palmer Dabbelt <pal...@sifive.com> Cc: Alistair Francis <alistair.fran...@wdc.com> Signed-

[Qemu-devel] [PATCH v1 04/30] RISC-V: Simplify riscv_cpu_local_irqs_pending

2018-05-22 Thread Michael Clark
This commit is intended to improve readability. There is no change to the logic. Cc: Sagar Karandikar <sag...@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbast...@mail.uni-paderborn.de> Cc: Palmer Dabbelt <pal...@sifive.com> Cc: Alistair Francis <alistair.fran...@wdc.com>

[Qemu-devel] [PATCH v1 11/30] RISC-V: Split out mstatus_fs from tb_flags

2018-05-22 Thread Michael Clark
<richard.hender...@linaro.org> Signed-off-by: Michael Clark <m...@sifive.com> Reviewed-by: Michael Clark <m...@sifive.com> --- target/riscv/cpu.h | 6 +++--- target/riscv/translate.c | 10 +- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/target/ris

[Qemu-devel] [PATCH v1 25/30] RISC-V: Enable second UART on sifive_e and sifive_u

2018-05-22 Thread Michael Clark
gt; Cc: Sagar Karandikar <sag...@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbast...@mail.uni-paderborn.de> Cc: Alistair Francis <alistair.fran...@wdc.com> Signed-off-by: Michael Clark <m...@sifive.com> --- hw/riscv/sifive_e.c | 4 ++-- hw/riscv/sifive_u.c | 4 ++-- 2 fil

[Qemu-devel] [PATCH v1 09/30] RISC-V: Implement atomic mip/sip CSR updates

2018-05-22 Thread Michael Clark
Use the new CSR read/modify/write interface to implement atomic updates to mip/sip. Cc: Sagar Karandikar <sag...@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbast...@mail.uni-paderborn.de> Cc: Palmer Dabbelt <pal...@sifive.com> Cc: Alistair Francis <alistair.fran...@wdc.com>

[Qemu-devel] [PATCH v1 10/30] RISC-V: Implement existential predicates for CSRs

2018-05-22 Thread Michael Clark
Dabbelt <pal...@sifive.com> Cc: Alistair Francis <alistair.fran...@wdc.com> Signed-off-by: Michael Clark <m...@sifive.com> --- target/riscv/cpu.c| 6 ++ target/riscv/cpu.h| 5 +- target/riscv/cpu_helper.c | 3 +- t

[Qemu-devel] [PATCH v1 27/30] elf: Add RISC-V PSABI ELF header defines

2018-05-22 Thread Michael Clark
cis <alistair.fran...@wdc.com> Signed-off-by: Michael Clark <m...@sifive.com> --- include/elf.h | 8 1 file changed, 8 insertions(+) diff --git a/include/elf.h b/include/elf.h index 934dbbd6b3ae..d363ba85a688 100644 --- a/include/elf.h +++ b/include/elf.h @@ -1285,6 +1285,1

[Qemu-devel] [PATCH v1 24/30] RISC-V: Fix PLIC pending bitfield reads

2018-05-22 Thread Michael Clark
Dabbelt <pal...@sifive.com> Cc: Sagar Karandikar <sag...@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbast...@mail.uni-paderborn.de> Cc: Alistair Francis <alistair.fran...@wdc.com> Reported-by: Vincent Siles <vincent.si...@ens-lyon.org> Signed-off-by: Michael Clark &

[Qemu-devel] [PATCH v1 15/30] RISC-V: Add hartid and \n to interrupt logging

2018-05-22 Thread Michael Clark
: Alistair Francis <alistair.fran...@wdc.com> Signed-off-by: Michael Clark <m...@sifive.com> --- target/riscv/cpu_helper.c | 18 ++ 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index bc15e19022cc..69

[Qemu-devel] [PATCH v1 06/30] RISC-V: Move non-ops from op_helper to cpu_helper

2018-05-22 Thread Michael Clark
; Cc: Palmer Dabbelt <pal...@sifive.com> Cc: Alistair Francis <alistair.fran...@wdc.com> Signed-off-by: Michael Clark <m...@sifive.com> Reviewed-by: Alistair Francis <alistair.fran...@wdc.com> --- target/riscv/Makefile.objs | 2 +- target/r

[Qemu-devel] [PATCH v1 30/30] RISC-V: Support separate firmware and kernel payload

2018-05-22 Thread Michael Clark
m> Cc: Alistair Francis <alistair.fran...@wdc.com> Signed-off-by: Michael Clark <m...@sifive.com> --- hw/riscv/Makefile.objs | 1 + hw/riscv/boot.c | 172 hw/riscv/virt.c | 67 +++ include/hw/riscv/b

[Qemu-devel] [PATCH v1 29/30] RISC-V: Don't add NULL bootargs to device-tree

2018-05-22 Thread Michael Clark
--- hw/riscv/sifive_u.c | 4 +++- hw/riscv/spike.c| 6 -- hw/riscv/virt.c | 4 +++- 3 files changed, 10 insertions(+), 4 deletions(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 326b0f434cff..02721d43c474 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@

[Qemu-devel] [PATCH v1 07/30] RISC-V: Update CSR and interrupt definitions

2018-05-22 Thread Michael Clark
.@wdc.com> Signed-off-by: Michael Clark <m...@sifive.com> Reviewed-by: Alistair Francis <alistair.fran...@wdc.com> --- target/riscv/cpu_bits.h | 692 +-- target/riscv/op_helper.c | 4 +- 2 files changed, 376 insertions(+), 320 del

[Qemu-devel] [PATCH v1 13/30] RISC-V: Implement mstatus.TSR/TW/TVM

2018-05-22 Thread Michael Clark
.com> Cc: Matthew Suozzo <msuo...@google.com> Signed-off-by: Michael Clark <m...@sifive.com> Co-authored-by: Matthew Suozzo <msuo...@google.com> Co-authored-by: Michael Clark <m...@sifive.com> --- target/riscv/csr.c | 17 + target/riscv/op_helper.c

[Qemu-devel] [PATCH v1 19/30] RISC-V: Allow interrupt controllers to claim interrupts

2018-05-22 Thread Michael Clark
and software interrupts by other interrupt controller models. Cc: Palmer Dabbelt <pal...@sifive.com> Cc: Sagar Karandikar <sag...@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbast...@mail.uni-paderborn.de> Cc: Alistair Francis <alistair.fran...@wdc.com> Signed-off-by: Michae

[Qemu-devel] [PATCH v1 01/30] RISC-V: Update address bits to support sv39 and sv48

2018-05-22 Thread Michael Clark
Cc: Sagar Karandikar Cc: Bastian Koppelmann Cc: Palmer Dabbelt Cc: Alistair Francis Signed-off-by: Palmer Dabbelt --- target/riscv/cpu.h | 8 1 file changed, 4

[Qemu-devel] [PATCH v1 23/30] RISC-V: Fix CLINT timecmp low 32-bit writes

2018-05-22 Thread Michael Clark
aderborn.de> Cc: Alistair Francis <alistair.fran...@wdc.com> Co-Authored-by: Johannes Haring <johannes.har...@gmx.net> Signed-off-by: Michael Clark <m...@sifive.com> --- hw/riscv/sifive_clint.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git

Re: [Qemu-devel] [PATCH v1 02/30] RISC-V: Improve page table walker spec compliance

2018-05-23 Thread Michael Clark
, May 23, 2018 at 12:14 PM, Michael Clark <m...@sifive.com> wrote: > - Inline PTE_TABLE check for better readability > - Change access checks from ternary operator to if > - Improve readibility of User page U mode and SUM test > - Disallow non U mode from fetching from User pages &g

Re: [Qemu-devel] [PATCH v2] elf: Add RISC-V PSABI ELF header defines

2018-05-25 Thread Michael Clark
On Fri, May 25, 2018 at 7:53 PM, Laurent Vivier <laur...@vivier.eu> wrote: > Le 25/05/2018 à 09:22, Michael Clark a écrit : > > Refer to the RISC-V PSABI specification for details: > > > > - https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md >

Re: [Qemu-devel] [RISC-V] Coverity 1390849, Logically dead code

2018-05-25 Thread Michael Clark
On Fri, May 25, 2018 at 9:54 AM, Richard Henderson wrote: > In the latest Coverity scan, it reports > > 405if (csrno >= CSR_MHPMCOUNTER3 && csrno <= CSR_MHPMCOUNTER31) { > 406return 0; > 407} > 408#if defined(TARGET_RISCV32) > 409if (csrno >=

[Qemu-devel] [PATCH] RISC-V: Correct typo in RV32 perf counters

2018-05-25 Thread Michael Clark
This patch enables mhpmcounter3h through mhpmcounter31h on RV32. Previously the RV32 h versions (high 32-bits of 64-bit counters) of these counters would trap with an illegal instruction instead of returning 0 as intended. Reported-by: Richard Henderson <r...@twiddle.net> Signed-off-by: M

Re: [Qemu-devel] [PATCH v1 27/30] elf: Add RISC-V PSABI ELF header defines

2018-05-25 Thread Michael Clark
On Wed, May 23, 2018 at 6:44 PM, Laurent Vivier <laur...@vivier.eu> wrote: > Le 23/05/2018 à 02:15, Michael Clark a écrit : > > Refer to the RISC-V PSABI specification for details: > > > > - https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md >

[Qemu-devel] [PATCH v2] elf: Add RISC-V PSABI ELF header defines

2018-05-25 Thread Michael Clark
cis <alistair.fran...@wdc.com> Signed-off-by: Michael Clark <m...@sifive.com> --- include/elf.h | 8 1 file changed, 8 insertions(+) diff --git a/include/elf.h b/include/elf.h index 934dbbd6b3ae..bd0493f43d19 100644 --- a/include/elf.h +++ b/include/elf.h @@ -1285,6 +1285,1

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