Re: [Qemu-devel] [sw-dev] RFC: QEMU RISC-V modular ISA decoding

2017-07-26 Thread Michael Clark
> On 27 Jul 2017, at 8:58 AM, kr...@berkeley.edu wrote: > > > Given that one of the goals of RISC-V is extensibility, it would be > nice if the QEMU port was done in a way to make it easier to extend by > third parties, including other automated tools. I'm sure that, over > time, the

Re: [Qemu-devel] [PATCH v1 03/21] RISC-V CPU Core Definition

2018-01-04 Thread Michael Clark
On Fri, 5 Jan 2018 at 6:39 AM, Antony Pavlov <antonynpav...@gmail.com> wrote: > On Thu, 4 Jan 2018 20:33:57 +1300 > Michael Clark <m...@sifive.com> wrote: > > > On Thu, Jan 4, 2018 at 7:47 PM, Antony Pavlov <antonynpav...@gmail.com> > > wrote: >

Re: [Qemu-devel] [PATCH v1 21/21] RISC-V Build Infrastructure

2018-01-04 Thread Michael Clark
On Fri, 5 Jan 2018 at 5:55 AM, Antony Pavlov <antonynpav...@gmail.com> wrote: > On Wed, 3 Jan 2018 13:44:25 +1300 > Michael Clark <m...@sifive.com> wrote: > > > This adds RISC-V into the build system enabling the following targets: > > > > - riscv32-soft

Re: [Qemu-devel] [PATCH v1 17/21] SiFive RISC-V UART Device

2018-01-04 Thread Michael Clark
On Thu, Jan 4, 2018 at 3:57 AM, KONRAD Frederic <frederic.kon...@adacore.com > wrote: > Hi all, > > > On 01/03/2018 01:44 AM, Michael Clark wrote: > >> QEMU model of the UART on the SiFive E300 and U500 series SOCs. >> BBL supports the SiFive UART for

Re: [Qemu-devel] [PATCH v1 10/21] RISC-V Linux User Emulation

2018-01-04 Thread Michael Clark
On Thu, Jan 4, 2018 at 12:47 PM, Richard Henderson < richard.hender...@linaro.org> wrote: > On 01/02/2018 04:44 PM, Michael Clark wrote: > > diff --git a/linux-user/elfload.c b/linux-user/elfload.c > > index 20f3d8c..178af56 100644 > > --- a/linux-user/elfload.c >

Re: [Qemu-devel] [PATCH v1 17/21] SiFive RISC-V UART Device

2018-01-04 Thread Michael Clark
On Fri, 5 Jan 2018 at 9:53 AM, Antony Pavlov <antonynpav...@gmail.com> wrote: > On Wed, 3 Jan 2018 13:44:21 +1300 > Michael Clark <m...@sifive.com> wrote: > > > QEMU model of the UART on the SiFive E300 and U500 series SOCs. > > BBL supports the SiFive UART for

Re: [Qemu-devel] [PATCH v1 21/21] RISC-V Build Infrastructure

2018-01-04 Thread Michael Clark
On Thu, Jan 4, 2018 at 12:23 PM, Eric Blake <ebl...@redhat.com> wrote: > On 01/02/2018 06:44 PM, Michael Clark wrote: > > This adds RISC-V into the build system enabling the following targets: > > > > - riscv32-softmmu > > - riscv64-softmmu > > - risc

Re: [Qemu-devel] [PATCH v1 03/21] RISC-V CPU Core Definition

2018-01-07 Thread Michael Clark
/michaeljclark/riscv-qemu/commits/qemu-devel Hopefully, I'll have a new spin relatively soon... I'm making good progress on getting target/riscv clean enough for re-submission... Michael. On Thu, Jan 4, 2018 at 11:30 AM, Michael Clark <m...@sifive.com> wrote: > > > On Wed, Jan 3, 2018 at 6

[Qemu-devel] [PATCH v3 09/21] RISC-V Physical Memory Protection

2018-01-10 Thread Michael Clark
be preferable to keep the code in-tree for folk that are interested in RISC-V PMP support. Signed-off-by: Michael Clark <m...@sifive.com> --- target/riscv/pmp.c | 386 + target/riscv/pmp.h | 70 ++ 2 files changed, 456 insertions(+) creat

[Qemu-devel] [PATCH v3 00/21] RISC-V QEMU Port Submission v3

2018-01-10 Thread Michael Clark
ykov - Antony Pavlov - Bastian Koppelmann - Bruce Hoult - Chih-Min Chao - Daire McNamara - David Abdurachmanov - Ivan Griffin - Kito Cheng - Michael Clark - Palmer Dabbelt - Sagar Karandikar - Stefan O'Rear Notes: - contributor email addresses available off-list on request. - checkpatch has been r

[Qemu-devel] [PATCH v3 17/21] SiFive RISC-V UART Device

2018-01-10 Thread Michael Clark
/serial.c'. Signed-off-by: Michael Clark <m...@sifive.com> --- hw/riscv/sifive_uart.c | 182 + include/hw/riscv/sifive_uart.h | 76 + 2 files changed, 258 insertions(+) create mode 100644 hw/riscv/sifive_uart.c create mode

[Qemu-devel] [PATCH v3 18/21] SiFive RISC-V PRCI Block

2018-01-10 Thread Michael Clark
Simple model of the PRCI (Power, Reset, Clock, Interrupt) to emulate register reads made by the SDK BSP. Signed-off-by: Michael Clark <m...@sifive.com> --- hw/riscv/sifive_prci.c | 107 + include/hw/riscv/sifive_prci.h | 43 ++

[Qemu-devel] [PATCH v3 02/21] RISC-V ELF Machine Definition

2018-01-10 Thread Michael Clark
Define RISC-V ELF machine EM_RISCV 243 Reviewed-by: Richard Henderson <richard.hender...@linaro.org> Signed-off-by: Michael Clark <m...@sifive.com> --- include/elf.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/elf.h b/include/elf.h index e8a515c..8e457fc 100644 -

[Qemu-devel] [PATCH v3 12/21] RISC-V HART Array

2018-01-10 Thread Michael Clark
Holds the state of a heterogenous array of RISC-V hardware threads. Signed-off-by: Michael Clark <m...@sifive.com> --- hw/riscv/riscv_hart.c | 95 +++ include/hw/riscv/riscv_hart.h | 45 2 files changed, 140 inse

[Qemu-devel] [PATCH v3 06/21] RISC-V FPU Support

2018-01-10 Thread Michael Clark
Helper routines for FPU instructions and NaN definitions. Signed-off-by: Michael Clark <m...@sifive.com> --- fpu/softfloat-specialize.h | 7 +- target/riscv/fpu_helper.c | 591 + 2 files changed, 595 insertions(+), 3 deletions(-) create mode

[Qemu-devel] [PATCH v3 01/21] RISC-V Maintainers

2018-01-10 Thread Michael Clark
Add Michael Clark, Palmer Dabbelt, Sagar Karandikar and Bastian Koppelmann as RISC-V Maintainers. Signed-off-by: Michael Clark <m...@sifive.com> --- MAINTAINERS | 11 +++ 1 file changed, 11 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index bc2d3a4..17af5b4

[Qemu-devel] [PATCH v3 05/21] RISC-V CPU Helpers

2018-01-10 Thread Michael Clark
Privileged control and status register helpers and page fault handling. Signed-off-by: Michael Clark <m...@sifive.com> --- target/riscv/helper.c| 499 ++ target/riscv/helper.h| 78 ++ target/riscv/op_helper.c

[Qemu-devel] [PATCH v3 13/21] SiFive RISC-V CLINT Block

2018-01-10 Thread Michael Clark
The CLINT (Core Local Interruptor) device provides real-time clock, timer and interprocessor interrupts based on SiFive's CLINT specification. Signed-off-by: Michael Clark <m...@sifive.com> --- hw/riscv/sifive_clint.c | 312 include/hw

[Qemu-devel] [PATCH v3 03/21] RISC-V CPU Core Definition

2018-01-10 Thread Michael Clark
Add CPU state header, CPU definitions and initialization routines Signed-off-by: Michael Clark <m...@sifive.com> --- target/riscv/cpu.c | 391 + target/riscv/cpu.h | 271 +++ target/riscv/cpu_bits.h

[Qemu-devel] [PATCH v3 10/21] RISC-V Linux User Emulation

2018-01-10 Thread Michael Clark
Implementation of linux user emulation for RISC-V. Signed-off-by: Michael Clark <m...@sifive.com> --- linux-user/elfload.c | 22 +++ linux-user/main.c | 114 +++ linux-user/riscv/syscall_nr.h | 275 +++ linu

[Qemu-devel] [PATCH v3 14/21] SiFive RISC-V PLIC Block

2018-01-10 Thread Michael Clark
The PLIC (Platform Level Interrupt Controller) device provides a parameterizable interrupt controller based on SiFive's PLIC specification. Signed-off-by: Michael Clark <m...@sifive.com> --- hw/riscv/sifive_plic.c | 554 + include/hw

[Qemu-devel] [PATCH v3 16/21] RISC-V VirtIO Machine

2018-01-10 Thread Michael Clark
RISC-V machine with device-tree, 16550a UART and VirtIO MMIO. The following machine is implemented: - 'virt'; CLINT, PLIC, 16550A UART, VirtIO MMIO, device-tree Signed-off-by: Michael Clark <m...@sifive.com> --- hw/riscv/virt.c

[Qemu-devel] [PATCH v3 11/21] RISC-V HTIF Console

2018-01-10 Thread Michael Clark
reads the ELF kernel and locates the 'tohost' and 'fromhost' symbols which it uses for guest to host console MMIO. The HTIT chardev implements the pre qom legacy interface consistent with the 16550a UART in 'hw/char/serial.c'. Signed-off-by: Michael Clark <m...@sifive.com> --- hw/riscv/riscv

[Qemu-devel] [PATCH v3 08/21] RISC-V TCG Code Generation

2018-01-10 Thread Michael Clark
: Privileged ISA Version 1.9.1 - RISC-V Instruction Set Manual Volume II: Privileged ISA Version 1.10 Signed-off-by: Michael Clark <m...@sifive.com> --- target/riscv/instmap.h | 377 + target/riscv/translate.c | 1982 ++ 2 files changed

[Qemu-devel] [PATCH v3 04/21] RISC-V Disassembler

2018-01-10 Thread Michael Clark
and brevity reasons: ERROR: line over 90 characters ERROR: trailing statements should be on next line ERROR: space prohibited between function name and open parenthesis '(' Signed-off-by: Michael Clark <m...@sifive.com> --- disas.c |2 + disas/Makefile.objs |1 + disas/r

[Qemu-devel] [PATCH v3 07/21] RISC-V GDB Stub

2018-01-10 Thread Michael Clark
GDB Register read and write routines. Signed-off-by: Michael Clark <m...@sifive.com> --- target/riscv/gdbstub.c | 59 ++ 1 file changed, 59 insertions(+) create mode 100644 target/riscv/gdbstub.c diff --git a/target/riscv/gdbstub.c b/target

[Qemu-devel] [PATCH v3 15/21] RISC-V Spike Machines

2018-01-10 Thread Michael Clark
-by: Michael Clark <m...@sifive.com> --- hw/riscv/spike_v1_09.c | 207 ++ hw/riscv/spike_v1_10.c | 281 +++ include/hw/riscv/spike.h | 51 + 3 files changed, 539 insertions(+) create mode 100644 hw/riscv/spike

[Qemu-devel] [PATCH v3 20/21] SiFive Freedom U500 RISC-V Machine

2018-01-10 Thread Michael Clark
This provides a RISC-V Board compatible with the the SiFive U500 SDK. The following machine is implemented: - 'sifive_u500'; CLINT, PLIC, UART, device-tree Signed-off-by: Michael Clark <m...@sifive.com> --- hw/riscv/sifive_u500.c | 338 + i

[Qemu-devel] [PATCH v3 19/21] SiFive Freedom E300 RISC-V Machine

2018-01-10 Thread Michael Clark
This provides a RISC-V Board compatible with the the SiFive E300 SDK. The following machine is implemented: - 'sifive_e300'; CLINT, PLIC, UART, AON, GPIO, QSPI, PWM Signed-off-by: Michael Clark <m...@sifive.com> --- hw/riscv/sifive_e300.c

[Qemu-devel] [PATCH v3 21/21] RISC-V Build Infrastructure

2018-01-10 Thread Michael Clark
' script is updated to add the RISC-V ELF magic. Expected checkpatch errors for consistency reasons: ERROR: line over 90 characters FILE: scripts/qemu-binfmt-conf.sh Signed-off-by: Michael Clark <m...@sifive.com> --- Makefile.objs | 1 + arch_

[Qemu-devel] [PATCH v2 02/21] RISC-V ELF Machine Definition

2018-01-10 Thread Michael Clark
Define RISC-V ELF machine EM_RISCV 243 Reviewed-by: Richard Henderson <richard.hender...@linaro.org> Signed-off-by: Michael Clark <m...@sifive.com> --- include/elf.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/elf.h b/include/elf.h index e8a515c..8e457fc 100644 -

[Qemu-devel] [PATCH v2 06/21] RISC-V FPU Support

2018-01-10 Thread Michael Clark
Helper routines for FPU instructions and NaN definitions. Signed-off-by: Michael Clark <m...@sifive.com> --- fpu/softfloat-specialize.h | 7 +- target/riscv/fpu_helper.c | 591 + 2 files changed, 595 insertions(+), 3 deletions(-) create mode

[Qemu-devel] [PATCH v2 01/21] RISC-V Maintainers

2018-01-10 Thread Michael Clark
Add Michael Clark, Palmer Dabbelt, Sagar Karandikar and Bastian Koppelmann as RISC-V Maintainers. Signed-off-by: Michael Clark <m...@sifive.com> --- MAINTAINERS | 11 +++ 1 file changed, 11 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index bc2d3a4..17af5b4

[Qemu-devel] [PATCH v2 05/21] RISC-V CPU Helpers

2018-01-10 Thread Michael Clark
Privileged control and status register helpers and page fault handling. Signed-off-by: Michael Clark <m...@sifive.com> --- target/riscv/helper.c| 499 ++ target/riscv/helper.h| 78 ++ target/riscv/op_helper.c

[Qemu-devel] [PATCH v2 03/21] RISC-V CPU Core Definition

2018-01-10 Thread Michael Clark
Add CPU state header, CPU definitions and initialization routines Signed-off-by: Michael Clark <m...@sifive.com> --- target/riscv/cpu.c | 391 + target/riscv/cpu.h | 271 +++ target/riscv/cpu_bits.h

[Qemu-devel] [PATCH v2 07/21] RISC-V GDB Stub

2018-01-10 Thread Michael Clark
GDB Register read and write routines. Signed-off-by: Michael Clark <m...@sifive.com> --- target/riscv/gdbstub.c | 59 ++ 1 file changed, 59 insertions(+) create mode 100644 target/riscv/gdbstub.c diff --git a/target/riscv/gdbstub.c b/target

[Qemu-devel] [PATCH v2 00/21] RISC-V QEMU Port Submission v2

2018-01-10 Thread Michael Clark
- Bastian Koppelmann - Bruce Hoult - Chih-Min Chao - Daire McNamara - David Abdurachmanov - Ivan Griffin - Kito Cheng - Michael Clark - Palmer Dabbelt - Sagar Karandikar - Stefan O'Rear Notes: - contributor email addresses available off-list on request. - checkpatch has been run on all 21 p

[Qemu-devel] [PATCH v2 09/21] RISC-V Physical Memory Protection

2018-01-10 Thread Michael Clark
be preferable to keep the code in-tree for folk that are interested in RISC-V PMP support. Signed-off-by: Michael Clark <m...@sifive.com> --- target/riscv/pmp.c | 386 + target/riscv/pmp.h | 70 ++ 2 files changed, 456 insertions(+) creat

[Qemu-devel] [PATCH v2 13/21] SiFive RISC-V CLINT Block

2018-01-10 Thread Michael Clark
The CLINT (Core Local Interruptor) device provides real-time clock, timer and interprocessor interrupts based on SiFive's CLINT specification. Signed-off-by: Michael Clark <m...@sifive.com> --- hw/riscv/sifive_clint.c | 312 include/hw

[Qemu-devel] [PATCH v2 11/21] RISC-V HTIF Console

2018-01-10 Thread Michael Clark
reads the ELF kernel and locates the 'tohost' and 'fromhost' symbols which it uses for guest to host console MMIO. The HTIT chardev implements the pre qom legacy interface consistent with the 16550a UART in 'hw/char/serial.c'. Signed-off-by: Michael Clark <m...@sifive.com> --- hw/riscv/riscv

[Qemu-devel] [PATCH v2 12/21] RISC-V HART Array

2018-01-10 Thread Michael Clark
Holds the state of a heterogenous array of RISC-V hardware threads. Signed-off-by: Michael Clark <m...@sifive.com> --- hw/riscv/riscv_hart.c | 95 +++ include/hw/riscv/riscv_hart.h | 45 2 files changed, 140 inse

[Qemu-devel] [PATCH v2 10/21] RISC-V Linux User Emulation

2018-01-10 Thread Michael Clark
Implementation of linux user emulation for RISC-V. Signed-off-by: Michael Clark <m...@sifive.com> --- linux-user/elfload.c | 22 +++ linux-user/main.c | 114 +++ linux-user/riscv/syscall_nr.h | 275 +++ linu

[Qemu-devel] [PATCH v2 17/21] SiFive RISC-V UART Device

2018-01-10 Thread Michael Clark
/serial.c'. Signed-off-by: Michael Clark <m...@sifive.com> --- hw/riscv/sifive_uart.c | 182 + include/hw/riscv/sifive_uart.h | 76 + 2 files changed, 258 insertions(+) create mode 100644 hw/riscv/sifive_uart.c create mode

[Qemu-devel] [PATCH v2 16/21] RISC-V VirtIO Machine

2018-01-10 Thread Michael Clark
RISC-V machine with device-tree, 16550a UART and VirtIO MMIO. The following machine is implemented: - 'virt'; CLINT, PLIC, 16550A UART, VirtIO MMIO, device-tree Signed-off-by: Michael Clark <m...@sifive.com> --- hw/riscv/virt.c

[Qemu-devel] [PATCH v2 18/21] SiFive RISC-V PRCI Block

2018-01-10 Thread Michael Clark
Simple model of the PRCI (Power, Reset, Clock, Interrupt) to emulate register reads made by the SDK BSP. Signed-off-by: Michael Clark <m...@sifive.com> --- hw/riscv/sifive_prci.c | 107 + include/hw/riscv/sifive_prci.h | 43 ++

[Qemu-devel] [PATCH v2 14/21] SiFive RISC-V PLIC Block

2018-01-10 Thread Michael Clark
The PLIC (Platform Level Interrupt Controller) device provides a parameterizable interrupt controller based on SiFive's PLIC specification. Signed-off-by: Michael Clark <m...@sifive.com> --- hw/riscv/sifive_plic.c | 554 + include/hw

[Qemu-devel] [PATCH v2 08/21] RISC-V TCG Code Generation

2018-01-10 Thread Michael Clark
: Privileged ISA Version 1.9.1 - RISC-V Instruction Set Manual Volume II: Privileged ISA Version 1.10 Signed-off-by: Michael Clark <m...@sifive.com> --- target/riscv/instmap.h | 377 + target/riscv/translate.c | 1982 ++ 2 files changed

[Qemu-devel] [PATCH v2 21/21] RISC-V Build Infrastructure

2018-01-10 Thread Michael Clark
' script is updated to add the RISC-V ELF magic. Expected checkpatch errors for consistency reasons: ERROR: line over 90 characters FILE: scripts/qemu-binfmt-conf.sh Signed-off-by: Michael Clark <m...@sifive.com> --- Makefile.objs | 1 + arch_

[Qemu-devel] [PATCH v2 20/21] SiFive Freedom U500 RISC-V Machine

2018-01-10 Thread Michael Clark
This provides a RISC-V Board compatible with the the SiFive U500 SDK. The following machine is implemented: - 'sifive_u500'; CLINT, PLIC, UART, device-tree Signed-off-by: Michael Clark <m...@sifive.com> --- hw/riscv/sifive_u500.c | 338 + i

[Qemu-devel] [PATCH v2 15/21] RISC-V Spike Machines

2018-01-10 Thread Michael Clark
-by: Michael Clark <m...@sifive.com> --- hw/riscv/spike_v1_09.c | 207 ++ hw/riscv/spike_v1_10.c | 281 +++ include/hw/riscv/spike.h | 51 + 3 files changed, 539 insertions(+) create mode 100644 hw/riscv/spike

[Qemu-devel] [PATCH v2 04/21] RISC-V Disassembler

2018-01-10 Thread Michael Clark
and brevity reasons: ERROR: line over 90 characters ERROR: trailing statements should be on next line ERROR: space prohibited between function name and open parenthesis '(' Signed-off-by: Michael Clark <m...@sifive.com> --- disas.c |2 + disas/Makefile.objs |1 + disas/r

[Qemu-devel] [PATCH v2 19/21] SiFive Freedom E300 RISC-V Machine

2018-01-10 Thread Michael Clark
This provides a RISC-V Board compatible with the the SiFive E300 SDK. The following machine is implemented: - 'sifive_e300'; CLINT, PLIC, UART, AON, GPIO, QSPI, PWM Signed-off-by: Michael Clark <m...@sifive.com> --- hw/riscv/sifive_e300.c

Re: [Qemu-devel] [PATCH v2 00/21] RISC-V QEMU Port Submission v2

2018-01-10 Thread Michael Clark
FYI - I intended these emails to go to the RISC-V Patches but unfortunately had the wrong address on the 'cc. This time around, the patches are in the qemu-devel archives here: - http://lists.nongnu.org/archive/html/qemu-devel/2018-01/threads.html On Thu, Jan 11, 2018 at 12:46 PM, Michael Clark

Re: [Qemu-devel] [PATCH v2 03/21] RISC-V CPU Core Definition

2018-01-24 Thread Michael Clark
On Mon, Jan 15, 2018 at 5:44 AM, Igor Mammedov <imamm...@redhat.com> wrote: > On Wed, 10 Jan 2018 15:46:22 -0800 > Michael Clark <m...@sifive.com> wrote: > > > Add CPU state header, CPU definitions and initialization routines > > > > Signed

Re: [Qemu-devel] [PATCH v1 06/21] RISC-V FPU Support

2018-01-24 Thread Michael Clark
On Wed, Jan 24, 2018 at 8:16 AM, Richard Henderson < richard.hender...@linaro.org> wrote: > On 01/23/2018 05:31 PM, Michael Clark wrote: > > For the meantime we've greatly simplified cpu_mmu_index to just return > the > > processor mode as well as a

Re: [Qemu-devel] [PATCH v3 21/21] RISC-V Build Infrastructure

2018-01-11 Thread Michael Clark
On Fri, Jan 12, 2018 at 3:05 AM, Eric Blake <ebl...@redhat.com> wrote: > On 01/10/2018 08:22 PM, Michael Clark wrote: > > This adds RISC-V into the build system enabling the following targets: > > > > - riscv32-softmmu > > - riscv64-softmmu > > - risc

Re: [Qemu-devel] [PATCH v2 00/21] RISC-V QEMU Port Submission v2

2018-01-11 Thread Michael Clark
ct, device-tree should be frozen and versioned too as it is only implicitly specified by the code that implements it. On Thu, Jan 11, 2018 at 8:58 PM, Christoph Hellwig <h...@lst.de> wrote: > On Wed, Jan 10, 2018 at 03:46:19PM -0800, Michael Clark wrote: > > - RISC-V Instruction Set Ma

Re: [Qemu-devel] [PATCH v3 06/21] RISC-V FPU Support

2018-01-11 Thread Michael Clark
On Fri, Jan 12, 2018 at 4:31 AM, Richard Henderson < richard.hender...@linaro.org> wrote: > On 01/10/2018 06:21 PM, Michael Clark wrote: > > Helper routines for FPU instructions and NaN definitions. > > > > Signed-off-by: Michael Clark <m...@sifive.com> > &

Re: [Qemu-devel] [PATCH v3 03/21] RISC-V CPU Core Definition

2018-01-11 Thread Michael Clark
On Fri, Jan 12, 2018 at 3:37 AM, Richard Henderson < richard.hender...@linaro.org> wrote: > On 01/10/2018 06:21 PM, Michael Clark wrote: > > +static inline void cpu_get_tb_cpu_state(CPURISCVState *env, > target_ulong *pc, > > +

Re: [Qemu-devel] [PATCH v3 08/21] RISC-V TCG Code Generation

2018-01-11 Thread Michael Clark
On Fri, Jan 12, 2018 at 4:47 AM, Richard Henderson < richard.hender...@linaro.org> wrote: > On 01/10/2018 06:21 PM, Michael Clark wrote: > > TCG code generation for the RV32IMAFDC and RV64IMAFDC. The QEMU > > RISC-V code generator has complete coverage for the Base ISA v2.

Re: [Qemu-devel] [PATCH v3 08/21] RISC-V TCG Code Generation

2018-01-11 Thread Michael Clark
On Fri, Jan 12, 2018 at 7:15 AM, Michael Clark <m...@sifive.com> wrote: > > > On Fri, Jan 12, 2018 at 4:47 AM, Richard Henderson < > richard.hender...@linaro.org> wrote: > >> On 01/10/2018 06:21 PM, Michael Clark wrote: >> > TCG code generation f

Re: [Qemu-devel] [PATCH v1 06/21] RISC-V FPU Support

2018-02-02 Thread Michael Clark
On Mon, Jan 29, 2018 at 12:33 PM, Jim Wilson wrote: > On Wed, Jan 24, 2018 at 3:47 PM, Richard Henderson > wrote: > > On 01/24/2018 10:58 AM, Jim Wilson wrote: > >> Although, looking at this again, I see another statement in a > >> different place

Re: [Qemu-devel] [PATCH v1 11/21] RISC-V HTIF Console

2018-02-04 Thread Michael Clark
On Tue, Jan 9, 2018 at 3:31 AM, Christoph Hellwig <h...@lst.de> wrote: > On Wed, Jan 03, 2018 at 01:44:15PM +1300, Michael Clark wrote: > > HTIF (Host Target Interface) provides console emulation for QEMU. HTIF > > allows identical copies of BBL (Berkeley Boot Loader) and lin

Re: [Qemu-devel] [PATCH v3 21/21] RISC-V Build Infrastructure

2018-02-04 Thread Michael Clark
On Fri, Jan 12, 2018 at 7:43 AM, Michael Clark <m...@sifive.com> wrote: > > > On Fri, Jan 12, 2018 at 3:05 AM, Eric Blake <ebl...@redhat.com> wrote: > >> On 01/10/2018 08:22 PM, Michael Clark wrote: >> > This adds RISC-V into the build system enabling the

Re: [Qemu-devel] [PATCH v1 11/21] RISC-V HTIF Console

2018-02-04 Thread Michael Clark
On Mon, Feb 5, 2018 at 10:29 AM, Christoph Hellwig <h...@lst.de> wrote: > On Mon, Feb 05, 2018 at 09:19:46AM +1300, Michael Clark wrote: > > BTW I've created branches in my own personal trees for Privileged ISA > > v1.9.1. These trees are what I use for v1.9.1 backward comp

[Qemu-devel] [PATCH v4 00/22] RISC-V QEMU Port Submission

2018-02-04 Thread Michael Clark
- Bastian Koppelmann - Bruce Hoult - Chih-Min Chao - Daire McNamara - Darius Rad - David Abdurachmanov - Ivan Griffin - Jim Wilson - Kito Cheng - Michael Clark - Palmer Dabbelt - Richard Henderon - Sagar Karandikar - Stefan O'Rear Notes: - contributor email addresses available off-list on request. -

[Qemu-devel] [PATCH v4 03/22] RISC-V CPU Core Definition

2018-02-04 Thread Michael Clark
Add CPU state header, CPU definitions and initialization routines Signed-off-by: Michael Clark <m...@sifive.com> --- target/riscv/cpu.c | 385 target/riscv/cpu.h | 256 + target/riscv/cpu_bits.h

[Qemu-devel] [PATCH v4 05/22] RISC-V CPU Helpers

2018-02-04 Thread Michael Clark
Privileged control and status register helpers and page fault handling. Signed-off-by: Michael Clark <m...@sifive.com> --- target/riscv/helper.c| 464 ++ target/riscv/helper.h| 78 ++ target/riscv/op_helper.c

[Qemu-devel] [PATCH v4 08/22] RISC-V TCG Code Generation

2018-02-04 Thread Michael Clark
: Privileged ISA Version 1.9.1 - RISC-V Instruction Set Manual Volume II: Privileged ISA Version 1.10 Signed-off-by: Michael Clark <m...@sifive.com> --- target/riscv/instmap.h | 366 + target/riscv/translate.c | 1964 ++ 2 files changed

[Qemu-devel] [PATCH v4 16/22] RISC-V VirtIO Machine

2018-02-04 Thread Michael Clark
RISC-V machine with device-tree, 16550a UART and VirtIO MMIO. The following machine is implemented: - 'virt'; CLINT, PLIC, 16550A UART, VirtIO MMIO, device-tree Signed-off-by: Michael Clark <m...@sifive.com> --- hw/riscv/virt.c

[Qemu-devel] [PATCH v4 21/22] SiFive Freedom U500 RISC-V Machine

2018-02-04 Thread Michael Clark
This provides a RISC-V Board compatible with the the SiFive U500 SDK. The following machine is implemented: - 'sifive_u500'; CLINT, PLIC, UART, device-tree Signed-off-by: Michael Clark <m...@sifive.com> --- hw/riscv/sifive_u500.c | 338 + i

[Qemu-devel] [PATCH v4 14/22] SiFive RISC-V PLIC Block

2018-02-04 Thread Michael Clark
The PLIC (Platform Level Interrupt Controller) device provides a parameterizable interrupt controller based on SiFive's PLIC specification. Signed-off-by: Michael Clark <m...@sifive.com> --- hw/riscv/sifive_plic.c | 554 + include/hw

[Qemu-devel] [PATCH v4 09/22] RISC-V Physical Memory Protection

2018-02-04 Thread Michael Clark
be preferable to keep the code in-tree for folk that are interested in RISC-V PMP support. Signed-off-by: Michael Clark <m...@sifive.com> --- target/riscv/pmp.c | 386 + target/riscv/pmp.h | 70 ++ 2 files changed, 456 insertions(+) creat

[Qemu-devel] [PATCH v4 11/22] RISC-V HTIF Console

2018-02-04 Thread Michael Clark
reads the ELF kernel and locates the 'tohost' and 'fromhost' symbols which it uses for guest to host console MMIO. The HTIT chardev implements the pre qom legacy interface consistent with the 16550a UART in 'hw/char/serial.c'. Signed-off-by: Michael Clark <m...@sifive.com> --- hw/riscv/riscv

[Qemu-devel] [PATCH v4 19/22] SiFive RISC-V Test Finisher

2018-02-04 Thread Michael Clark
Test finisher memory mapped device used to exit simulation. Signed-off-by: Michael Clark <m...@sifive.com> --- hw/riscv/sifive_test.c | 99 ++ include/hw/riscv/sifive_test.h | 48 2 files changed, 147 insertions(+) creat

[Qemu-devel] [PATCH v4 07/22] RISC-V GDB Stub

2018-02-04 Thread Michael Clark
GDB Register read and write routines. Reviewed-by: Richard Henderson <richard.hender...@linaro.org> Signed-off-by: Michael Clark <m...@sifive.com> --- target/riscv/gdbstub.c | 60 ++ 1 file changed, 60 insertions(+) create mode 100644

[Qemu-devel] [PATCH v4 02/22] RISC-V ELF Machine Definition

2018-02-04 Thread Michael Clark
Define RISC-V ELF machine EM_RISCV 243 Reviewed-by: Richard Henderson <richard.hender...@linaro.org> Signed-off-by: Michael Clark <m...@sifive.com> --- include/elf.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/elf.h b/include/elf.h index e8a515c..8e457fc 100644 -

[Qemu-devel] [PATCH v4 01/22] RISC-V Maintainers

2018-02-04 Thread Michael Clark
Add Michael Clark, Palmer Dabbelt, Sagar Karandikar and Bastian Koppelmann as RISC-V Maintainers. Signed-off-by: Michael Clark <m...@sifive.com> --- MAINTAINERS | 11 +++ 1 file changed, 11 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 0f952d4..d607039

[Qemu-devel] [PATCH v4 06/22] RISC-V FPU Support

2018-02-04 Thread Michael Clark
Helper routines for FPU instructions and NaN definitions. Signed-off-by: Michael Clark <m...@sifive.com> --- fpu/softfloat-specialize.h | 7 +- target/riscv/fpu_helper.c | 375 + 2 files changed, 379 insertions(+), 3 deletions(-) create mode

[Qemu-devel] [PATCH v4 04/22] RISC-V Disassembler

2018-02-04 Thread Michael Clark
and brevity reasons: ERROR: line over 90 characters ERROR: trailing statements should be on next line ERROR: space prohibited between function name and open parenthesis '(' Reviewed-by: Richard Henderson <richard.hender...@linaro.org> Signed-off-by: Michael Clark <m...@sifive.com>

[Qemu-devel] [PATCH v4 12/22] RISC-V HART Array

2018-02-04 Thread Michael Clark
Holds the state of a heterogenous array of RISC-V hardware threads. Signed-off-by: Michael Clark <m...@sifive.com> --- hw/riscv/riscv_hart.c | 95 +++ include/hw/riscv/riscv_hart.h | 45 2 files changed, 140 inse

[Qemu-devel] [PATCH v4 20/22] SiFive Freedom E300 RISC-V Machine

2018-02-04 Thread Michael Clark
This provides a RISC-V Board compatible with the the SiFive E300 SDK. The following machine is implemented: - 'sifive_e300'; CLINT, PLIC, UART, AON, GPIO, QSPI, PWM Signed-off-by: Michael Clark <m...@sifive.com> --- hw/riscv/sifive_e300.c

[Qemu-devel] [PATCH v4 13/22] SiFive RISC-V CLINT Block

2018-02-04 Thread Michael Clark
The CLINT (Core Local Interruptor) device provides real-time clock, timer and interprocessor interrupts based on SiFive's CLINT specification. Signed-off-by: Michael Clark <m...@sifive.com> --- hw/riscv/sifive_clint.c | 312 include/hw

[Qemu-devel] [PATCH v4 10/22] RISC-V Linux User Emulation

2018-02-04 Thread Michael Clark
Implementation of linux user emulation for RISC-V. Signed-off-by: Michael Clark <m...@sifive.com> --- linux-user/elfload.c | 22 +++ linux-user/main.c | 97 ++ linux-user/riscv/syscall_nr.h | 275 ++ linu

[Qemu-devel] [PATCH v4 17/22] SiFive RISC-V UART Device

2018-02-04 Thread Michael Clark
/serial.c'. Signed-off-by: Michael Clark <m...@sifive.com> --- hw/riscv/sifive_uart.c | 182 + include/hw/riscv/sifive_uart.h | 76 + 2 files changed, 258 insertions(+) create mode 100644 hw/riscv/sifive_uart.c create mode

[Qemu-devel] [PATCH v4 22/22] RISC-V Build Infrastructure

2018-02-04 Thread Michael Clark
' script is updated to add the RISC-V ELF magic. Expected checkpatch errors for consistency reasons: ERROR: line over 90 characters FILE: scripts/qemu-binfmt-conf.sh Signed-off-by: Michael Clark <m...@sifive.com> --- Makefile.objs | 1 + arch_

[Qemu-devel] [PATCH v4 15/22] RISC-V Spike Machines

2018-02-04 Thread Michael Clark
-by: Michael Clark <m...@sifive.com> --- hw/riscv/spike_v1_09.c | 204 ++ hw/riscv/spike_v1_10.c | 278 +++ include/hw/riscv/spike.h | 51 + 3 files changed, 533 insertions(+) create mode 100644 hw/riscv/spike

[Qemu-devel] [PATCH v4 18/22] SiFive RISC-V PRCI Block

2018-02-04 Thread Michael Clark
Simple model of the PRCI (Power, Reset, Clock, Interrupt) to emulate register reads made by the SDK BSP. Signed-off-by: Michael Clark <m...@sifive.com> --- hw/riscv/sifive_prci.c | 95 ++ include/hw/riscv/sifive_prci.h | 43

Re: [Qemu-devel] [PATCH v4 10/22] RISC-V Linux User Emulation

2018-02-05 Thread Michael Clark
On Tue, Feb 6, 2018 at 12:37 AM, Andreas Schwab <sch...@suse.de> wrote: > On Feb 05 2018, Michael Clark <m...@sifive.com> wrote: > > > diff --git a/linux-user/riscv/syscall_nr.h > b/linux-user/riscv/syscall_nr.h > > new file mode 100644 > > index 000..bd

Re: [Qemu-devel] [PATCH v5 06/23] Softfloat support for IEEE 754-201x minimumNumber/maximumNumber

2018-02-08 Thread Michael Clark
On Fri, Feb 9, 2018 at 3:35 AM, Richard Henderson < richard.hender...@linaro.org> wrote: > On 02/07/2018 05:28 PM, Michael Clark wrote: > > QEMU currently implements IEEE 754-2008 minNum/maxNum. This patch adds > > support for IEEE 754-201x minimumNumber/maximumNum

[Qemu-devel] [PATCH v1] Implement support for IEEE 754-201x minimumNumber/maximumNumber

2018-02-07 Thread Michael Clark
-by: Michael Clark <m...@sifive.com> --- fpu/softfloat.c | 41 +++-- include/fpu/softfloat.h | 4 2 files changed, 39 insertions(+), 6 deletions(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 433c5da..5793cc9 100644 --- a/fpu/softfloat.c +++

[Qemu-devel] [PATCH v5 08/23] RISC-V GDB Stub

2018-02-07 Thread Michael Clark
GDB Register read and write routines. Reviewed-by: Richard Henderson <richard.hender...@linaro.org> Signed-off-by: Michael Clark <m...@sifive.com> --- target/riscv/gdbstub.c | 60 ++ 1 file changed, 60 insertions(+) create mode 100644

[Qemu-devel] [PATCH v5 23/23] RISC-V Build Infrastructure

2018-02-07 Thread Michael Clark
' script is updated to add the RISC-V ELF magic. Expected checkpatch errors for consistency reasons: ERROR: line over 90 characters FILE: scripts/qemu-binfmt-conf.sh Reviewed-by: Richard Henderson <richard.hender...@linaro.org> Signed-off-by: Michael Clark <m...@sifive.com> --- M

[Qemu-devel] [PATCH v5 13/23] RISC-V HART Array

2018-02-07 Thread Michael Clark
Holds the state of a heterogenous array of RISC-V hardware threads. Signed-off-by: Michael Clark <m...@sifive.com> --- hw/riscv/riscv_hart.c | 95 +++ include/hw/riscv/riscv_hart.h | 45 2 files changed, 140 inse

[Qemu-devel] [PATCH v5 20/23] SiFive RISC-V Test Finisher

2018-02-07 Thread Michael Clark
Test finisher memory mapped device used to exit simulation. Signed-off-by: Michael Clark <m...@sifive.com> --- hw/riscv/sifive_test.c | 99 ++ include/hw/riscv/sifive_test.h | 48 2 files changed, 147 insertions(+) creat

[Qemu-devel] [PATCH v5 22/23] SiFive Freedom U500 RISC-V Machine

2018-02-07 Thread Michael Clark
This provides a RISC-V Board compatible with the the SiFive U500 SDK. The following machine is implemented: - 'sifive_u500'; CLINT, PLIC, UART, device-tree Signed-off-by: Michael Clark <m...@sifive.com> --- hw/riscv/sifive_u500.c | 338 + i

Re: [Qemu-devel] [PATCH v4 03/22] RISC-V CPU Core Definition

2018-02-07 Thread Michael Clark
On Wed, Feb 7, 2018 at 4:03 AM, Igor Mammedov <imamm...@redhat.com> wrote: > On Tue, 6 Feb 2018 11:09:56 +1300 > Michael Clark <m...@sifive.com> wrote: > > > On Tue, Feb 6, 2018 at 4:04 AM, Igor Mammedov <imamm...@redhat.com> > wrote: > > > > &g

[Qemu-devel] [PATCH v5 19/23] SiFive RISC-V PRCI Block

2018-02-07 Thread Michael Clark
Simple model of the PRCI (Power, Reset, Clock, Interrupt) to emulate register reads made by the SDK BSP. Signed-off-by: Michael Clark <m...@sifive.com> --- hw/riscv/sifive_prci.c | 95 ++ include/hw/riscv/sifive_prci.h | 43

[Qemu-devel] [PATCH v5 15/23] SiFive RISC-V PLIC Block

2018-02-07 Thread Michael Clark
The PLIC (Platform Level Interrupt Controller) device provides a parameterizable interrupt controller based on SiFive's PLIC specification. Signed-off-by: Michael Clark <m...@sifive.com> --- hw/riscv/sifive_plic.c | 554 + include/hw

[Qemu-devel] [PATCH v5 06/23] Softfloat support for IEEE 754-201x minimumNumber/maximumNumber

2018-02-07 Thread Michael Clark
-by: Michael Clark <m...@sifive.com> --- fpu/softfloat.c | 41 +++-- include/fpu/softfloat.h | 4 2 files changed, 39 insertions(+), 6 deletions(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 433c5da..5793cc9 100644 --- a/fpu/softfloat.c +++

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