/avocado/boot_linux_console.py
...
RESULTS: PASS 7 | ERROR 0 | FAIL 0 | SKIP 0 | WARN 0 | INTERRUPT 0 |
CANCEL 1
JOB TIME : 177.65 s
So for this patch:
Reviewed-by: Niek Linnenbank
Tested-by: Niek Linnenbank
About the BootLinuxConsole.test_arm_orangepi_bionic_20_08 test, I'd be
On Tue, Apr 30, 2024 at 4:12 PM Peter Maydell
wrote:
> On Mon, 29 Apr 2024 at 21:40, Niek Linnenbank
> wrote:
> >
> > Hi Peter, Strahinja,
> >
> > I can confirm that the orangepi-pc and cubieboard based tests are
> working OK using the newer kernel 6.6.16:
>
Hi Corey,
On Thu, Feb 6, 2020 at 10:09 PM Niek Linnenbank
wrote:
> Hi Corey,
>
> On Mon, Feb 3, 2020 at 2:10 PM Corey Minyard wrote:
>
>> On Sun, Feb 02, 2020 at 10:27:49PM +0100, Niek Linnenbank wrote:
>> > Hi Corey,
>> >
>> > Thanks for reviewi
s problem does not show.
I'm comparing traces and adding more low-level debug output to NetBSD and
QEMU to find the issue.
Also I processed the review remarks which were send so far.
Kind regards,
Niek
[1] https://www.netbsd.org/releases/formal-9/NetBSD-9.0.html
On Sun, Jan 19, 2020 at 1:51
On Wed, Feb 12, 2020 at 11:48 PM Philippe Mathieu-Daudé
wrote:
> )-.On Wed, Feb 12, 2020 at 10:31 PM Niek Linnenbank
> wrote:
> >
> > Hi Corey,
> >
> > On Thu, Feb 6, 2020 at 10:09 PM Niek Linnenbank <
> nieklinnenb...@gmail.com> wrote:
> >>
>
Hi Philippe,
On Wed, Feb 12, 2020 at 11:12 PM Philippe Mathieu-Daudé
wrote:
> On 2/12/20 10:47 PM, Niek Linnenbank wrote:
> > Hi all,
> >
> > Short status update regarding this series.
> >
> > Currently I am debugging booting NetBSD 9.0-RC2, which is recently
&g
-by: Niek Linnenbank
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
---
default-configs/arm-softmmu.mak | 1 +
include/hw/arm/allwinner-h3.h | 106 +++
hw/arm/allwinner-h3.c | 327
MAINTAINERS | 7
ttps://lists.gnu.org/archive/html/qemu-devel/2019-12/msg03265.html
https://github.com/nieklinnenbank/qemu/tree/allwinner-h3-v2
v1: https://lists.gnu.org/archive/html/qemu-devel/2019-12/msg00320.html
https://github.com/nieklinnenbank/qemu/tree/allwinner-h3-v1
With kind regards,
Niek Linnenban
-off-by: Niek Linnenbank
Reviewed-by: Gerd Hoffmann
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
---
hw/usb/hcd-ehci.h | 1 +
include/hw/arm/allwinner-h3.h | 8 +++
hw/arm/allwinner-h3.c | 44 +++
hw/usb/hcd-ehci
reference, this behaviour is documented
by the Linux Sunxi project wiki at:
https://linux-sunxi.org/BROM#U-Boot_SPL_limitations
Signed-off-by: Niek Linnenbank
---
include/hw/arm/allwinner-h3.h | 21 +
hw/arm/allwinner-h3.c | 18 ++
hw/arm/orangepi.c
Orange Pi PC machine.
Signed-off-by: Niek Linnenbank
Tested-by: KONRAD Frederic
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Philippe Mathieu-Daudé
Acked-by: Igor Mammedov
---
hw/arm/orangepi.c| 95
MAINTAINERS | 1 +
hw/arm
[NL: rename in commit message Raspbian to Armbian, remove vm.set_machine()]
Signed-off-by: Niek Linnenbank
---
tests/acceptance/boot_linux_console.py | 25 +
1 file changed, 25 insertions(+)
diff --git a/tests/acceptance/boot_linux_console.py
b/tests/acceptance/boot_lin
Signed-off-by: Niek Linnenbank
---
include/hw/arm/allwinner-h3.h | 3 +
include/hw/misc/allwinner-cpucfg.h | 52 ++
hw/arm/allwinner-h3.c | 9 +-
hw/misc/allwinner-cpucfg.c | 270 +
hw/misc/Makefile.objs | 1 +
hw/misc
The Clock Control Unit is responsible for clock signal generation,
configuration and distribution in the Allwinner H3 System on Chip.
This commit adds support for the Clock Control Unit which emulates
a simple read/write register interface.
Signed-off-by: Niek Linnenbank
Reviewed-by: Philippe
The Allwinner H3 System on Chip has an System Control
module that provides system wide generic controls and
device information. This commit adds support for the
Allwinner H3 System Control module.
Signed-off-by: Niek Linnenbank
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu
onsole: Requesting system reboot
console: reboot: Restarting system
PASS (48.32 s)
JOB TIME : 49.16 s
Signed-off-by: Philippe Mathieu-Daudé
[NL: rename in commit message Raspbian to Armbian, remove vm.set_machine()]
Signed-off-by: Niek Linnenbank
---
tests/acceptance/b
ANCEL 0
JOB TIME : 36.09 s
Note, this test only took ~65 seconds to run on Travis-CI, see: [3].
This test is based on a description from Niek Linnenbank from [4].
[1]
https://wiki.debian.org/InstallingDebianOn/Allwinner#Creating_a_bootable_SD_Card_with_u-boot
[2] https://wiki.netbsd.org/port
SDRAM controller.
Signed-off-by: Niek Linnenbank
---
include/hw/arm/allwinner-h3.h| 5 +
include/hw/misc/allwinner-h3-dramc.h | 106
hw/arm/allwinner-h3.c| 19 +-
hw/arm/orangepi.c| 6 +
hw/misc/allwinner-h3-dramc.c | 358
The Security Identifier device found in various Allwinner System on Chip
designs gives applications a per-board unique identifier. This commit
adds support for the Allwinner Security Identifier using a 128-bit
UUID value as input.
Signed-off-by: Niek Linnenbank
---
include/hw/arm/allwinner-h3.h
- /dev/null
+++ b/include/hw/rtc/allwinner-rtc.h
@@ -0,0 +1,134 @@
+/*
+ * Allwinner Real Time Clock emulation
+ *
+ * Copyright (C) 2019 Niek Linnenbank
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published b
spbian to Armbian, remove vm.set_machine()]
Signed-off-by: Niek Linnenbank
---
tests/acceptance/boot_linux_console.py | 41 ++
1 file changed, 41 insertions(+)
diff --git a/tests/acceptance/boot_linux_console.py
b/tests/acceptance/boot_linux_console.py
index dabc8ef2af
systemd[1]: Set hostname to .
Signed-off-by: Philippe Mathieu-Daudé
[NL: rename in commit message Raspbian to Armbian, remove vm.set_machine()]
[NL: changed test to boot from SD card via BootROM, added check for 7z]
Signed-off-by: Niek Linnenbank
---
tests/acceptance/boot_linux_conso
interface
* Transmit CRC calculation
Signed-off-by: Niek Linnenbank
---
include/hw/arm/allwinner-h3.h | 3 +
include/hw/net/allwinner-sun8i-emac.h | 99 +++
hw/arm/allwinner-h3.c | 16 +-
hw/arm/orangepi.c | 3 +
hw/net/allwinner-sun8i-emac.c
I/O
* Short/Long format command responses
* Auto-Stop command (CMD12)
* Insert & remove card detection
The following boards are extended with the SD host controller:
* Cubieboard (hw/arm/cubieboard.c)
* Orange Pi PC (hw/arm/orangepi.c)
Signed-off-by: Niek Linnenbank
Tested-by: Phil
-off-by: Niek Linnenbank
---
docs/orangepi.rst | 226 ++
MAINTAINERS | 1 +
2 files changed, 227 insertions(+)
create mode 100644 docs/orangepi.rst
diff --git a/docs/orangepi.rst b/docs/orangepi.rst
new file mode 100644
index 00
7;s a disk/sd card image file"
> where the expected use with real hardware is "dd the image
> file onto the SD card".
>
Yes, the description you gave here is indeed the issue.
And unfortunately in this particular case, the distro did not give a very
understandable
diagnostic error message.
Kind regards,
Niek
>
> thanks
> -- PMM
>
--
Niek Linnenbank
ted. Opts: (null)
Starting syslogd: OK
Starting klogd: OK
Running sysctl: OK
Initializing random number generator: OK
Saving random seed: [7.205617] random: dd: uninitialized urandom read
(512 bytes read)
OK
Starting network: OK
Welcome to Cubieboard2!
Cubieboard2 login:
Thanks!
Tested-by: Niek Linnenbank
Regards,
Niek
--
Niek Linnenbank
Hello Philippe,
On Tue, Dec 3, 2019 at 10:18 AM Philippe Mathieu-Daudé
wrote:
> On 12/2/19 10:09 PM, Niek Linnenbank wrote:
> > The Xunlong Orange Pi PC is an Allwinner H3 System on Chip
> > based embedded computer with mainline support in both U-Boot
> > and Linux. The bo
Hey Peter,
On Fri, Dec 6, 2019 at 3:25 PM Peter Maydell
wrote:
> On Mon, 2 Dec 2019 at 21:10, Niek Linnenbank
> wrote:
> >
> > This change ensures that the FPU can be accessed in Non-Secure mode
> > when the CPU core is reset using the arm_set_cpu_on() function call.
Hey Peter, Philippe,
On Fri, Dec 6, 2019 at 5:35 PM Philippe Mathieu-Daudé
wrote:
> On 12/6/19 3:27 PM, Peter Maydell wrote:
> > On Mon, 2 Dec 2019 at 21:10, Niek Linnenbank
> wrote:
> >>
> >> The Security Identifier device in Allwinner H3 System on Chip
>
Hi Philippe,
On Fri, Dec 6, 2019 at 6:41 AM Philippe Mathieu-Daudé
wrote:
> On 12/5/19 11:15 PM, Niek Linnenbank wrote:
> > Hello Philippe,
> >
> > On Tue, Dec 3, 2019 at 10:18 AM Philippe Mathieu-Daudé
> > mailto:phi...@redhat.com>> wrote:
> >
> >
Hi Philippe,
On Tue, Dec 3, 2019 at 9:47 AM Philippe Mathieu-Daudé
wrote:
> On 12/2/19 10:09 PM, Niek Linnenbank wrote:
> > Dear QEMU developers,
> >
> > Hereby I would like to contribute the following set of patches to QEMU
> > which add support for the Allwinne
Hi Gerd,
On Tue, Dec 10, 2019 at 9:29 AM Gerd Hoffmann wrote:
> On Tue, Dec 10, 2019 at 08:56:02AM +0100, Philippe Mathieu-Daudé wrote:
> > On 12/2/19 10:09 PM, Niek Linnenbank wrote:
> > > The Allwinner H3 System on Chip contains multiple USB 2.0 bus
> > > connect
Hi Philippe,
On Tue, Dec 10, 2019 at 9:59 AM Philippe Mathieu-Daudé
wrote:
> On 12/6/19 11:15 PM, Niek Linnenbank wrote:
> [...]
> > > > +static void orangepi_machine_init(MachineClass *mc)
> > > > +{
> > &g
Hi Philippe,
On Tue, Dec 10, 2019 at 10:02 AM Philippe Mathieu-Daudé
wrote:
> On 12/2/19 10:09 PM, Niek Linnenbank wrote:
> > The Allwinner H3 is a System on Chip containing four ARM Cortex A7
> > processor cores. Features and specifications include DDR2/DDR3 memory,
> >
work using the
steps described above by Philippe.
Regards,
Niek
[1]
https://www.kernel.org/doc/html/v4.10/dev-tools/gdb-kernel-debugging.html
>
> >
> > If someone want to work with me in this task, should know that I
> > don't have to much experience and I'm doing this job in my free time
> > (this means that I work only in my free time).
> >
> > I appreciate any kind of comment or advice.
> >
> > Thanks for your time ;)
> > EstebanB
> >
>
>
--
Niek Linnenbank
Hi Frederic,
On Tue, Dec 10, 2019 at 11:34 AM KONRAD Frederic <
frederic.kon...@adacore.com> wrote:
>
>
> Le 12/2/19 à 10:09 PM, Niek Linnenbank a écrit :
> > Dear QEMU developers,
> >
> > Hereby I would like to contribute the following set of patches to Q
Hi Philippe,
On Tue, Dec 10, 2019 at 9:26 AM Philippe Mathieu-Daudé
wrote:
> On 12/9/19 10:37 PM, Niek Linnenbank wrote:
> > Hi Philippe,
> >
> > On Tue, Dec 3, 2019 at 9:47 AM Philippe Mathieu-Daudé > <mailto:phi...@redhat.com>> wrote:
> >
> >
Ping!
Anyone would like to comment on this driver?
I finished the rework on all previous comments in this series.
Currently debugging the hflags error reported by Philippe.
After that, I'm ready to send out v2 of these patches.
Regards,
Niek
On Mon, Dec 2, 2019 at 10:10 PM Niek Linne
tb_cpu_state: Assertion `flags ==
rebuild_hflags_internal(env)' failed.
Aborted (core dumped)
$ git describe
v4.2.0
What should be the next step? Should this be reported as a bug?
Regards,
Niek
On Tue, Dec 10, 2019 at 9:12 PM Niek Linnenbank
wrote:
> Hi Philippe,
>
> On Tue, De
Hi Philippe,
On Fri, Dec 13, 2019 at 12:25 AM Philippe Mathieu-Daudé
wrote:
> Cc'ing Alex.
>
> On 12/13/19 12:07 AM, Niek Linnenbank wrote:
> > Hi Philippe,
> >
> > I have discovered that the hflags assertion error you reported is not
> > caused by the Al
tate
*target_cpu_state,
target_cpu->env.regs[0] = info->context_id;
}
+/* Ensure hflags is rebuild */
+arm_rebuild_hflags(&target_cpu->env);
+
/* Start the new CPU at the requested address */
cpu_set_pc(target_cpu_state, info->entry);
On Fri, Dec 6, 2019 at 9:01 P
On Fri, Dec 13, 2019 at 12:56 AM Philippe Mathieu-Daudé
wrote:
> Hi Niek,
>
> On 12/11/19 11:34 PM, Niek Linnenbank wrote:
> > Ping!
> >
> > Anyone would like to comment on this driver?
> >
> > I finished the rework on all previous comments in this series.
On Sat, Dec 14, 2019 at 2:59 PM Philippe Mathieu-Daudé
wrote:
> On 12/13/19 10:00 PM, Niek Linnenbank wrote:
> > On Fri, Dec 13, 2019 at 12:56 AM Philippe Mathieu-Daudé
> > mailto:phi...@redhat.com>> wrote:
> >
> > Hi Niek,
> >
> >
On Fri, Dec 13, 2019 at 12:56 AM Philippe Mathieu-Daudé
wrote:
> Hi Niek,
>
> On 12/11/19 11:34 PM, Niek Linnenbank wrote:
> > Ping!
> >
> > Anyone would like to comment on this driver?
> >
> > I finished the rework on all previous comments in this series.
On Fri, Dec 13, 2019 at 1:09 AM Philippe Mathieu-Daudé
wrote:
> On 12/2/19 10:09 PM, Niek Linnenbank wrote:
> > The Allwinner H3 System on Chip has an System Control
> > module that provides system wide generic controls and
> > device information. This commit adds support
On Mon, Dec 16, 2019 at 1:14 AM Philippe Mathieu-Daudé
wrote:
> On 12/16/19 12:07 AM, Niek Linnenbank wrote:
> >
> >
> > On Fri, Dec 13, 2019 at 12:56 AM Philippe Mathieu-Daudé
> > mailto:phi...@redhat.com>> wrote:
> >
> > Hi Niek,
> >
-by: Niek Linnenbank
---
default-configs/arm-softmmu.mak | 1 +
include/hw/arm/allwinner-h3.h | 80 +++
hw/arm/allwinner-h3.c | 360
MAINTAINERS | 7 +
hw/arm/Kconfig | 8 +
hw/arm/Makefile.objs
The Allwinner H3 System on Chip has an System Control
module that provides system wide generic controls and
device information. This commit adds support for the
Allwinner H3 System Control module.
Signed-off-by: Niek Linnenbank
---
include/hw/arm/allwinner-h3.h | 2 +
include/hw/misc
Orange Pi PC machine.
Signed-off-by: Niek Linnenbank
Tested-by: KONRAD Frederic
---
hw/arm/orangepi.c| 101 +++
MAINTAINERS | 1 +
hw/arm/Makefile.objs | 2 +-
3 files changed, 103 insertions(+), 1 deletion(-)
create mode 100644 hw/arm
the source file
* target/arm/arm-powerctl.c: invoke arm_rebuild_hflags() after setting CP15
bits
With kind regards,
Niek Linnenbank
[1] http://www.orangepi.org/downloadresources/
[2] https://buildroot.org/download.html
[3] https://www.armbian.com/orange-pi-pc/
Niek Linnenbank (10):
hw: a
-off-by: Niek Linnenbank
Reviewed-by: Gerd Hoffmann
---
hw/usb/hcd-ehci.h| 1 +
hw/arm/allwinner-h3.c| 28
hw/usb/hcd-ehci-sysbus.c | 17 +
3 files changed, 46 insertions(+)
diff --git a/hw/usb/hcd-ehci.h b/hw/usb/hcd-ehci.h
index
The Security Identifier device in Allwinner H3 System on Chip
gives applications a per-board unique identifier. This commit
adds support for the Allwinner H3 Security Identifier using
a 128-bit UUID value as input.
Signed-off-by: Niek Linnenbank
---
include/hw/arm/allwinner-h3.h | 2
-by: Niek Linnenbank
---
include/hw/arm/allwinner-h3.h | 2 +
include/hw/net/allwinner-h3-emac.h | 67 +++
hw/arm/allwinner-h3.c | 13 +
hw/arm/orangepi.c | 7 +
hw/net/allwinner-h3-emac.c | 831 +
hw/arm/Kconfig
Signed-off-by: Niek Linnenbank
---
include/hw/arm/allwinner-h3.h | 2 +
include/hw/misc/allwinner-h3-cpucfg.h | 42
hw/arm/allwinner-h3.c | 7 +
hw/misc/allwinner-h3-cpucfg.c | 288 ++
hw/misc/Makefile.objs | 1 +
hw
ff-by: Niek Linnenbank
---
target/arm/arm-powerctl.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/arm/arm-powerctl.c b/target/arm/arm-powerctl.c
index b064513d44..b75f813b40 100644
--- a/target/arm/arm-powerctl.c
+++ b/target/arm/arm-powerctl.c
@@ -127,6 +127,9 @@ static
The Clock Control Unit is responsible for clock signal generation,
configuration and distribution in the Allwinner H3 System on Chip.
This commit adds support for the Clock Control Unit which emulates
a simple read/write register interface.
Signed-off-by: Niek Linnenbank
---
include/hw/arm
format command responses
* Auto-Stop command (CMD12)
* Insert & remove card detection
Signed-off-by: Niek Linnenbank
---
include/hw/arm/allwinner-h3.h | 2 +
include/hw/sd/allwinner-h3-sdhost.h | 71 +++
hw/arm/allwinner-h3.c | 16 +
hw/arm/orange
2/msg01920.html
[2] https://lists.gnu.org/archive/html/qemu-devel/2019-12/msg02784.html
[3] https://lists.gnu.org/archive/html/qemu-devel/2019-12/msg02785.html
On Tue, Dec 17, 2019 at 12:36 AM Niek Linnenbank
wrote:
> After setting CP15 bits in arm_set_cpu_on() the cached hflags must
> be re
exception trap on the first FPU access for the
secondary cores under Linux.
Fixes: fc1120a7f5
Signed-off-by: Niek Linnenbank
---
target/arm/arm-powerctl.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/arm/arm-powerctl.c b/target/arm/arm-powerctl.c
index f77a950db6..b064513d44 100644
Signed-off-by: Niek Linnenbank
---
hw/arm/allwinner-h3.c | 11 +
hw/misc/Makefile.objs | 1 +
hw/misc/allwinner-h3-cpucfg.c | 280 ++
include/hw/arm/allwinner-h3.h | 2 +
include/hw/misc/allwinner-h3-cpucfg.h | 44
5
Orange Pi PC machine.
Signed-off-by: Niek Linnenbank
---
MAINTAINERS | 1 +
hw/arm/Makefile.objs | 2 +-
hw/arm/orangepi.c| 90
3 files changed, 92 insertions(+), 1 deletion(-)
create mode 100644 hw/arm/orangepi.c
diff --git a
0 0x4200 zImage
-> ext2load mmc 0 0x4300 sun8i-h2-plus-orangepi-zero.dtb
-> bootz 0x4200 - 0x4300
Looking forward to your review comments. I will do my best
to update the patches where needed.
With kind regards,
Niek Linnenbank
[1] http://www.orangepi.org/downlo
The Clock Control Unit is responsible for clock signal generation,
configuration and distribution in the Allwinner H3 System on Chip.
This commit adds support for the Clock Control Unit which emulates
a simple read/write register interface.
Signed-off-by: Niek Linnenbank
---
hw/arm/allwinner-h3
The Security Identifier device in Allwinner H3 System on Chip
gives applications a per-board unique identifier. This commit
adds support for the Allwinner H3 Security Identifier using
randomized data as input.
Signed-off-by: Niek Linnenbank
---
hw/arm/allwinner-h3.c | 11 ++
hw
-by: Niek Linnenbank
---
hw/arm/Kconfig | 1 +
hw/arm/allwinner-h3.c | 17 +
hw/arm/orangepi.c | 7 +
hw/net/Kconfig | 3 +
hw/net/Makefile.objs | 1 +
hw/net/allwinner-h3-emac.c | 786
-off-by: Niek Linnenbank
---
hw/arm/allwinner-h3.c| 20
hw/usb/hcd-ehci-sysbus.c | 17 +
hw/usb/hcd-ehci.h| 1 +
3 files changed, 38 insertions(+)
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
index 5566e979ec..afeb49c0ac 100644
--- a
-by: Niek Linnenbank
---
MAINTAINERS | 7 ++
default-configs/arm-softmmu.mak | 1 +
hw/arm/Kconfig | 8 ++
hw/arm/Makefile.objs| 1 +
hw/arm/allwinner-h3.c | 215
include/hw/arm/allwinner-h3.h
format command responses
* Auto-Stop command (CMD12)
* Insert & remove card detection
Signed-off-by: Niek Linnenbank
---
hw/arm/allwinner-h3.c | 20 +
hw/arm/orangepi.c | 17 +
hw/sd/Makefile.objs | 1 +
hw/sd/allwinner-h3-sdho
The Allwinner H3 System on Chip has an System Control
module that provides system wide generic controls and
device information. This commit adds support for the
Allwinner H3 System Control module.
Signed-off-by: Niek Linnenbank
---
hw/arm/allwinner-h3.c | 11 ++
hw/misc
Hello Philippe,
On Tue, Dec 3, 2019 at 10:02 AM Philippe Mathieu-Daudé
wrote:
> On 12/2/19 10:09 PM, Niek Linnenbank wrote:
> > Dear QEMU developers,
> >
> > Hereby I would like to contribute the following set of patches to QEMU
> > which add support for the Allwinne
Hello Frederic,
Thank you for your quick review comments!
I'll start working on v2 of the patches and include the changes you
suggested.
On Tue, Dec 3, 2019 at 10:33 AM KONRAD Frederic
wrote:
>
>
> Le 12/2/19 à 10:09 PM, Niek Linnenbank a écrit :
> > The Allwinner H3 System
hieu-Daudé
wrote:
> On 12/2/19 10:09 PM, Niek Linnenbank wrote:
> > Dear QEMU developers,
> >
> > Hereby I would like to contribute the following set of patches to QEMU
> > which add support for the Allwinner H3 System on Chip and the
> > Orange Pi PC machine. The f
Hello Philippe,
Thanks for your quick review comments!
I'll start working on a v2 of the patches and include the changes you
suggested.
Regards,
Niek
On Tue, Dec 3, 2019 at 10:18 AM Philippe Mathieu-Daudé
wrote:
> On 12/2/19 10:09 PM, Niek Linnenbank wrote:
> > The Xunlong Oran
On Wed, Dec 4, 2019 at 10:03 AM Philippe Mathieu-Daudé
wrote:
> On 12/3/19 8:33 PM, Niek Linnenbank wrote:
> > Hello Philippe,
> >
> > Thanks for your quick review comments!
> > I'll start working on a v2 of the patches and include the changes you
> > sug
On Wed, Dec 4, 2019 at 5:11 PM Aleksandar Markovic <
aleksandar.m.m...@gmail.com> wrote:
>
>
> On Monday, December 2, 2019, Niek Linnenbank
> wrote:
>
>> The Allwinner H3 System on Chip contains multiple USB 2.0 bus
>> connections which provide software
Hello Philippe,
On Wed, Dec 4, 2019 at 5:53 PM Philippe Mathieu-Daudé
wrote:
> Hi Niek,
>
> On 12/2/19 10:09 PM, Niek Linnenbank wrote:
> > The Allwinner H3 is a System on Chip containing four ARM Cortex A7
> > processor cores. Features and specifications include DDR2/DD
Hi Corey,
On Mon, Feb 3, 2020 at 2:10 PM Corey Minyard wrote:
> On Sun, Feb 02, 2020 at 10:27:49PM +0100, Niek Linnenbank wrote:
> > Hi Corey,
> >
> > Thanks for reviewing!
> >
> > On Mon, Jan 20, 2020 at 6:59 PM Corey Minyard
> wrote:
> >
>
Hi Philippe,
On Sun, Jan 19, 2020 at 11:30 PM Philippe Mathieu-Daudé
wrote:
> On 1/19/20 1:50 AM, Niek Linnenbank wrote:
> > From: Philippe Mathieu-Daudé
> >
> > This test boots Ubuntu Bionic on a OrangePi PC board.
> >
> > As it requires 1GB of storage, a
missing from the machine, the error
will be visible.
Regards,
Niek
On Sun, Feb 2, 2020 at 10:43 PM Niek Linnenbank
wrote:
> Hi Philippe,
>
> On Sun, Jan 19, 2020 at 8:02 PM Philippe Mathieu-Daudé
> wrote:
>
>> On 1/19/20 1:50 AM, Niek Linnenbank wrote:
>> > The All
ctClass
> *oc, void *data)
> sc->silicon_rev = AST2600_A0_SILICON_REV;
> sc->sram_size= 0x1;
> sc->spis_num = 2;
> +sc->ehcis_num= 2;
>
Since this field is only set once here, does it need to be part of the
class state?
> sc->wdts_num = 4;
> sc->macs_num = 4;
> sc->irqmap = aspeed_soc_ast2600_irqmap;
> --
> 2.17.1
>
>
>
Rest looks good to me.
Regards,
Niek
--
Niek Linnenbank
On Fri, Feb 7, 2020, 22:34 Guenter Roeck wrote:
> On Fri, Feb 07, 2020 at 10:25:01PM +0100, Niek Linnenbank wrote:
> > Hi Guenter,
> >
> > On Fri, Feb 7, 2020 at 6:46 PM Guenter Roeck wrote:
> >
> > > Initialize EHCI controllers on AST2600 using the existing
"hw/arm/raspi: Extract the board
model from the board revision"?
Regards,
Niek
> mc->init = raspi3_init;
> mc->block_default_type = IF_SD;
> mc->no_parallel = 1;
> --
> 2.21.1
>
>
--
Niek Linnenbank
[5]
> https://github.com/raspberrypi/linux/commit/d9fac63adac#diff-6722037d79570df5b392a49e0e006573R526
> [6]
> http://lists.infradead.org/pipermail/linux-rpi-kernel/2015-February/001268.html
>
> Cc: Zoltán Baldaszti
> Cc: Pekka Enberg
> Cc: Stephen Warren
> Cc: Kshitij Son
w/watchdog/allwinner-wdt.c
> new file mode 100644
> index 00..45a4a36ba7
> --- /dev/null
> +++ b/hw/watchdog/allwinner-wdt.c
> @@ -0,0 +1,416 @@
> +/*
> + * Allwinner Watchdog emulation
> + *
> + * Copyright (C) 2023 Strahinja Jankovic
> + *
> + * This file is
STRONGARM', if_true: files('strongarm.c'))
> arm_ss.add(when: 'CONFIG_ALLWINNER_A10', if_true:
> files('allwinner-a10.c', 'cubieboard.c'))
> arm_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3.c',
> 'orangepi.c'))
> +arm_ss.add(when: 'CONFIG_ALLWINNER_R40', if_true:
> files('allwinner-r40.c', 'bananapi_m2u.c'))
> arm_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2836.c', 'raspi.c'))
> arm_ss.add(when: 'CONFIG_STM32F100_SOC', if_true:
> files('stm32f100_soc.c'))
> arm_ss.add(when: 'CONFIG_STM32F205_SOC', if_true:
> files('stm32f205_soc.c'))
> diff --git a/include/hw/arm/allwinner-r40.h
> b/include/hw/arm/allwinner-r40.h
> new file mode 100644
> index 00..348bf25d6b
> --- /dev/null
> +++ b/include/hw/arm/allwinner-r40.h
> @@ -0,0 +1,110 @@
> +/*
> + * Allwinner R40/A40i/T3 System on Chip emulation
> + *
> + * Copyright (C) 2023 qianfan Zhao
> + *
> + * This program is free software: you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation, either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#ifndef HW_ARM_ALLWINNER_R40_H
> +#define HW_ARM_ALLWINNER_R40_H
> +
> +#include "qom/object.h"
> +#include "hw/arm/boot.h"
> +#include "hw/timer/allwinner-a10-pit.h"
> +#include "hw/intc/arm_gic.h"
> +#include "hw/sd/allwinner-sdhost.h"
> +#include "target/arm/cpu.h"
> +#include "sysemu/block-backend.h"
> +
> +enum {
> +AW_R40_DEV_SRAM_A1,
> +AW_R40_DEV_SRAM_A2,
> +AW_R40_DEV_SRAM_A3,
> +AW_R40_DEV_SRAM_A4,
> +AW_R40_DEV_MMC0,
> +AW_R40_DEV_MMC1,
> +AW_R40_DEV_MMC2,
> +AW_R40_DEV_MMC3,
> +AW_R40_DEV_CCU,
> +AW_R40_DEV_PIT,
> +AW_R40_DEV_UART0,
> +AW_R40_DEV_GIC_DIST,
> +AW_R40_DEV_GIC_CPU,
> +AW_R40_DEV_GIC_HYP,
> +AW_R40_DEV_GIC_VCPU,
> +AW_R40_DEV_SDRAM
> +};
> +
> +#define AW_R40_NUM_CPUS (4)
> +
> +/**
> + * Allwinner R40 object model
> + * @{
> + */
> +
> +/** Object type for the Allwinner R40 SoC */
> +#define TYPE_AW_R40 "allwinner-r40"
> +
> +/** Convert input object to Allwinner R40 state object */
> +OBJECT_DECLARE_SIMPLE_TYPE(AwR40State, AW_R40)
> +
> +/** @} */
> +
> +/**
> + * Allwinner R40 object
> + *
> + * This struct contains the state of all the devices
> + * which are currently emulated by the R40 SoC code.
> + */
> +#define AW_R40_NUM_MMCS 4
> +
> +struct AwR40State {
> +/*< private >*/
> +DeviceState parent_obj;
> +/*< public >*/
> +
> +ARMCPU cpus[AW_R40_NUM_CPUS];
> +const hwaddr *memmap;
> +AwA10PITState timer;
> +AwSdHostState mmc[AW_R40_NUM_MMCS];
> +GICState gic;
> +MemoryRegion sram_a1;
> +MemoryRegion sram_a2;
> +MemoryRegion sram_a3;
> +MemoryRegion sram_a4;
> +};
> +
> +/**
> + * Emulate Boot ROM firmware setup functionality.
> + *
> + * A real Allwinner R40 SoC contains a Boot ROM
> + * which is the first code that runs right after
> + * the SoC is powered on. The Boot ROM is responsible
> + * for loading user code (e.g. a bootloader) from any
> + * of the supported external devices and writing the
> + * downloaded code to internal SRAM. After loading the SoC
> + * begins executing the code written to SRAM.
> + *
> + * This function emulates the Boot ROM by copying 32 KiB
> + * of data from the given block device and writes it to
> + * the start of the first internal SRAM memory.
> + *
> + * @s: Allwinner R40 state object pointer
> + * @blk: Block backend device object pointer
> + * @unit: the mmc control's unit
> + */
> +bool allwinner_r40_bootrom_setup(AwR40State *s, BlockBackend *blk, int
> unit);
> +
> +#endif /* HW_ARM_ALLWINNER_R40_H */
> --
> 2.25.1
>
>
With the above resolved/answered:
Reviewed-by: Niek Linnenbank
--
Niek Linnenbank
it which emulates
> a simple read/write register interface.
>
> Signed-off-by: qianfan Zhao
>
Reviewed-by: Niek Linnenbank
> ---
> hw/arm/allwinner-r40.c | 8 +-
> hw/misc/allwinner-r40-ccu.c | 209
> hw/misc/meson.bu
s->mmc[i],
> -TYPE_AW_SDHOST_SUN5I);
> +TYPE_AW_SDHOST_SUN50I_A64);
> }
>
> object_initialize_child(obj, "twi0", &s->i2c0, TYPE_AW_I2C_SUN6I);
> --
> 2.25.1
>
>
--
Niek Linnenbank
On Tue, Mar 28, 2023 at 7:48 AM wrote:
> From: qianfan Zhao
>
> Add documents for Banana Pi M2U
>
> Signed-off-by: qianfan Zhao
>
Reviewed-by: Niek Linnenbank
> ---
> docs/system/arm/bananapi_m2u.rst | 138 +++
> 1 file changed, 138 i
W_SDHOST "-sun50i-a64-emmc"
> +
> /** @} */
>
> /**
> @@ -110,6 +116,7 @@ struct AwSdHostState {
> uint32_t startbit_detect; /**< eMMC DDR Start Bit Detection Control
> */
> uint32_t response_crc; /**< Response CRC */
> uint32_t data_crc[8]; /**< Data CRC */
> +uint32_t sample_delay; /**< Sample delay control */
> uint32_t status_crc;/**< Status CRC */
>
> /** @} */
> @@ -132,6 +139,8 @@ struct AwSdHostClass {
> size_t max_desc_size;
> bool is_sun4i;
>
> +/** does the IP block support autocalibration? */
> +bool can_calibrate;
> };
>
> #endif /* HW_SD_ALLWINNER_SDHOST_H */
> --
> 2.25.1
>
>
In this patch, I don't see any update to the new allwinner-r40.c file.
If you make the required changes to allwinner-r40.c in this patch, you can
also avoid having patch 08.
Regards,
Niek
--
Niek Linnenbank
:
Tested-by: Niek Linnenbank
On Tue, Mar 28, 2023 at 7:49 AM wrote:
> From: qianfan Zhao
>
> Add test case for booting from initrd and sd card.
>
> Signed-off-by: qianfan Zhao
> ---
> tests/avocado/boot_linux_console.py | 176
> 1 file
t; differ in applicable temperatures range (industrial and military).
>
> Signed-off-by: qianfan Zhao
>
Reviewed-by: Niek Linnenbank
> ---
> hw/arm/Kconfig | 10 +
> hw/arm/allwinner-r40.c | 418 +
> hw/arm/banana
it which emulates
> a simple read/write register interface.
>
> Signed-off-by: qianfan Zhao
>
Reviewed-by: Niek Linnenbank
> ---
> hw/arm/allwinner-r40.c | 8 +-
> hw/misc/allwinner-r40-ccu.c | 209
> hw/misc/meson.bu
#x27;omap2.c'))
> arm_ss.add(when: 'CONFIG_STRONGARM', if_true: files('strongarm.c'))
> arm_ss.add(when: 'CONFIG_ALLWINNER_A10', if_true:
> files('allwinner-a10.c', 'cubieboard.c'))
> arm_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3.c',
> 'orangepi.c'))
> +arm_ss.add(when: 'CONFIG_ALLWINNER_R40', if_true:
> files('allwinner-r40.c', 'bananapi_m2u.c'))
> arm_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2836.c', 'raspi.c'))
> arm_ss.add(when: 'CONFIG_STM32F100_SOC', if_true:
> files('stm32f100_soc.c'))
> arm_ss.add(when: 'CONFIG_STM32F205_SOC', if_true:
> files('stm32f205_soc.c'))
> diff --git a/include/hw/arm/allwinner-r40.h
> b/include/hw/arm/allwinner-r40.h
> new file mode 100644
> index 00..348bf25d6b
> --- /dev/null
> +++ b/include/hw/arm/allwinner-r40.h
> @@ -0,0 +1,110 @@
> +/*
> + * Allwinner R40/A40i/T3 System on Chip emulation
> + *
> + * Copyright (C) 2023 qianfan Zhao
> + *
> + * This program is free software: you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation, either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#ifndef HW_ARM_ALLWINNER_R40_H
> +#define HW_ARM_ALLWINNER_R40_H
> +
> +#include "qom/object.h"
> +#include "hw/arm/boot.h"
> +#include "hw/timer/allwinner-a10-pit.h"
> +#include "hw/intc/arm_gic.h"
> +#include "hw/sd/allwinner-sdhost.h"
> +#include "target/arm/cpu.h"
> +#include "sysemu/block-backend.h"
> +
> +enum {
> +AW_R40_DEV_SRAM_A1,
> +AW_R40_DEV_SRAM_A2,
> +AW_R40_DEV_SRAM_A3,
> +AW_R40_DEV_SRAM_A4,
> +AW_R40_DEV_MMC0,
> +AW_R40_DEV_MMC1,
> +AW_R40_DEV_MMC2,
> +AW_R40_DEV_MMC3,
> +AW_R40_DEV_CCU,
> +AW_R40_DEV_PIT,
> +AW_R40_DEV_UART0,
> +AW_R40_DEV_GIC_DIST,
> +AW_R40_DEV_GIC_CPU,
> +AW_R40_DEV_GIC_HYP,
> +AW_R40_DEV_GIC_VCPU,
> +AW_R40_DEV_SDRAM
> +};
> +
> +#define AW_R40_NUM_CPUS (4)
> +
> +/**
> + * Allwinner R40 object model
> + * @{
> + */
> +
> +/** Object type for the Allwinner R40 SoC */
> +#define TYPE_AW_R40 "allwinner-r40"
> +
> +/** Convert input object to Allwinner R40 state object */
> +OBJECT_DECLARE_SIMPLE_TYPE(AwR40State, AW_R40)
> +
> +/** @} */
> +
> +/**
> + * Allwinner R40 object
> + *
> + * This struct contains the state of all the devices
> + * which are currently emulated by the R40 SoC code.
> + */
> +#define AW_R40_NUM_MMCS 4
> +
> +struct AwR40State {
> +/*< private >*/
> +DeviceState parent_obj;
> +/*< public >*/
> +
> +ARMCPU cpus[AW_R40_NUM_CPUS];
> +const hwaddr *memmap;
> +AwA10PITState timer;
> +AwSdHostState mmc[AW_R40_NUM_MMCS];
> +GICState gic;
> +MemoryRegion sram_a1;
> +MemoryRegion sram_a2;
> +MemoryRegion sram_a3;
> +MemoryRegion sram_a4;
> +};
> +
> +/**
> + * Emulate Boot ROM firmware setup functionality.
> + *
> + * A real Allwinner R40 SoC contains a Boot ROM
> + * which is the first code that runs right after
> + * the SoC is powered on. The Boot ROM is responsible
> + * for loading user code (e.g. a bootloader) from any
> + * of the supported external devices and writing the
> + * downloaded code to internal SRAM. After loading the SoC
> + * begins executing the code written to SRAM.
> + *
> + * This function emulates the Boot ROM by copying 32 KiB
> + * of data from the given block device and writes it to
> + * the start of the first internal SRAM memory.
> + *
> + * @s: Allwinner R40 state object pointer
> + * @blk: Block backend device object pointer
> + * @unit: the mmc control's unit
> + */
> +bool allwinner_r40_bootrom_setup(AwR40State *s, BlockBackend *blk, int
> unit);
> +
> +#endif /* HW_ARM_ALLWINNER_R40_H */
> --
> 2.25.1
>
>
--
Niek Linnenbank
_UART3 = 4,
>
Since you put the addition of UART1-7 in this patch, probably it makes
sense to have adding the lines 'AW_R40_GIC_SPI_UART1/2/3' also part of this
patch.
With the two above remarks resolved, the patch looks good to me.
Reviewed-by: Niek Linnenbank
Regards,
ta rate
> up to 400kbit/s.
>
> Signed-off-by: qianfan Zhao
>
Reviewed-by: Niek Linnenbank
> ---
> hw/arm/allwinner-r40.c | 11 ++-
> include/hw/arm/allwinner-r40.h | 3 +++
> 2 files changed, 13 insertions(+), 1 deletion(-)
>
> diff --git a/hw/arm/all
+static const TypeInfo axp209_info = {
> +.name = TYPE_AXP209_PMU,
> +.parent = TYPE_AXP2XX,
> +.class_init = axp209_class_init
> +};
> +
> +static void axp221_class_init(ObjectClass *oc, void *data)
> +{
> +AXP2xxClass *sc = AXP2XX_CLASS(oc);
> +
> +sc->reset_enter = axp221_reset_enter;
> +}
> +
> +static const TypeInfo axp221_info = {
> +.name = TYPE_AXP221_PMU,
> +.parent = TYPE_AXP2XX,
> +.class_init = axp221_class_init,
> +};
> +
> +static void axp2xx_register_devices(void)
> +{
> +type_register_static(&axp2xx_info);
> +type_register_static(&axp209_info);
> +type_register_static(&axp221_info);
> +}
> +
> +type_init(axp2xx_register_devices);
> diff --git a/hw/misc/meson.build b/hw/misc/meson.build
> index 96e35f1cdb..1db034 100644
> --- a/hw/misc/meson.build
> +++ b/hw/misc/meson.build
> @@ -45,7 +45,7 @@ softmmu_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true:
> files('allwinner-h3-dramc.c
> softmmu_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true:
> files('allwinner-h3-sysctrl.c'))
> softmmu_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true:
> files('allwinner-sid.c'))
> softmmu_ss.add(when: 'CONFIG_ALLWINNER_R40', if_true:
> files('allwinner-r40-ccu.c'))
> -softmmu_ss.add(when: 'CONFIG_AXP209_PMU', if_true: files('axp209.c'))
> +softmmu_ss.add(when: 'CONFIG_AXP2XX_PMU', if_true: files('axp2xx.c'))
> softmmu_ss.add(when: 'CONFIG_REALVIEW', if_true: files('arm_sysctl.c'))
> softmmu_ss.add(when: 'CONFIG_NSERIES', if_true: files('cbus.c'))
> softmmu_ss.add(when: 'CONFIG_ECCMEMCTL', if_true: files('eccmemctl.c'))
> diff --git a/hw/misc/trace-events b/hw/misc/trace-events
> index c47876a902..24cdec83fe 100644
> --- a/hw/misc/trace-events
> +++ b/hw/misc/trace-events
> @@ -23,10 +23,10 @@ allwinner_sid_write(uint64_t offset, uint64_t data,
> unsigned size) "offset 0x%"
> avr_power_read(uint8_t value) "power_reduc read value:%u"
> avr_power_write(uint8_t value) "power_reduc write value:%u"
>
> -# axp209.c
> -axp209_rx(uint8_t reg, uint8_t data) "Read reg 0x%" PRIx8 " : 0x%" PRIx8
> -axp209_select(uint8_t reg) "Accessing reg 0x%" PRIx8
> -axp209_tx(uint8_t reg, uint8_t data) "Write reg 0x%" PRIx8 " : 0x%" PRIx8
> +# axp2xx
> +axp2xx_rx(uint8_t reg, uint8_t data) "Read reg 0x%" PRIx8 " : 0x%" PRIx8
> +axp2xx_select(uint8_t reg) "Accessing reg 0x%" PRIx8
> +axp2xx_tx(uint8_t reg, uint8_t data) "Write reg 0x%" PRIx8 " : 0x%" PRIx8
>
> # eccmemctl.c
> ecc_mem_writel_mer(uint32_t val) "Write memory enable 0x%08x"
> --
> 2.25.1
>
>
--
Niek Linnenbank
cpus[AW_R40_NUM_CPUS];
> const hwaddr *memmap;
> AwA10PITState timer;
> AwSdHostState mmc[AW_R40_NUM_MMCS];
> AwR40ClockCtlState ccu;
> +AwR40DramCtlState dramc;
> AWI2CState i2c0;
> GICState gic;
> MemoryRegion sram_a1;
> diff --git a/include/hw/misc/allwinner-r40-dramc.h
> b/include/hw/misc/allwinner-r40-dramc.h
> new file mode 100644
> index 00..6a1a3a7893
> --- /dev/null
> +++ b/include/hw/misc/allwinner-r40-dramc.h
> @@ -0,0 +1,108 @@
> +/*
> + * Allwinner R40 SDRAM Controller emulation
> + *
> + * Copyright (C) 2023 qianfan Zhao
> + *
> + * This program is free software: you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation, either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#ifndef HW_MISC_ALLWINNER_R40_DRAMC_H
> +#define HW_MISC_ALLWINNER_R40_DRAMC_H
> +
> +#include "qom/object.h"
> +#include "hw/sysbus.h"
> +#include "exec/hwaddr.h"
> +
> +/**
> + * Constants
> + * @{
> + */
> +
> +/** Highest register address used by DRAMCOM module */
> +#define AW_R40_DRAMCOM_REGS_MAXADDR (0x804)
> +
> +/** Total number of known DRAMCOM registers */
> +#define AW_R40_DRAMCOM_REGS_NUM (AW_R40_DRAMCOM_REGS_MAXADDR / \
> + sizeof(uint32_t))
> +
> +/** Highest register address used by DRAMCTL module */
> +#define AW_R40_DRAMCTL_REGS_MAXADDR (0x88c)
> +
> +/** Total number of known DRAMCTL registers */
> +#define AW_R40_DRAMCTL_REGS_NUM (AW_R40_DRAMCTL_REGS_MAXADDR / \
> + sizeof(uint32_t))
> +
> +/** Highest register address used by DRAMPHY module */
> +#define AW_R40_DRAMPHY_REGS_MAXADDR (0x4)
> +
> +/** Total number of known DRAMPHY registers */
> +#define AW_R40_DRAMPHY_REGS_NUM (AW_R40_DRAMPHY_REGS_MAXADDR / \
> + sizeof(uint32_t))
> +
> +/** @} */
> +
> +/**
> + * Object model
> + * @{
> + */
> +
> +#define TYPE_AW_R40_DRAMC "allwinner-r40-dramc"
> +OBJECT_DECLARE_SIMPLE_TYPE(AwR40DramCtlState, AW_R40_DRAMC)
> +
> +/** @} */
> +
> +/**
> + * Allwinner R40 SDRAM Controller object instance state.
> + */
> +struct AwR40DramCtlState {
> +/*< private >*/
> +SysBusDevice parent_obj;
> +/*< public >*/
> +
> +/** Physical base address for start of RAM */
> +hwaddr ram_addr;
> +
> +/** Total RAM size in megabytes */
> +uint32_t ram_size;
> +
> +uint8_t set_row_bits;
> +uint8_t set_bank_bits;
> +uint8_t set_col_bits;
> +
> +/**
> + * @name Memory Regions
> + * @{
> + */
> +MemoryRegion dramcom_iomem;/**< DRAMCOM module I/O registers */
> +MemoryRegion dramctl_iomem;/**< DRAMCTL module I/O registers */
> +MemoryRegion dramphy_iomem;/**< DRAMPHY module I/O registers */
> +MemoryRegion dram_high;/**< The high 1G dram for dualrank
> detect */
> +MemoryRegion detect_cells; /**< DRAM memory cells for auto detect
> */
> +
> +/** @} */
> +
> +/**
> + * @name Hardware Registers
> + * @{
> + */
> +
> +uint32_t dramcom[AW_R40_DRAMCOM_REGS_NUM]; /**< DRAMCOM registers */
> +uint32_t dramctl[AW_R40_DRAMCTL_REGS_NUM]; /**< DRAMCTL registers */
> +uint32_t dramphy[AW_R40_DRAMPHY_REGS_NUM] ;/**< DRAMPHY registers */
> +
> +/** @} */
> +
> +};
> +
> +#endif /* HW_MISC_ALLWINNER_R40_DRAMC_H */
> --
> 2.25.1
>
>
Looks good to me.
Reviewed-by: Niek Linnenbank
--
Niek Linnenbank
; *data)
> @@ -888,6 +920,24 @@ static void
> allwinner_sdhost_sun5i_class_init(ObjectClass *klass, void *data)
> sc->is_sun4i = false;
> }
>
> +static void allwinner_sdhost_sun50i_a64_class_init(ObjectClass *klass,
> +
/allwinner-r40-ccu.h"
> #include "hw/misc/allwinner-r40-dramc.h"
> #include "hw/i2c/allwinner-i2c.h"
> +#include "hw/net/allwinner_emac.h"
> +#include "hw/net/allwinner-sun8i-emac.h"
> #include "target/arm/cpu.h"
> #include "sysemu/block-backend.h"
>
> @@ -36,6 +38,7 @@ enum {
> AW_R40_DEV_SRAM_A2,
> AW_R40_DEV_SRAM_A3,
> AW_R40_DEV_SRAM_A4,
> +AW_R40_DEV_EMAC,
> AW_R40_DEV_MMC0,
> AW_R40_DEV_MMC1,
> AW_R40_DEV_MMC2,
> @@ -51,6 +54,7 @@ enum {
> AW_R40_DEV_UART6,
> AW_R40_DEV_UART7,
> AW_R40_DEV_TWI0,
> +AW_R40_DEV_GMAC,
> AW_R40_DEV_GIC_DIST,
> AW_R40_DEV_GIC_CPU,
> AW_R40_DEV_GIC_HYP,
> @@ -103,6 +107,8 @@ struct AwR40State {
> AwR40ClockCtlState ccu;
> AwR40DramCtlState dramc;
> AWI2CState i2c0;
> +AwEmacState emac;
> +AwSun8iEmacState gmac;
> GICState gic;
> MemoryRegion sram_a1;
> MemoryRegion sram_a2;
> --
> 2.25.1
>
>
Regards,
Niek
--
Niek Linnenbank
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