[Qemu-devel] [Bug 1777777] [NEW] arm9 clock pending (SP804)

2018-06-20 Thread RTOS Pharos
Public bug reported: Hello all, I'm using the versatilepb board and the timer Interrupt Mask Status register (offset 0x14 of the SP804) does not seem to be working properly on the latest qemu-2.12. I tried on the 2.5 (i believe this is the mainstream version that comes with Linux) and it works

[Qemu-devel] [Bug 1777777] Re: arm9 clock pending (SP804)

2018-07-30 Thread RTOS Pharos
Hello, Let me explain a bit how to reproduce the problem. I'm developing a RTOS with qemu (and boards,etc) - https://sourceforge.net/projects/rtospharos/. The first version used ARM926 with the versatilepb board and I used the qemu 2.5 version. In my test (to check that the RTOS is working

[Qemu-devel] [Bug 1817846] [NEW] Qemu 3.1 Aarch64 TLBI VAE1, x0

2019-02-27 Thread RTOS Pharos
Public bug reported: Hello, In my code I'm trying to remove some permissions to a 4KiB MMU descriptor. After that I invalidate the MMU with TLBI VAE1, x0 where x0 is the start of the address of the 4 KiB page. In Qemu 2.12 this did not work, but I worked around it with: /* invalidate

[Qemu-devel] [Bug 1815078] [NEW] Qemu 3.1.0 risc-v mie.MEIE

2019-02-07 Thread RTOS Pharos
Public bug reported: Hello all, There is a bug in qemu for Risc-v, related to the mie register: when we try to set the MEIE bit (11) nothing is done, even when we are running at machine mode. Li a0 , 1 << 11 Csrs mie , a0 And when we read mie it is as though nothing was done. Going through

[Qemu-devel] [Bug 1815721] [NEW] RISC-V PLIC enable interrupt for multicore

2019-02-12 Thread RTOS Pharos
Public bug reported: Hello all, There is a bug in Qemu related to the enabling of external interrupts for multicores (Virt machine). After correcting Qemu as described in #1815078 (https://bugs.launchpad.net/qemu/+bug/1815078), when we try to enable interrupts for core 1 at address 0x0C00_2080

[Qemu-devel] [Bug 1815078] Re: Qemu 3.1.0 risc-v mie.MEIE

2019-02-13 Thread RTOS Pharos
Good news, Thanks -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1815078 Title: Qemu 3.1.0 risc-v mie.MEIE Status in QEMU: New Bug description: Hello all, There is a bug in qemu for

[Qemu-devel] [Bug 1815078] Re: Qemu 3.1.0 risc-v mie.MEIE

2019-02-13 Thread RTOS Pharos
So I tried it but got the error: ERROR: missing file ../qemu-3.1.0/ui/keycodemapdb/README This is not a GIT checkout but module content appears to be missing. Do not use 'git archive' or GitHub download links to acquire QEMU source archives. Non-GIT builds are only supported with source archives

[Qemu-devel] [Bug 1815078] Re: Qemu 3.1.0 risc-v mie.MEIE

2019-02-13 Thread RTOS Pharos
OK, I'll give it a try and give you some feedback. Thanks -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1815078 Title: Qemu 3.1.0 risc-v mie.MEIE Status in QEMU: Fix Committed Bug

[Bug 1777777] Re: arm9 clock pending (SP804)

2019-09-27 Thread RTOS Pharos
Thank you for checking this issue. I looked at the ptimer code, like you said. Just one question: isn't this used by other hw as well? Maybe this problem is more general... I also tried (basically) the same example on a aarch64 (raspberry pi3), and I don't find any problems there. Maybe could

[Bug 1777777] Re: arm9 clock pending (SP804)

2019-09-23 Thread RTOS Pharos
Forgot to state the qemu argument, it's this one: ~/cross-compiler/qemu/2.5/bin/qemu-system-arm -M versatilepb -m 128M -nographic -kernel myApplication -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU.

[Bug 1777777] Re: arm9 clock pending (SP804)

2019-09-23 Thread RTOS Pharos
Sorry to have taken some time to answer. Created the binary with the test. Here is the output when it fails (tested in Qemu 2.12): Checked 0 times if the time is always increasing Checked 10 times if the time is always increasing Checked 20 times if the time is always increasing Checked

[Bug 1815721] Re: RISC-V PLIC enable interrupt for multicore

2020-03-25 Thread RTOS Pharos
Thank you for the explanation. I actually built it for "Virt" machine. I'll try the "sifive_u" when I can. But I guess your explanation is correct so this bug could be closed from my part. -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to

[Bug 1815721] Re: RISC-V PLIC enable interrupt for multicore

2020-03-24 Thread RTOS Pharos
Hi, After some debugging (and luck), the problem (at least in the Virt board) was that the PLIC code inside QEMU addresses the core x 2 instead of just the core (core=hart). That is why it worked for core 0 (0x2 = 0) but for core 1 it has to address the PLIC memory area for core 2. For example,