Re: [Qemu-devel] Could configure generate QEMU's linker scripts?

2013-05-21 Thread Richard Henderson
On 05/21/2013 10:51 AM, Ed Maste wrote: On 20 May 2013 13:21, Richard Henderson r...@twiddle.net wrote: In general I believe that using the -Ttext-segment ADDR flag for ld would completely obviate the need for even editing the link script. That sounds cleaner, although there's a wrinkle

Re: [Qemu-devel] [PATCH 2/4] tcg/aarch64: implement new TCG target for aarch64

2013-05-23 Thread Richard Henderson
On 05/23/2013 01:18 AM, Claudio Fontana wrote: +static inline void patch_reloc(uint8_t *code_ptr, int type, + tcg_target_long value, tcg_target_long addend) +{ +switch (type) { +case R_AARCH64_JUMP26: +case R_AARCH64_CALL26: +

Re: [Qemu-devel] [PATCH 01/10] target-arm: Don't use TCGv when we mean TCGv_i32

2013-05-23 Thread Richard Henderson
1 file changed, 229 insertions(+), 224 deletions(-) Reviewed-by: Richard Henderson r...@twiddle.net r~

Re: [Qemu-devel] [PATCH 02/10] target-arm: Remove gen_ld64() and gen_st64()

2013-05-23 Thread Richard Henderson
(-) Reviewed-by: Richard Henderson r...@twiddle.net r~

Re: [Qemu-devel] [PATCH 03/10] target-arm: Remove uses of gen_{ld, st}* from iWMMXt code

2013-05-23 Thread Richard Henderson
On 05/23/2013 04:59 AM, Peter Maydell wrote: Signed-off-by: Peter Maydell peter.mayd...@linaro.org --- target-arm/translate.c | 18 ++ 1 file changed, 10 insertions(+), 8 deletions(-) Reviewed-by: Richard Henderson r...@twiddle.net r~

Re: [Qemu-devel] [PATCH 10/10] target-arm: Abstract out load/store from a vaddr in AArch32

2013-05-23 Thread Richard Henderson
a place to put the zero extension of the vaddr and the extension/truncation of the data value. Apart from the function definitions most of this patch is a simple s/tcg_gen_qemu_/gen_aa32_/. Signed-off-by: Peter Maydell peter.mayd...@linaro.org Reviewed-by: Richard Henderson r

Re: [Qemu-devel] [PATCH 2/4] tcg/aarch64: implement new TCG target for aarch64

2013-05-24 Thread Richard Henderson
On 05/24/2013 01:53 AM, Claudio Fontana wrote: No real need to special case zero; it's just an extra test slowing down the compiler. Yes, we need to handle the special case zero. Otherwise no instruction at all would be emitted for value 0. Hmm, true. Although I'd been thinking more along

Re: [Qemu-devel] [PATCH 2/4] tcg/aarch64: implement new TCG target for aarch64

2013-05-24 Thread Richard Henderson
On 05/24/2013 10:08 AM, Peter Maydell wrote: Where's the waste? The procedure calling standard mandates that we set FP up, so it's not like we can use it as a general purpose register anywhere. Well, the calling standard is another document that's not available yet, so obviously I don't know

Re: [Qemu-devel] [PATCH 2/4] tcg/aarch64: implement new TCG target for aarch64

2013-05-24 Thread Richard Henderson
On 05/24/2013 10:28 AM, Peter Maydell wrote: It does what a frame pointer usually does, ie permits the debugger (and other tools) to unwind the stack. And is there perchance a reason we've been dropping the frame pointer from new abis, like x86_64? On the side unwind information does the job

[Qemu-devel] [PATCH 2/2] tcg: Fix high_pc fields in .debug_info

2013-05-24 Thread Richard Henderson
I don't think the debugger actually looks at this for anything, using the correct .debug_frame contents, but might as well get it all correct. Signed-off-by: Richard Henderson r...@twiddle.net --- tcg/tcg.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tcg/tcg.c b/tcg

[Qemu-devel] [PATCH 1/2] tcg-arm: Implement tcg_register_jit

2013-05-24 Thread Richard Henderson
Allows unwinding past the code_gen_buffer. Signed-off-by: Richard Henderson r...@twiddle.net --- tcg/arm/tcg-target.c | 91 ++-- 1 file changed, 82 insertions(+), 9 deletions(-) diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c index

Re: [Qemu-devel] [PATCH 00/22] Memory/IOMMU patches, part 2: unassigned access detection

2013-05-24 Thread Richard Henderson
memory: correctly handle endian-swapped 64-bit accesses exec: just use io_mem_read/io_mem_write for 8-byte I/O accesses memory: propagate errors on I/O dispatch memory: add return value to address_space_rw/read/write Reviewed-by: Richard Henderson r...@twiddle.net r~

Re: [Qemu-devel] [PATCH] i386/translate: ignore 0x67 (PREFIX_ADR) on TARGET_X86_64 CODE64()

2013-05-25 Thread Richard Henderson
On 2013-05-24 14:37, Laszlo Ersek wrote: @@ -4813,7 +4813,11 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, /* 0x66 is ignored if rex.w is set */ dflag = 2; } -if (!(prefixes PREFIX_ADR)) { +if (prefixes PREFIX_ADR) {

Re: [Qemu-devel] [PATCH 2/4] tcg/aarch64: implement new TCG target for aarch64

2013-05-27 Thread Richard Henderson
On 2013-05-27 02:10, Claudio Fontana wrote: +case INDEX_op_mov_i64: ext = 1; Please don't put code on the same line as a case statement. Also fall-through cases should have an explicit /* fall through */ comment (except in the case where there is no code at all between one case statement

Re: [Qemu-devel] [PATCH 2/4] tcg/aarch64: implement new TCG target for aarch64

2013-05-27 Thread Richard Henderson
On 2013-05-27 04:43, Claudio Fontana wrote: Hmm, true. Although I'd been thinking more along the lines of arranging the code such that we'd use movz to set the zero. I think we need to keep treating zero specially if we want to keep the optimization where we don't emit needless MOVK

Re: [Qemu-devel] [PATCH 2/4] tcg/aarch64: implement new TCG target for aarch64

2013-05-28 Thread Richard Henderson
On 05/28/2013 12:17 AM, Claudio Fontana wrote: if (type == TCG_TYPE_I32) { value = (uint32_t)value; ext = 0; } else if (value = 0x) { ext = 0; } else { ext = 0x8000; } The check for type is probably unnecessary, since we

Re: [Qemu-devel] [PATCH v4 00/12] target-i386: remove some macros

2013-05-28 Thread Richard Henderson
On 05/28/2013 01:19 AM, li guang wrote: remove macros EAX, EBX, ECX, EDX, EBP, ESP, ESI, EDI, EIP, DF as suggested by Richard Henderson r...@twiddle.net v4: fix alignment issue in patch 6. Li Guang (12) target-i386/helper: remove EAX macro target-i386/helper: remove EBX

Re: [Qemu-devel] [PATCH v3 2/3] tcg/aarch64: implement new TCG target for aarch64

2013-05-28 Thread Richard Henderson
On 05/28/2013 08:28 AM, Claudio Fontana wrote: +static inline void tcg_out_movi_aux(TCGContext *s, +TCGReg rd, uint64_t value) +{ +uint32_t half, base, movk = 0, shift = 0; + +/* construct halfwords of the immediate with MOVZ/MOVK with LSL */ +

Re: [Qemu-devel] [PATCH v4 0/3] ARM aarch64 TCG target

2013-05-29 Thread Richard Henderson
Fontana (3): include/elf.h: add aarch64 ELF machine and relocs tcg/aarch64: implement new TCG target for aarch64 configure: permit compilation on arm aarch64 Reviewed-by: Richard Henderson r...@twiddle.net r~

[Qemu-devel] [PATCH] target-i386: Fix aflag logic for CODE64 and the 0x67 prefix

2013-05-29 Thread Richard Henderson
is undefined. Cc: Paolo Bonzini pbonz...@redhat.com Reported-by: Laszlo Ersek ler...@redhat.com Signed-off-by: Richard Henderson r...@twiddle.net --- target-i386/translate.c | 30 +++--- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/target-i386

[Qemu-devel] [PATCH 1/4] tcg: Split rem requirement from div requirement

2013-05-30 Thread Richard Henderson
There are several hosts with only a div insn. Remainder is computed manually from the quotient and inputs. We can do this generically. Signed-off-by: Richard Henderson r...@twiddle.net --- tcg/arm/tcg-target.h | 2 ++ tcg/hppa/tcg-target.h | 1 + tcg/ia64/tcg-target.h | 2 ++ tcg/mips

[Qemu-devel] [PATCH 2/4] tcg-arm: Don't implement rem

2013-05-30 Thread Richard Henderson
Signed-off-by: Richard Henderson r...@twiddle.net --- tcg/arm/tcg-target.c | 14 -- tcg/arm/tcg-target.h | 3 +-- 2 files changed, 1 insertion(+), 16 deletions(-) diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c index 3d43412..2fecc4d 100644 --- a/tcg/arm/tcg-target.c +++ b

[Qemu-devel] [PATCH 4/4] tcg-ppc64: Don't implement rem

2013-05-30 Thread Richard Henderson
Signed-off-by: Richard Henderson r...@twiddle.net --- tcg/ppc64/tcg-target.c | 26 -- tcg/ppc64/tcg-target.h | 4 ++-- 2 files changed, 2 insertions(+), 28 deletions(-) diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c index 0fcf2b5..ea5f150 100644 --- a/tcg

[Qemu-devel] [PATCH 3/4] tcg-ppc: Don't implement rem

2013-05-30 Thread Richard Henderson
Signed-off-by: Richard Henderson r...@twiddle.net --- tcg/ppc/tcg-target.c | 14 -- tcg/ppc/tcg-target.h | 2 +- 2 files changed, 1 insertion(+), 15 deletions(-) diff --git a/tcg/ppc/tcg-target.c b/tcg/ppc/tcg-target.c index 29ca934..453ab6b 100644 --- a/tcg/ppc/tcg-target.c +++ b

Re: [Qemu-devel] [PATCH] target-i386: Fix aflag logic for CODE64 and the 0x67 prefix

2013-05-31 Thread Richard Henderson
Ping. On 05/29/2013 12:30 PM, Richard Henderson wrote: The code reorganization in commit 4a6fd938 broke handling of PREFIX_ADR. While fixing this, tidy and comment the code so that it's more obvious what's going on in setting both aflag and dflag. The TARGET_X86_64 ifdef can be eliminated

Re: [Qemu-devel] [PATCH 1/4] tcg/aarch64: more low level ops in preparation of tlb, lookup

2013-05-31 Thread Richard Henderson
On 05/31/2013 10:57 AM, Jani Kokkonen wrote: +ARITH_SUBS = 0x6b, Any reason you're adding SUBS here, but not ANDS? +/* encode a logical immediate, mapping user parameter + M=set bits pattern length to S=M-1 */ +static inline unsigned int +aarch64_limm(unsigned int m, unsigned int r)

Re: [Qemu-devel] [PATCH 2/4] tcg/aarch64: implement byte swap operations

2013-05-31 Thread Richard Henderson
On 05/31/2013 11:01 AM, Jani Kokkonen wrote: +static inline void tcg_out_rev(TCGContext *s, int ext, TCGReg rd, TCGReg rm) +{ +/* using REV 0x5ac00800 */ +unsigned int base = ext ? 0xdac00c00 : 0x5ac00800; +tcg_out32(s, base | rm 5 | rd); +} + +static inline void

Re: [Qemu-devel] [PATCH 3/4] tcg/aarch64: implement sign/zero extend operations

2013-05-31 Thread Richard Henderson
On 05/31/2013 11:05 AM, Jani Kokkonen wrote: +static inline void tcg_out_uxt(TCGContext *s, int s_bits, + TCGReg rd, TCGReg rn) +{ +/* using ALIASes UXTB 0x53001c00, UXTH 0x53003c00 + of UBFM Wd, Wn, #0, #7|15 and mov */ +int bits = 8 * (1 s_bits)

Re: [Qemu-devel] [PATCH 4/4] tcg/aarch64: implement tlb lookup fast path

2013-05-31 Thread Richard Henderson
On 05/31/2013 11:07 AM, Jani Kokkonen wrote: +/* Load and compare a TLB entry, leaving the flags set. Leaves X2 pointing + to the tlb entry. Clobbers X0,X1,X2,X3 and TMP. */ + +static void tcg_out_tlb_read(TCGContext *s, TCGReg addr_reg, + int s_bits, uint8_t

Re: [Qemu-devel] [PATCH 01/21] memory: Introduce address_space_lookup_region

2013-05-31 Thread Richard Henderson
...@siemens.com Signed-off-by: Paolo Bonzini pbonz...@redhat.com Reviewed-by: Richard Henderson r...@twiddle.net r~

Re: [Qemu-devel] [PATCH 02/21] memory: move private types to exec.c

2013-05-31 Thread Richard Henderson
On 05/30/2013 02:16 PM, Paolo Bonzini wrote: Signed-off-by: Paolo Bonzini pbonz...@redhat.com --- exec.c | 16 include/exec/memory-internal.h | 15 --- 2 files changed, 16 insertions(+), 15 deletions(-) Reviewed-by: Richard Henderson r

Re: [Qemu-devel] [PATCH 03/21] exec: Allow unaligned address_space_rw

2013-05-31 Thread Richard Henderson
file changed, 6 insertions(+), 6 deletions(-) Reviewed-by: Richard Henderson r...@twiddle.net r~

Re: [Qemu-devel] [PATCH 04/21] exec: Resolve subpages in one step except for IOTLB fills

2013-05-31 Thread Richard Henderson
On 05/30/2013 02:16 PM, Paolo Bonzini wrote: static MemoryRegionSection *address_space_lookup_region(AddressSpace *as, -hwaddr addr) +hwaddr addr, +

Re: [Qemu-devel] [PATCH 05/21] exec: Implement subpage_read/write via address_space_rw

2013-05-31 Thread Richard Henderson
+ 1 file changed, 47 insertions(+), 78 deletions(-) I take it this is the subsequent patch that I queried from 4/. In which case both can have Reviewed-by: Richard Henderson r...@twiddle.net r~

Re: [Qemu-devel] [PATCH 07/21] Revert memory: limit sections in the radix tree to the actual address space size

2013-05-31 Thread Richard Henderson
On 05/30/2013 02:16 PM, Paolo Bonzini wrote: This reverts commit 86a8623692b1b559a419a92eb8b6897c221bca74. Signed-off-by: Paolo Bonzini pbonz...@redhat.com --- exec.c| 13 + include/exec/memory.h | 3 --- 2 files changed, 1 insertion(+), 15 deletions(-) I

Re: [Qemu-devel] [PATCH 06/21] exec: return MemoryRegion from address_space_translate

2013-05-31 Thread Richard Henderson
+- include/exec/memory.h | 8 +-- 2 files changed, 79 insertions(+), 79 deletions(-) Reviewed-by: Richard Henderson r...@twiddle.net r~

Re: [Qemu-devel] [PATCH 10/21] memory: make section size a 128-bit integer

2013-05-31 Thread Richard Henderson
On 05/30/2013 02:16 PM, Paolo Bonzini wrote: +static inline Int128 int128_rshift(Int128 a, int n) +{ +return (Int128) { (a.lo n) | (a.hi (64 - n)), (a.hi n) }; +} Produces wrong results for n == 0, since (a.hi 64) is undefined. r~

Re: [Qemu-devel] [PATCH 09/21] exec: reorganize mem_add to match Int128 version

2013-05-31 Thread Richard Henderson
--- 1 file changed, 16 insertions(+), 23 deletions(-) Reviewed-by: Richard Henderson r...@twiddle.net r~

Re: [Qemu-devel] [PATCH 11/21] memory: iommu support

2013-05-31 Thread Richard Henderson
(MemoryRegion *mr, + MemoryRegionIOMMUOps *ops, + const char *name, + uint64_t size) +{ Surely the incoming ops pointer should be const too? Otherwise, Reviewed-by: Richard Henderson r...@twiddle.net r~

Re: [Qemu-devel] [PATCH 13/21] vfio: abort if an emulated iommu is used

2013-05-31 Thread Richard Henderson
Signed-off-by: Paolo Bonzini pbonz...@redhat.com --- hw/misc/vfio.c | 2 ++ 1 file changed, 2 insertions(+) Reviewed-by: Richard Henderson r...@twiddle.net r~

Re: [Qemu-devel] [PATCH 12/21] memory: Add iommu map/unmap notifiers

2013-05-31 Thread Richard Henderson
memory.c | 18 ++ 2 files changed, 50 insertions(+) Reviewed-by: Richard Henderson r...@twiddle.net r~

Re: [Qemu-devel] [PATCH 0/4] aarch64 TCG tlb fast lookup prerequisites

2013-06-03 Thread Richard Henderson
+-- tcg/aarch64/tcg-target.h | 30 - 2 files changed, 166 insertions(+), 34 deletions(-) Reviewed-by: Richard Henderson r...@twiddle.net r~

Re: [Qemu-devel] Could configure generate QEMU's linker scripts?

2013-06-03 Thread Richard Henderson
On 06/02/2013 10:15 AM, Peter Maydell wrote: So for a new architecture how do we determine whether we need to fiddle with the start address or not? (More specifically, is aarch64 going to need a linker script or just to go in the configure list of hosts which don't need one ?) Basically, for

Re: [Qemu-devel] [PATCH 1/4] tcg-ppc64: Fix RLDCL opcode

2013-06-03 Thread Richard Henderson
On 06/02/2013 05:27 AM, Anton Blanchard wrote: The rldcl instruction doesn't have an sh field, so the minor opcode of 8 is actually 4 when using the XO30 macro. Cc: qemu-sta...@nongnu.org Signed-off-by: Anton Blanchard an...@samba.org --- Index: b/tcg/ppc64/tcg-target.c

Re: [Qemu-devel] [PATCH 2/4] tcg-ppc64: bswap64 rotates output 32 bits

2013-06-03 Thread Richard Henderson
On 06/02/2013 05:28 AM, Anton Blanchard wrote: If our input and output is in the same register, bswap64 tries to undo a rotate of the input. This just ends up rotating the output. Cc: qemu-sta...@nongnu.org Signed-off-by: Anton Blanchard an...@samba.org Reviewed-by: Richard Henderson r

Re: [Qemu-devel] [PATCH 3/4] tcg-ppc64: Fix add2_i64

2013-06-03 Thread Richard Henderson
an...@samba.org Reviewed-by: Richard Henderson r...@twiddle.net r~

Re: [Qemu-devel] [PATCH 4/4] tcg-ppc64: rotr_i32 rotates wrong amount

2013-06-03 Thread Richard Henderson
On 06/02/2013 05:30 AM, Anton Blanchard wrote: rotr_i32 calculates the amount to left shift and puts it into a temporary, but then doesn't use it when doing the shift. Cc: qemu-sta...@nongnu.org Signed-off-by: Anton Blanchard an...@samba.org --- Reviewed-by: Richard Henderson r

Re: [Qemu-devel] Could configure generate QEMU's linker scripts?

2013-06-03 Thread Richard Henderson
On 06/03/2013 07:57 AM, Peter Maydell wrote: Well, the output of ld --verbose says: PROVIDE (__executable_start = SEGMENT_START(text-segment, 0x40)); . = SEGMENT_START(text-segment, 0x40) + SIZEOF_HEADERS; and objdump of a random aarch64 binary suggests the text segment

Re: [Qemu-devel] [PATCH 0/2] linux-user: Drop direct use of openat etc syscalls

2013-06-03 Thread Richard Henderson
is too old. uClibc provides these functions.] Peter Maydell (2): linux-user: Drop direct use of openat etc syscalls configure: Drop CONFIG_ATFILE test Reviewed-by: Richard Henderson r...@twiddle.net r~

Re: [Qemu-devel] [PATCH] linux-user: Allow getdents to be provided by getdents64

2013-06-03 Thread Richard Henderson
On 06/02/2013 10:10 AM, Peter Maydell wrote: +tde-d_ino = tswapal(ino); +tde-d_off = tswapal(off); +tde-d_reclen = tswap16(treclen); +memmove(tde-d_name, de-d_name, namelen + 1); Wouldn't it be better to do the

Re: [Qemu-devel] [PATCH] linux-user: Allow getdents to be provided by getdents64

2013-06-03 Thread Richard Henderson
On 06/03/2013 08:45 AM, Peter Maydell wrote: +/* The target_dirent type is in what was formerly a padding + * byte at the end of the structure: + */ +*(((char *)tde) + treclen - 1) = type; Maybe easier

Re: [Qemu-devel] [PATCH 4/4] tcg/aarch64: implement tlb lookup fast path

2013-06-03 Thread Richard Henderson
On 06/03/2013 04:21 AM, Jani Kokkonen wrote: @ merge the tlb index into the env+tlb_offset add x1, x1, x0, lsl #3 For the record, oops. 3 should be CPU_TLB_ENTRY_BITS. r~

Re: [Qemu-devel] [PATCH v2] linux-user: Allow getdents to be provided by getdents64

2013-06-04 Thread Richard Henderson
...@linaro.org Message-id: 1370193044-24535-1-git-send-email-peter.mayd...@linaro.org --- Changes v1-v2: * memmove() call moved to before we write inode/offset/reclen * wrapped a stray long line that snuck in somehow Reviewed-by: Richard Henderson r...@twiddle.net r~

Re: [Qemu-devel] Could configure generate QEMU's linker scripts?

2013-06-04 Thread Richard Henderson
On 06/04/2013 09:13 AM, Peter Maydell wrote: Since we now default to reserve 4GB space and set guest-base this should work OK (if all the TCG bits are right). Indeed it should. Which reminds me... we should remove the bits that make guest-base optional, now that all TCG backends support it.

[Qemu-devel] [PATCH 2/2] tcg: Remove redundant tcg_target_init checks

2013-06-04 Thread Richard Henderson
We've got a compile-time check for the condition in exec/cpu-defs.h. Signed-off-by: Richard Henderson r...@twiddle.net --- tcg/arm/tcg-target.c | 6 -- tcg/i386/tcg-target.c | 6 -- tcg/s390/tcg-target.c | 7 --- 3 files changed, 19 deletions(-) diff --git a/tcg/arm/tcg-target.c b

[Qemu-devel] [PATCH 0/2] tcg: Remove redundant tcg_target_init checks

2013-06-04 Thread Richard Henderson
Reviewing the tcg/aarch64 patch set, and comparing that to existing hosts made me remember that I've wanted to do this for quite some time. r~ Richard Henderson (2): tcg: Use QEMU_BUILD_BUG_ON for CPU_TLB_ENTRY_BITS tcg: Remove redundant tcg_target_init checks include/exec/cpu-defs.h

[Qemu-devel] [PATCH 1/2] tcg: Use QEMU_BUILD_BUG_ON for CPU_TLB_ENTRY_BITS

2013-06-04 Thread Richard Henderson
Rather than a hand-coded version of the same thing. Signed-off-by: Richard Henderson r...@twiddle.net --- include/exec/cpu-defs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index d8c64e9..2e5a9ba 100644 --- a/include/exec

Re: [Qemu-devel] [PATCH 1/2] tcg-arm: Implement tcg_register_jit

2013-06-04 Thread Richard Henderson
Ping. r~ On 05/24/2013 02:20 PM, Richard Henderson wrote: Allows unwinding past the code_gen_buffer. Signed-off-by: Richard Henderson r...@twiddle.net --- tcg/arm/tcg-target.c | 91 ++-- 1 file changed, 82 insertions(+), 9 deletions

Re: [Qemu-devel] [PATCH 1/2] tcg-arm: Implement tcg_register_jit

2013-06-05 Thread Richard Henderson
On 06/04/2013 06:56 PM, li guang wrote: +typedef struct { +uint32_t len __attribute__((aligned((sizeof(void *); +uint32_t cie_offset; +tcg_target_long func_start __attribute__((packed)); +tcg_target_long func_len __attribute__((packed)); suspicious usage of packed

Re: [Qemu-devel] [PATCH 1/2] tcg-arm: Implement tcg_register_jit

2013-06-05 Thread Richard Henderson
On 06/05/2013 06:02 AM, Andreas Färber wrote: So why can't you apply QEMU_PACKED to the whole struct? Because of the contradicting void* alignment attribute of the first field? Actually, that might work. I'll give it a shot on x86_64 and change all of the uses if it does work. r~

[Qemu-devel] [PULL 0/2] tcg: Remove redundant tcg_target_init checks

2013-06-05 Thread Richard Henderson
:54:40 -0700) Richard Henderson (2): tcg: Use QEMU_BUILD_BUG_ON for CPU_TLB_ENTRY_BITS tcg: Remove redundant tcg_target_init checks include/exec/cpu-defs.h | 2 +- tcg/arm/tcg-target.c| 6 -- tcg/i386/tcg

[Qemu-devel] [PULL 2/2] tcg: Remove redundant tcg_target_init checks

2013-06-05 Thread Richard Henderson
We've got a compile-time check for the condition in exec/cpu-defs.h. Reviewed-by: Andreas Färber afaer...@suse.de Reviewed-by: liguang lig.f...@cn.fujitsu.com Signed-off-by: Richard Henderson r...@twiddle.net --- tcg/arm/tcg-target.c | 6 -- tcg/i386/tcg-target.c | 6 -- tcg/s390/tcg

[Qemu-devel] [PULL 1/2] tcg: Use QEMU_BUILD_BUG_ON for CPU_TLB_ENTRY_BITS

2013-06-05 Thread Richard Henderson
Rather than a hand-coded version of the same thing. Reviewed-by: Andreas Färber afaer...@suse.de Reviewed-by: liguang lig.f...@cn.fujitsu.com Signed-off-by: Richard Henderson r...@twiddle.net --- include/exec/cpu-defs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include

Re: [Qemu-devel] [PATCH 1/2] tcg-arm: Implement tcg_register_jit

2013-06-05 Thread Richard Henderson
On 06/05/2013 06:10 AM, Peter Maydell wrote: This isn't a big deal except for structs where we care about atomicity, though, which I don't think is the case here. Indeed not. This is just more dwarf debug info for gdb's use. r~

Re: [Qemu-devel] [PATCH 0/2] AArch64 TCG User Mode

2013-06-05 Thread Richard Henderson
| 2 +- tcg/aarch64/tcg-target.c | 121 +-- user-exec.c | 15 ++ 3 files changed, 132 insertions(+), 6 deletions(-) Reviewed-by: Richard Henderson r...@twiddle.net r~

[Qemu-devel] [PATCH v2 2/4] tcg: Move the CIE and FDE header definitions to common code

2013-06-05 Thread Richard Henderson
These will necessarily be the same layout for all hosts. This limits the amount of boilerplate required to implement jit debug for a host. Signed-off-by: Richard Henderson r...@twiddle.net --- tcg/hppa/tcg-target.c | 35 ++- tcg/i386/tcg-target.c | 39

[Qemu-devel] [PATCH v2 1/4] tcg: Fix high_pc fields in .debug_info

2013-06-05 Thread Richard Henderson
I don't think the debugger actually looks at this for anything, using the correct .debug_frame contents, but might as well get it all correct. Signed-off-by: Richard Henderson r...@twiddle.net --- tcg/tcg.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tcg/tcg.c b/tcg

[Qemu-devel] [PATCH v2 3/4] tcg-i386: Use QEMU_BUILD_BUG_ON instead of assert for frame size

2013-06-05 Thread Richard Henderson
We can check the condition at compile time, rather than run time. Signed-off-by: Richard Henderson r...@twiddle.net --- tcg/i386/tcg-target.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/tcg/i386/tcg-target.c b/tcg/i386/tcg-target.c index 7d946eb..991f484 100644

[Qemu-devel] [PATCH v2 0/4] tcg-arm: Implement tcg_register_jit

2013-06-05 Thread Richard Henderson
Changes v1-v2: The suggestions for improvement I got from round 1 apply to all of the hosts, not just arm. r~ Richard Henderson (4): tcg: Fix high_pc fields in .debug_info tcg: Move the CIE and FDE header definitions to common code tcg-i386: Use QEMU_BUILD_BUG_ON instead of assert

[Qemu-devel] [PATCH v2 4/4] tcg-arm: Implement tcg_register_jit

2013-06-05 Thread Richard Henderson
Allows unwinding past the code_gen_buffer. Signed-off-by: Richard Henderson r...@twiddle.net --- tcg/arm/tcg-target.c | 76 +--- 1 file changed, 67 insertions(+), 9 deletions(-) diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c index

Re: [Qemu-devel] [PATCH 1/2] tcg-arm: Implement tcg_register_jit

2013-06-06 Thread Richard Henderson
On 06/05/2013 05:28 PM, li guang wrote: 在 2013-06-05三的 05:49 -0700,Richard Henderson写道: On 06/04/2013 06:56 PM, li guang wrote: +typedef struct { +uint32_t len __attribute__((aligned((sizeof(void *); +uint32_t cie_offset; +tcg_target_long func_start __attribute__((packed

[Qemu-devel] [PATCH 1/5] tcg: Allow non-constant control macros

2013-06-06 Thread Richard Henderson
This allows TCG_TARGET_HAS_* to be a variable rather than a constant, which allows easier support for differing ISA levels for the host. Signed-off-by: Richard Henderson r...@twiddle.net --- tcg/tcg-opc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tcg/tcg-opc.h b/tcg/tcg

[Qemu-devel] [PATCH 0/5] tcg-arm: Runtime detection of architecture

2013-06-06 Thread Richard Henderson
. Perhaps more valuable is being able to generate armv7 insns when running on e.g. an cortex-a15, even when the OS distribution is built for a more generic armv5. Tested on an a15, and with various hacks to force each of the unused code paths to be used. r~ Richard Henderson (5): tcg: Allow non

[Qemu-devel] [PATCH 2/5] tcg: Simplify logic using TCG_OPF_NOT_PRESENT

2013-06-06 Thread Richard Henderson
Expand the definition of not present to include should not be present. This means we can simplify the logic surrounding the generic tcg opcodes for which the host backend ought not be providing definitions. Signed-off-by: Richard Henderson r...@twiddle.net --- tcg/tcg-opc.h | 26

[Qemu-devel] [PATCH 4/5] tcg-arm: Simplify logic in detecting the ARM ISA in use

2013-06-06 Thread Richard Henderson
GCC 4.8 defines a handy __ARM_ARCH symbol that we can use, which will make us nicely forward compatible with ARMv8 AArch32. Signed-off-by: Richard Henderson r...@twiddle.net --- tcg/arm/tcg-target.c | 62 +--- 1 file changed, 20 insertions(+), 42

[Qemu-devel] [PATCH 5/5] tcg-arm: Use AT_PLATFORM to detect the host ISA

2013-06-06 Thread Richard Henderson
With this we can generate armv7 insns even when the OS compiles for a lower common denominator. The macros are arranged so that when we do compile for a given ISA, all of the runtime checks for that ISA are optimized away. Signed-off-by: Richard Henderson r...@twiddle.net --- tcg/arm/tcg

[Qemu-devel] [PATCH 3/5] tcg-arm: Make use of conditional availability of opcodes for divide

2013-06-06 Thread Richard Henderson
We can now detect and use divide instructions at runtime, rather than having to restrict their availability to compile-time. Signed-off-by: Richard Henderson r...@twiddle.net --- tcg/arm/tcg-target.c | 16 ++-- tcg/arm/tcg-target.h | 14 -- 2 files changed, 22 insertions

Re: [Qemu-devel] [PATCH 1/4] tcg: Split rem requirement from div requirement

2013-06-10 Thread Richard Henderson
Ping. On 05/30/2013 10:53 AM, Richard Henderson wrote: There are several hosts with only a div insn. Remainder is computed manually from the quotient and inputs. We can do this generically. Signed-off-by: Richard Henderson r...@twiddle.net --- tcg/arm/tcg-target.h | 2 ++ tcg/hppa

Re: [Qemu-devel] [PULL 0/2] tcg: Remove redundant tcg_target_init checks

2013-06-10 Thread Richard Henderson
Ping. On 06/05/2013 05:59 AM, Richard Henderson wrote: Reviewing the tcg/aarch64 patch set, and comparing that to existing hosts made me remember that I've wanted to do this for quite some time. Now with two reviews, please pull. r~ The following changes since commit

Re: [Qemu-devel] [PATCH 0/5] tcg-arm: Runtime detection of architecture

2013-06-10 Thread Richard Henderson
Ping. On 06/06/2013 11:05 AM, Richard Henderson wrote: Two prepatory generic tcg patches, to allow non-constant values for the various TCG_TARGET_HAS_foo macros. When in patch 3 this gets used, the code inlined in the translators will be able to check the relevant variable and emit either

Re: [Qemu-devel] [PATCH v2 0/4] tcg-arm: Implement tcg_register_jit

2013-06-10 Thread Richard Henderson
Ping. On 06/05/2013 10:29 AM, Richard Henderson wrote: Changes v1-v2: The suggestions for improvement I got from round 1 apply to all of the hosts, not just arm. r~ Richard Henderson (4): tcg: Fix high_pc fields in .debug_info tcg: Move the CIE and FDE header definitions

Re: [Qemu-devel] [PATCH 1/4] tcg-ppc64: Fix RLDCL opcode

2013-06-11 Thread Richard Henderson
: qemu-sta...@nongnu.org Signed-off-by: Anton Blanchard an...@samba.org Reviewed-by: Richard Henderson r...@twiddle.net r~

Re: [Qemu-devel] [PATCH 1/1] tcg/aarch64: implement ldst 12bit scaled uimm offset

2013-06-11 Thread Richard Henderson
/tcg-target.c | 32 +--- 1 file changed, 29 insertions(+), 3 deletions(-) Reviewed-by: Richard Henderson r...@twiddle.net r~

Re: [Qemu-devel] [PATCH 01/10] target-s390: Move facilities bits to env

2013-09-30 Thread Richard Henderson
On 09/30/2013 11:03 AM, Alexander Graf wrote: On 09/23/2013 04:04 PM, Richard Henderson wrote: Rather than simply hard-coding them in STFL instruction. Signed-off-by: Richard Hendersonr...@twiddle.net --- target-s390x/cpu.c | 3 +++ target-s390x/cpu.h | 1 + target-s390x

Re: [Qemu-devel] [PATCH 07/10] target-s390: Fix STIDP

2013-09-30 Thread Richard Henderson
On 09/30/2013 11:13 AM, Alexander Graf wrote: -int cpu_num; +union { +uint64_t cpuid; +struct { +#ifdef HOST_WORDS_BIGENDIAN +uint32_t cpu_num; +uint32_t machine_type; +#else +uint32_t machine_type; +uint32_t

Re: [Qemu-devel] [PATCH 3/4] Refactoring MonitorDef array

2013-09-30 Thread Richard Henderson
On 09/30/2013 08:57 AM, Fabien Chouteau wrote: +extern const MonitorDef arch_monitor_defs[]; This is supplied by target-foo/monitor.c, right? Why in the world is it declared in generic code? Especially if it's only ever accessed via the cpu-monitor_defs member? r~

Re: [Qemu-devel] [PATCH 3/4] Refactoring MonitorDef array

2013-10-01 Thread Richard Henderson
On 10/01/2013 07:28 AM, Fabien Chouteau wrote: On 10/01/2013 04:00 AM, Richard Henderson wrote: On 09/30/2013 08:57 AM, Fabien Chouteau wrote: +extern const MonitorDef arch_monitor_defs[]; This is supplied by target-foo/monitor.c, right? Why in the world is it declared in generic code

Re: [Qemu-devel] [PATCH 01/10] target-s390: Move facilities bits to env

2013-10-01 Thread Richard Henderson
On 10/01/2013 08:48 AM, Alexander Graf wrote: On 09/30/2013 09:15 PM, Richard Henderson wrote: On 09/30/2013 11:03 AM, Alexander Graf wrote: On 09/23/2013 04:04 PM, Richard Henderson wrote: Rather than simply hard-coding them in STFL instruction. Signed-off-by: Richard Hendersonr

Re: [Qemu-devel] [PATCH 07/10] target-s390: Fix STIDP

2013-10-01 Thread Richard Henderson
On 10/01/2013 08:52 AM, Alexander Graf wrote: On 09/30/2013 09:48 PM, Richard Henderson wrote: On 09/30/2013 11:13 AM, Alexander Graf wrote: -int cpu_num; +union { +uint64_t cpuid; +struct { +#ifdef HOST_WORDS_BIGENDIAN +uint32_t cpu_num

Re: [Qemu-devel] [PATCH 01/10] target-s390: Move facilities bits to env

2013-10-01 Thread Richard Henderson
On 10/01/2013 08:54 AM, Alexander Graf wrote: Just make sure you actually check for feature bits on every instruction (which I think you do, but the current code is way too magical to me to really understand it anymore) so that we can always implement a z900 cpu type later on. Yes, the code

[Qemu-devel] [PATCH v2 0/9] target-s390 tcg improvements

2013-10-01 Thread Richard Henderson
implementations adjusted for feedback. * Minor tweaks to SAM implementations. * Split out z9-109 hack to a separate patch. r~ Richard Henderson (9): target-s390: Add facilities data to env target-s390: Implement STFLE target-s390: Implement SAM31 and SAM64 target-s390: Implement EPSW target

[Qemu-devel] [PATCH v2 2/9] target-s390: Implement STFLE

2013-10-01 Thread Richard Henderson
Signed-off-by: Richard Henderson r...@twiddle.net --- target-s390x/helper.h | 1 + target-s390x/insn-data.def | 2 ++ target-s390x/misc_helper.c | 13 + target-s390x/translate.c | 8 4 files changed, 24 insertions(+) diff --git a/target-s390x/helper.h b/target

[Qemu-devel] [PATCH v2 1/9] target-s390: Add facilities data to env

2013-10-01 Thread Richard Henderson
Name the facilities bits, collect the set of bits for tcg and the various real processor revisions. Update the set of facilities reported for TCG. Validate the insns we execute against the facilities enabled. Report the correct facilities via STFL. Signed-off-by: Richard Henderson r

[Qemu-devel] [PATCH v2 3/9] target-s390: Implement SAM31 and SAM64

2013-10-01 Thread Richard Henderson
Signed-off-by: Richard Henderson r...@twiddle.net --- target-s390x/insn-data.def | 8 target-s390x/translate.c | 26 ++ 2 files changed, 30 insertions(+), 4 deletions(-) diff --git a/target-s390x/insn-data.def b/target-s390x/insn-data.def index 4b462d4

[Qemu-devel] [PATCH v2 5/9] target-s390: Fix STIDP

2013-10-01 Thread Richard Henderson
The implementation had been incomplete, as we did not store the machine type. Note that the machine_type member is still unset during initialization, so this has no effect yet. Signed-off-by: Richard Henderson r...@twiddle.net --- target-s390x/cpu.h | 4 +++- target-s390x/translate.c | 6

[Qemu-devel] [PATCH v2 6/9] target-s390: Fix STURA

2013-10-01 Thread Richard Henderson
We were storing 16 bits instead of 32. Signed-off-by: Richard Henderson r...@twiddle.net --- target-s390x/mem_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target-s390x/mem_helper.c b/target-s390x/mem_helper.c index 1422ae9..408836c 100644 --- a/target-s390x

[Qemu-devel] [PATCH v2 4/9] target-s390: Implement EPSW

2013-10-01 Thread Richard Henderson
Signed-off-by: Richard Henderson r...@twiddle.net --- target-s390x/insn-data.def | 2 ++ target-s390x/translate.c | 18 ++ 2 files changed, 20 insertions(+) diff --git a/target-s390x/insn-data.def b/target-s390x/insn-data.def index c528eb4..48850ff 100644 --- a/target-s390x

[Qemu-devel] [PATCH v2 8/9] target-s390: Implement ECAG

2013-10-01 Thread Richard Henderson
Signed-off-by: Richard Henderson r...@twiddle.net --- target-s390x/insn-data.def | 2 ++ target-s390x/translate.c | 7 +++ 2 files changed, 9 insertions(+) diff --git a/target-s390x/insn-data.def b/target-s390x/insn-data.def index a405f64..d3bc5b1 100644 --- a/target-s390x/insn-data.def

[Qemu-devel] [PATCH v2 7/9] target-s390: Implement LURA, LURAG, STURG

2013-10-01 Thread Richard Henderson
Signed-off-by: Richard Henderson r...@twiddle.net --- target-s390x/helper.h | 3 +++ target-s390x/insn-data.def | 4 target-s390x/mem_helper.c | 16 target-s390x/translate.c | 26 ++ 4 files changed, 49 insertions(+) diff --git a/target

[Qemu-devel] [PATCH v2 9/9] target-s390: Force TCG to report Z9-109

2013-10-01 Thread Richard Henderson
Fedora 19 targets Z9-109 as the minimum supported cpu, and the kernel will exit very early in the boot process if facilities do not match. This is a hack until we properly implement distinct qom cpu types. Signed-off-by: Richard Henderson r...@twiddle.net --- target-s390x/cpu.c | 10

  1   2   3   4   5   6   7   8   9   10   >