Re: [Qemu-devel] [RFC PATCH 07/17] target/ppc/POWER9: Add partition table pointer to sPAPRMachineState

On Wed, 2017-02-01 at 15:04 +1100, David Gibson wrote: > On Fri, Jan 13, 2017 at 05:28:13PM +1100, Suraj Jitindar Singh wrote: > > > > POWER9 uses a partition table to store information relating to how > > address translation is performed on a per partition basis. >

Re: [Qemu-devel] [RFC PATCH 00/17] target/ppc: Implement POWER9 pseries tcg legacy kernel support

On Wed, 2017-02-01 at 12:04 +1100, David Gibson wrote: > On Thu, Jan 12, 2017 at 10:55:49PM -0800, no-re...@patchew.org wrote: > > > > Hi, > > > > Your series seems to have some coding style problems. See output > > below for > > more information: > > > > Message-id:

Re: [Qemu-devel] [RFC PATCH 10/17] target/ppc/POWER9: Add POWER9 mmu fault handler

On Wed, 2017-02-01 at 15:23 +1100, David Gibson wrote: > On Fri, Jan 13, 2017 at 05:28:16PM +1100, Suraj Jitindar Singh wrote: > > > > Add a new mmu fault handler for the POWER9 cpu and add it as the > > handler > > for the POWER9 cpu definition. > > > > Th

Re: [Qemu-devel] [RFC PATCH 11/17] target/ppc/POWER9: Update to new pte format for POWER9 accesses

On Wed, 2017-02-01 at 15:28 +1100, David Gibson wrote: > On Fri, Jan 13, 2017 at 05:28:17PM +1100, Suraj Jitindar Singh wrote: > > > > The page table entry format was updated for the POWER9 processor. > > > > It was decided that kernels would used

Re: [Qemu-devel] [RFC PATCH 08/17] target/ppc/POWER9: Add external partition table pointer to cpu state

On Wed, 2017-02-01 at 15:09 +1100, David Gibson wrote: > On Fri, Jan 13, 2017 at 05:28:14PM +1100, Suraj Jitindar Singh wrote: > > > > Similarly to how we have an external hpt pointer in the cpu state, > > add > > an external partition table pointer and update it to

Re: [Qemu-devel] [RFC PATCH 09/17] target/ppc/POWER9: Remove SDR1 register

On Wed, 2017-02-01 at 15:16 +1100, David Gibson wrote: > On Fri, Jan 13, 2017 at 05:28:15PM +1100, Suraj Jitindar Singh wrote: > > > > The SDR1 registers was used to store the location of the hash page > > table. > > > > This register no longer exists on POWER

Re: [Qemu-devel] [RFC PATCH 04/17] target/ppc/POWER9: Add ISAv3.00 MMU definition

On Tue, 2017-01-17 at 11:33 +1100, Suraj Jitindar Singh wrote: > On Tue, 2017-01-17 at 08:36 +1100, David Gibson wrote: > > > > On Fri, Jan 13, 2017 at 05:28:10PM +1100, Suraj Jitindar Singh > > wrote: > > > > > > > > > POWER9 process

Re: [Qemu-devel] [RFC PATCH 05/17] target/ppc/POWER9: Adapt LPCR handling for POWER9

On Tue, 2017-01-17 at 15:37 +1100, David Gibson wrote: > On Tue, Jan 17, 2017 at 11:48:31AM +1100, Suraj Jitindar Singh wrote: > > > > On Tue, 2017-01-17 at 08:40 +1100, David Gibson wrote: > > > > > > On Fri, Jan 13, 2017 at 05:28:11PM +1100,

[Qemu-devel] [QEMU-PPC] [PATCH V3 02/10] target/ppc: Fix LPCR DPFD mask define

The DPFD field in the LPCR is 3 bits wide. This has always been defined as 0x3 << shift which indicates a 2 bit field, which is incorrect. Correct this. Signed-off-by: Suraj Jitindar Singh <sjitindarsi...@gmail.com> --- target/ppc/cpu.h | 2 +- 1 file changed, 1 insertion(+), 1 delet

[Qemu-devel] [QEMU-PPC] [PATCH V3 00/10] target/ppc: Implement POWER9 pseries tcg legacy support

v3.h - Error report and abort on attempt to use segment tables Suraj Jitindar Singh (10): target/ppc/POWER9: Add ISAv3.00 MMU definition target/ppc: Fix LPCR DPFD mask define target/ppc/POWER9: Adapt LPCR handling for POWER9 target/ppc/POWER9: Direct all instr and data storage interrupts to

[Qemu-devel] [QEMU-PPC] [PATCH V3 01/10] target/ppc/POWER9: Add ISAv3.00 MMU definition

POWER9 processors implement the mmu as defined in version 3.00 of the ISA. Add a definition for this mmu model and set the POWER9 cpu model to use this mmu model. Signed-off-by: Suraj Jitindar Singh <sjitindarsi...@gmail.com> --- target/ppc/cpu-qom.h| 5 - target/ppc/mmu_he

[Qemu-devel] [QEMU-PPC] [PATCH V3 04/10] target/ppc/POWER9: Direct all instr and data storage interrupts to the hypv

Jitindar Singh <sjitindarsi...@gmail.com> Reviewed-by: David Gibson <da...@gibson.dropbear.id.au> --- target/ppc/mmu-hash64.c | 20 ++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index 24d9901..7c

[Qemu-devel] [QEMU-PPC] [PATCH V3 08/10] target/ppc/POWER9: Add POWER9 pa-features definition

Add a pa-features definition which includes all of the new fields which have been added, note we don't claim support for any of these new features at this stage. Signed-off-by: Suraj Jitindar Singh <sjitindarsi...@gmail.com> Reviewed-by: David Gibson <da...@gibson.dropbear.id.au>

[Qemu-devel] [QEMU-PPC] [PATCH V3 05/10] target/ppc: Add patb_entry to sPAPRMachineState

to be migrated as part of the sPAPRMachineState as we will need it on the receiving side as the guest will never tell us this information again and we need it to perform translation. Signed-off-by: Suraj Jitindar Singh <sjitindarsi...@gmail.com> --- V2->V3: - Only add patbe to migration stre

[Qemu-devel] [QEMU-PPC] [PATCH V3 03/10] target/ppc/POWER9: Adapt LPCR handling for POWER9

The logical partitioning control register controls a threads operation based on the partition it is currently executing. Add new definitions and update the mask used when writing to the LPCR based on the POWER9 spec. Signed-off-by: Suraj Jitindar Singh <sjitindarsi...@gmail.com> --- targ

[Qemu-devel] [QEMU-PPC] [PATCH V3 07/10] target/ppc/POWER9: Add POWER9 mmu fault handler

updated to check if the partition is using segment tables. Currently only legacy hash (no segment tables) is supported. Signed-off-by: Suraj Jitindar Singh <sjitindarsi...@gmail.com> --- V2->V3: - error_report on attempt to use segment tables instead of just LOG() - Rename mmu.h -> mmu

[Qemu-devel] [QEMU-PPC] [PATCH V3 10/10] hw/ppc/spapr: Add POWER9 to pseries cpu models

Add POWER9 cpu to list of spapr core models which allows it to be specified as the cpu model for a pseries guest (e.g. -machine pseries -cpu POWER9). This now allows a POWER9 cpu to boot to userspace in tcg emulation for a pseries machine with a legacy kernel. Signed-off-by: Suraj Jitindar Singh

[Qemu-devel] [QEMU-PPC] [PATCH V3 06/10] target/ppc: Don't gen an SDR1 on POWER9 and rework register creation

w cpu models. Signed-off-by: Suraj Jitindar Singh <sjitindarsi...@gmail.com> --- V2->V3: - Add rework of register generation --- target/ppc/mmu-hash64.c | 17 ++- target/ppc/mmu-hash64.h | 4 +- target/ppc/mmu_helper.c | 2 +- target/ppc/translate.c | 7 +-

[Qemu-devel] [QEMU-PPC] [PATCH V3 09/10] target/ppc/POWER9: Add cpu_has_work function for POWER9

-by: Suraj Jitindar Singh <sjitindarsi...@gmail.com> Reviewed-by: David Gibson <da...@gibson.dropbear.id.au> --- target/ppc/translate_init.c | 45 + 1 file changed, 45 insertions(+) diff --git a/target/ppc/translate_init.c b/target/ppc/translate_

Re: [Qemu-devel] [PATCH 1/6] pseries: Minor cleanups to HPT management hypercalls

env = >env; >  target_ulong flags = args[0]; > -target_ulong pte_index = args[1]; > +    target_ulong ptex = args[1]; >  uint8_t *hpte; >  int i, ridx, n_entries = 1; >   > -if (!valid_pte_index(env, pte_index)) { > +if (!valid_ptex(cpu, ptex)) { >  return H_PARAMETER; >  } >   >  if (flags & H_READ_4) { >  /* Clear the two low order bits */ > -pte_index &= ~(3ULL); > +ptex &= ~(3ULL); >  n_entries = 4; >  } >   > -hpte = env->external_htab + (pte_index * HASH_PTE_SIZE_64); > +hpte = env->external_htab + (ptex * HASH_PTE_SIZE_64); >   >  for (i = 0, ridx = 0; i < n_entries; i++) { >  args[ridx++] = ldq_p(hpte); I wholeheartedly agree with this rename. Reviewed-by: Suraj Jitindar Singh <sjitindarsi...@gmail.com>

Re: [Qemu-devel] [QEMU-PPC] [PATCH V3 05/10] target/ppc: Add patb_entry to sPAPRMachineState

On Thu, 2017-02-23 at 14:50 +1100, David Gibson wrote: > On Mon, Feb 20, 2017 at 03:04:33PM +1100, Suraj Jitindar Singh wrote: > > > > ISA v3.00 adds the idea of a partition table which is used to store > > the > > address translation details for all partitions on th

Re: [Qemu-devel] [PATCH 3/6] target/ppc: SDR1 is a hypervisor resource

_read_generic, _write_sdr1, > +0x); > +} else { > +    spr_register(env, SPR_SDR1, "SDR1", > + SPR_NOACCESS, SPR_NOACCESS, > + _read_generic, _write_sdr1, > + 0x); > +} > +#endif >  } >   >  /* BATs 0-3 */ Reviewed-by: Suraj Jitindar Singh <sjitindarsi...@gmail.com>

Re: [Qemu-devel] [Qemu-ppc] [QEMU-PPC] [PATCH V3 01/10] target/ppc/POWER9: Add ISAv3.00 MMU definition

On Thu, 2017-02-23 at 14:43 +1100, David Gibson wrote: > On Mon, Feb 20, 2017 at 04:16:26PM +1100, Balbir Singh wrote: > > > > On Mon, Feb 20, 2017 at 03:04:29PM +1100, Suraj Jitindar Singh > > wrote: > > > > > > POWER9 processors implement the mmu as d

Re: [Qemu-devel] [Qemu-ppc] [QEMU-PPC] [PATCH V3 03/10] target/ppc/POWER9: Adapt LPCR handling for POWER9

On Thu, 2017-02-23 at 14:47 +1100, David Gibson wrote: > On Mon, Feb 20, 2017 at 06:31:46PM +1100, Balbir Singh wrote: > > > > On Mon, Feb 20, 2017 at 03:04:31PM +1100, Suraj Jitindar Singh > > wrote: > > > > > > The logical partitioning control regi

Re: [Qemu-devel] [QEMU-PPC] [PATCH V3 07/10] target/ppc/POWER9: Add POWER9 mmu fault handler

On Thu, 2017-02-23 at 15:08 +1100, David Gibson wrote: > On Mon, Feb 20, 2017 at 03:04:35PM +1100, Suraj Jitindar Singh wrote: > > > > Add a new mmu fault handler for the POWER9 cpu and add it as the > > handler > > for the POWER9 cpu definition. > > > > Th

Re: [Qemu-devel] [PATCH 2/6] target/ppc: Merge cpu_ppc_set_vhyp() with cpu_ppc_set_papr()

; -{ > -cpu->vhyp = vhyp; > -} > - > -void cpu_ppc_set_papr(PowerPCCPU *cpu) > +void cpu_ppc_set_papr(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp) >  { >  CPUPPCState *env = >env; >  ppc_spr_t *lpcr = >spr_cb[SPR_LPCR]; >  ppc_spr_t *amor = >

Re: [Qemu-devel] [PATCH 4/6] target/ppc: Cleanup HPTE accessors for 64-bit hash MMU

need that at the > bottom > layer, but nowhere else). > > Signed-off-by: David Gibson <da...@gibson.dropbear.id.au> Other than the commit message: Reviewed-by: Suraj Jitindar Singh <sjitindarsi...@gmail.com> > --- >  hw/ppc/spapr_hcall.c| 36

Re: [Qemu-devel] [PATCH 5/6] target/ppc: Eliminate htab_base and htab_mask variables

On Thu, 2017-02-23 at 13:09 +1100, David Gibson wrote: > CPUPPCState includes fields htab_base and htab_mask which store the > base > address (GPA) and size (as a mask) of the guest's hashed page table > (HPT). > These are set when the SDR1 register is updated. > > Keeping these in sync with the

Re: [Qemu-devel] [PATCH 6/6] target/ppc: Manage external HPT via virtual hypervisor

> > To match this, the pseries machine now sets these vhyp fields in its > existing vhyp class, rather than reaching into the cpu object to set > the > external_htab field. > > Signed-off-by: David Gibson <da...@gibson.dropbear.id.au> Reviewed-by: Suraj Jitindar Singh <s

Re: [Qemu-devel] [RFC PATCH 11/17] target/ppc/POWER9: Update to new pte format for POWER9 accesses

On Thu, 2017-02-09 at 14:08 +1100, Suraj Jitindar Singh wrote: > On Wed, 2017-02-01 at 15:28 +1100, David Gibson wrote: > > > > On Fri, Jan 13, 2017 at 05:28:17PM +1100, Suraj Jitindar Singh > > wrote: > > > > > > > > > The page table e

Re: [Qemu-devel] [RFC PATCH 11/17] target/ppc/POWER9: Update to new pte format for POWER9 accesses

On Fri, 2017-02-10 at 11:21 +1100, David Gibson wrote: > On Fri, Feb 10, 2017 at 10:47:15AM +1100, Suraj Jitindar Singh wrote: > > > > On Thu, 2017-02-09 at 14:08 +1100, Suraj Jitindar Singh wrote: > > > > > > On Wed, 2017-02-01 a

[Qemu-devel] [QEMU-PPC] [PATCH V2 08/10] target/ppc/POWER9: Add POWER9 pa-features definition

Add a pa-features definition which includes all of the new fields which have been added, note we don't claim support for any of these new features at this stage. Signed-off-by: Suraj Jitindar Singh <sjitindarsi...@gmail.com> --- hw/ppc/spapr.c | 18 ++ 1 file chang

[Qemu-devel] [QEMU-PPC] [PATCH V2 03/10] target/ppc/POWER9: Adapt LPCR handling for POWER9

The logical partitioning control register controls a threads operation based on the partition it is currently executing. Add new definitions and update the mask used when writing to the LPCR based on the POWER9 spec. Signed-off-by: Suraj Jitindar Singh <sjitindarsi...@gmail.com> --- targ

[Qemu-devel] [QEMU-PPC] [PATCH V2 06/10] target/ppc: Don't use SDR1 when running under a POWER9 cpu model

owernv machine code to restore the sdr1 (and htab_[mask/base]) on incoming migration, note this means that the powernv machine isn't yet supported on a POWER9 cpu model. We also adapt the debug code to only print the SDR1 value if the register has been created. Signed-off-by: Suraj Jitindar

[Qemu-devel] [QEMU-PPC] [PATCH V2 07/10] target/ppc/POWER9: Add POWER9 mmu fault handler

updated to check if the partition is using segment tables. Currently only legacy hash (no segment tables) is supported. Signed-off-by: Suraj Jitindar Singh <sjitindarsi...@gmail.com> --- target/ppc/mmu-hash64.c | 9 target/ppc/mmu.h

[Qemu-devel] [QEMU-PPC] [PATCH V2 10/10] hw/ppc/spapr: Add POWER9 to pseries cpu models

Add POWER9 cpu to list of spapr core models which allows it to be specified as the cpu model for a pseries guest (e.g. -machine pseries -cpu POWER9). This now allows a POWER9 cpu to boot to userspace in tcg emulation for a pseries machine with a legacy kernel. Signed-off-by: Suraj Jitindar Singh

Re: [Qemu-devel] [QEMU-PPC] [PATCH V2 00/10] target/ppc: Implement POWER9 pseries tcg

On Fri, 2017-02-10 at 16:25 +1100, Suraj Jitindar Singh wrote: > This is V2 of the patch series to implement tcg emulation support for > a > POWER9 cpu model for the pseries machine type running a legacy > kernel. > That is a kernel which doesn't use the new radix mmu mode or the n

[Qemu-devel] [QEMU-PPC] [PATCH V2 05/10] target/ppc: Add patb_entry to sPAPRMachineState

to be migrated as part of the sPAPRMachineState as we will need it on the receiving side as the guest will never tell us this information again and we need it to perform translation. Signed-off-by: Suraj Jitindar Singh <sjitindarsi...@gmail.com> --- hw/ppc/spapr.c

[Qemu-devel] [QEMU-PPC] [PATCH V2 09/10] target/ppc/POWER9: Add cpu_has_work function for POWER9

-by: Suraj Jitindar Singh <sjitindarsi...@gmail.com> --- target/ppc/translate_init.c | 45 + 1 file changed, 45 insertions(+) diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c index a3a23d8..cc8ab1f 100644 --- a/targ

[Qemu-devel] [QEMU-PPC] [PATCH V2 02/10] target/ppc: Fix LPCR DPFD mask define

The DPFD field in the LPCR is 3 bits wide. This has always been defined as 0x3 << shift which indicates a 2 bit field, which is incorrect. Correct this. Signed-off-by: Suraj Jitindar Singh <sjitindarsi...@gmail.com> --- target/ppc/cpu.h | 2 +- 1 file changed, 1 insertion(+), 1 delet

[Qemu-devel] [QEMU-PPC] [PATCH V2 00/10] target/ppc: Implement POWER9 pseries tcg

R9 pseries cpu model to the end of the series. Suraj Jitindar Singh (10): target/ppc/POWER9: Add ISAv3.00 MMU definition target/ppc: Fix LPCR DPFD mask define target/ppc/POWER9: Adapt LPCR handling for POWER9 target/ppc/POWER9: Direct all instr and data storage interrupts to the hypv

[Qemu-devel] [QEMU-PPC] [PATCH V2 01/10] target/ppc/POWER9: Add ISAv3.00 MMU definition

POWER9 processors implement the mmu as defined in version 3.00 of the ISA. Add a definition for this mmu model and set the POWER9 cpu model to use this mmu model. Signed-off-by: Suraj Jitindar Singh <sjitindarsi...@gmail.com> --- target/ppc/cpu-qom.h| 5 - target/ppc/mmu_he

[Qemu-devel] [QEMU-PPC] [PATCH V2 04/10] target/ppc/POWER9: Direct all instr and data storage interrupts to the hypv

Jitindar Singh <sjitindarsi...@gmail.com> --- target/ppc/mmu-hash64.c | 20 ++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index 24d9901..7c5d589 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-ha

Re: [Qemu-devel] [QEMU-PPC] [PATCH V2 00/10] target/ppc: Implement POWER9 pseries tcg

On Fri, 2017-02-10 at 16:28 +1100, Suraj Jitindar Singh wrote: > On Fri, 2017-02-10 at 16:25 +1100, Suraj Jitindar Singh wrote: > > > > This is V2 of the patch series to implement tcg emulation support > > for > > a > > POWER9 cpu model for the pseries machine

[Qemu-devel] [Qemu-ppc] [PATCH] target/ppc: Stop parsing pvr list in H_CAS when exact match found

eries: Rewrite CAS PVR compatibility logic") Signed-off-by: Suraj Jitindar Singh <sjitindarsi...@gmail.com> --- hw/ppc/spapr_hcall.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c index 590105a..215c385 100644 --- a/hw/ppc/spapr_hcal

Re: [Qemu-devel] [QEMU-PPC] [PATCH V2 05/10] target/ppc: Add patb_entry to sPAPRMachineState

On Mon, 2017-02-13 at 13:17 +1100, David Gibson wrote: > On Fri, Feb 10, 2017 at 04:25:55PM +1100, Suraj Jitindar Singh wrote: > > > > ISA v3.00 adds the idea of a partition table which is used to store > > the > > address translation details for all partitions on th

Re: [Qemu-devel] [RFC PATCH 04/17] target/ppc/POWER9: Add ISAv3.00 MMU definition

On Tue, 2017-01-17 at 08:36 +1100, David Gibson wrote: > On Fri, Jan 13, 2017 at 05:28:10PM +1100, Suraj Jitindar Singh wrote: > > > > POWER9 processors implement the mmu as defined in version 3.00 of > > the ISA. > > > > Add a definition for this mmu m

Re: [Qemu-devel] [RFC PATCH 05/17] target/ppc/POWER9: Adapt LPCR handling for POWER9

On Tue, 2017-01-17 at 08:40 +1100, David Gibson wrote: > On Fri, Jan 13, 2017 at 05:28:11PM +1100, Suraj Jitindar Singh wrote: > > > > The logical partitioning control register controls a threads > > operation > > based on the partition it is currently executi

Re: [Qemu-devel] [RFC PATCH v2 06/12] spapr: Add ibm, processor-radix-AP-encodings to the device tree

On Tue, 2017-02-28 at 11:12 +1100, David Gibson wrote: > On Thu, Feb 23, 2017 at 04:59:59PM +1100, Sam Bobroff wrote: > > > > Use the new ioctl, KVM_PPC_GET_RMMU_INFO, to fetch radix MMU > > information from KVM and present the page encodings in the device > > tree > > under

Re: [Qemu-devel] [RFC PATCH v2 08/12] spapr: Only setup HTP if necessary.

On Tue, 2017-02-28 at 11:28 +1100, David Gibson wrote: > s/HTP/HPT/ in subject line. > > > On Thu, Feb 23, 2017 at 05:00:01PM +1100, Sam Bobroff wrote: > > > > If QEMU is using KVM, and KVM is capable of running in radix mode, > > guests can be run in real-mode without allocating a HPT (because

Re: [Qemu-devel] [PATCHv3 4/5] pseries: Enable HPT resizing for 2.9

achineClass *mc) >  { > +sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); > + >  spapr_machine_2_9_class_options(mc); >  SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_8); > +smc->resize_hpt_default = SPAPR_RESIZE_HPT_DISABLED; >  } >   >  DEFINE_SPAPR_MACHINE(2_8, "2.8", false); If people don't want this by default they should probably specify on the command line. Reviewed-by: Suraj Jitindar Singh <sjitindarsi...@gmail.com>

Re: [Qemu-devel] [PATCHv3 2/5] pseries: Stubs for HPT resizing

directly if the HPT is under > our > + * control or KVM's, which is what's really relevant here. > + * Unfortunately, in order to correctly size the HPT, we need to > + * know if we can do resizing, _before_ we attempt to allocate > it > + * with KVM.  Before that point, we don't officially know > whether > + * we'll control the HPT or not.  So we have to use a fallback > + * test for PR vs HV KVM to predict that. > + */ > +if (kvmppc_is_pr(kvm_state)) { > +return; > +} > + > +error_setg(errp, "Hash page table resizing not available with > this KVM version"); > +} > diff --git a/target-ppc/kvm_ppc.h b/target-ppc/kvm_ppc.h > index 841a29b..3e852ba 100644 > --- a/target-ppc/kvm_ppc.h > +++ b/target-ppc/kvm_ppc.h > @@ -59,6 +59,7 @@ bool kvmppc_has_cap_htm(void); >  int kvmppc_enable_hwrng(void); >  int kvmppc_put_books_sregs(PowerPCCPU *cpu); >  PowerPCCPUClass *kvm_ppc_get_host_cpu_class(void); > +void kvmppc_check_papr_resize_hpt(Error **errp); >   >  #else >   > @@ -270,6 +271,10 @@ static inline PowerPCCPUClass > *kvm_ppc_get_host_cpu_class(void) >  return NULL; >  } >   > +static inline void kvmppc_check_papr_resize_hpt(Error **errp) > +{ > +return; > +} >  #endif >   >  #ifndef CONFIG_KVM Since you're adding a new machine option it would be nice if this was documented in the help message. Either way it all seems sane: Reviewed-by: Suraj Jitindar Singh <sjitindarsi...@gmail.com>

Re: [Qemu-devel] [PATCHv3 3/5] pseries: Implement HPT resizing

On Mon, 2016-12-12 at 15:06 +1100, David Gibson wrote: > This patch implements hypercalls allowing a PAPR guest to resize its > own > hash page table.  This will eventually allow for more flexible memory > hotplug. > > The implementation is partially asynchronous, handled in a special > thread >

Re: [Qemu-devel] [PATCHv3 3/5] pseries: Implement HPT resizing

On Mon, 2016-12-12 at 15:06 +1100, David Gibson wrote: > This patch implements hypercalls allowing a PAPR guest to resize its > own > hash page table.  This will eventually allow for more flexible memory > hotplug. > > The implementation is partially asynchronous, handled in a special > thread >

Re: [Qemu-devel] [PATCHv3 5/5] pseries: Use smaller default hash page tables when guest can resize

>  sPAPRMachineState *spapr); >  int spapr_hpt_shift_for_ramsize(uint64_t ramsize); > +void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift, > +  Error **errp); >   >  /* rtas-configure-connector state */ >

Re: [Qemu-devel] [PATCHv3 4/5] pseries: Enable HPT resizing for 2.9

On Wed, 2016-12-14 at 17:20 +1100, David Gibson wrote: > On Wed, Dec 14, 2016 at 04:32:26PM +1100, Suraj Jitindar Singh wrote: > > > > On Mon, 2016-12-12 at 15:06 +1100, David Gibson wrote: > > > > > > We've now implemented a PAPR extensions which allows PAPR

Re: [Qemu-devel] [PATCHv3 3/5] pseries: Implement HPT resizing

On Wed, 2016-12-14 at 17:20 +1100, David Gibson wrote: > On Wed, Dec 14, 2016 at 04:30:57PM +1100, Suraj Jitindar Singh wrote: > > > > On Mon, 2016-12-12 at 15:06 +1100, David Gibson wrote: > [snip] > > > > > > > > +if (!(pte0 &am

[Qemu-devel] [RFC PATCH 05/17] target/ppc/POWER9: Adapt LPCR handling for POWER9

The logical partitioning control register controls a threads operation based on the partition it is currently executing. Add new definitions and update the mask used when writing to the LPCR based on the POWER9 spec. Signed-off-by: Suraj Jitindar Singh <sjitindarsi...@gmail.com> --- targ

[Qemu-devel] [RFC PATCH 09/17] target/ppc/POWER9: Remove SDR1 register

displaying register debug info. Signed-off-by: Suraj Jitindar Singh <sjitindarsi...@gmail.com> --- target/ppc/kvm.c| 10 +- target/ppc/mmu-hash64.c | 15 ++- target/ppc/translate.c | 6 -- target/ppc/translate_init.c | 16 +--- 4 files c

[Qemu-devel] [RFC PATCH 13/17] target/ppc/POWER9: Add cpu_has_work function for POWER9

-by: Suraj Jitindar Singh <sjitindarsi...@gmail.com> --- target/ppc/translate_init.c | 45 + 1 file changed, 45 insertions(+) diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c index 87297a7..9db004d 100644 --- a/targ

[Qemu-devel] [RFC PATCH 17/17] target/ppc/mmu_hash64: Fix incorrect shift value in amr calculation

this. Signed-off-by: Suraj Jitindar Singh <sjitindarsi...@gmail.com> --- target/ppc/mmu-hash64.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/ppc/mmu-hash64.h b/target/ppc/mmu-hash64.h index 73d7ce4..e8160c3 100644 --- a/target/ppc/mmu-hash64.h +++ b/target/ppc/mmu-ha

[Qemu-devel] [RFC PATCH 11/17] target/ppc/POWER9: Update to new pte format for POWER9 accesses

to perform this conversion, we remove the old functions which accessed either the first or second doubleword and introduce a new functions which access the entire pte, returning the entry converted back to the old format (if required). Update call sites accordingly. Signed-off-by: Suraj Jitindar Singh

[Qemu-devel] [RFC PATCH 14/17] target/ppc/debug: Print LPCR register value if register exists

It can be useful when debugging to print the LPCR value. Thus we add the LPCR to the "info registers" output if the register had been defined. Signed-off-by: Suraj Jitindar Singh <sjitindarsi...@gmail.com> --- target/ppc/translate.c | 3 +++ 1 file changed, 3 insertions(+) dif

[Qemu-devel] [RFC PATCH 04/17] target/ppc/POWER9: Add ISAv3.00 MMU definition

POWER9 processors implement the mmu as defined in version 3.00 of the ISA. Add a definition for this mmu model and set the POWER9 cpu model to use this mmu model. Signed-off-by: Suraj Jitindar Singh <sjitindarsi...@gmail.com> --- target/ppc/cpu-qom.h| 5 - target/ppc/mmu_he

[Qemu-devel] [RFC PATCH 00/17] target/ppc: Implement POWER9 pseries tcg legacy kernel support

nto what I think are logical chunks, how exactly this should be split up is up for debate. A current upstream kernel with POWER9 support added to the architecture vector should correctly report a POWER9 cpu under /proc/cpuinfo. Suraj Jitindar Singh (17): powerpc/cpu-models: rename ISAv3.00 l

[Qemu-devel] [RFC PATCH 03/17] target/ppc: Add pcr_supported to POWER9 cpu class definition

pcr_supported is used to define the supported PCR values for a given processor. A POWER9 processor can support 3.00, 2.07, 2.06 and 2.05 compatibility modes, thus we set this accordingly. Signed-off-by: Suraj Jitindar Singh <sjitindarsi...@gmail.com> --- target/ppc/cpu.h| 1 +

[Qemu-devel] [RFC PATCH 01/17] powerpc/cpu-models: rename ISAv3.00 logical PVR definition

This logical PVR value now corresponds to ISA version 3.00 so rename it accordingly. Signed-off-by: Suraj Jitindar Singh <sjitindarsi...@gmail.com> --- target/ppc/cpu-models.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/ppc/cpu-models.h b/target/ppc/cpu-mo

[Qemu-devel] [RFC PATCH 15/17] tcg/POWER9: NOOP the cp_abort instruction

paste facility and that we don't claim to support it, we can just noop this instruction. Signed-off-by: Suraj Jitindar Singh <sjitindarsi...@gmail.com> --- target/ppc/translate.c | 5 + 1 file changed, 5 insertions(+) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 5

[Qemu-devel] [RFC PATCH 12/17] target/ppc/POWER9: Add POWER9 pa-features definition

Add a pa-features definition which includes all of the new fields which have been added, note we don't claim support for any of these new features at this stage. Signed-off-by: Suraj Jitindar Singh <sjitindarsi...@gmail.com> --- hw/ppc/spapr.c | 18 ++ 1 file chang

[Qemu-devel] [RFC PATCH 10/17] target/ppc/POWER9: Add POWER9 mmu fault handler

updated to check if the partition is using segment tables. Currently only legacy hash (no segment tables) is supported. Signed-off-by: Suraj Jitindar Singh <sjitindarsi...@gmail.com> --- target/ppc/mmu-hash64.c | 8 target/ppc/mmu.h| 8 target/ppc/mmu_he

[Qemu-devel] [RFC PATCH 08/17] target/ppc/POWER9: Add external partition table pointer to cpu state

Similarly to how we have an external hpt pointer in the cpu state, add an external partition table pointer and update it to point to the partition table entry in the machine state struct on cpu reset. Signed-off-by: Suraj Jitindar Singh <sjitindarsi...@gmail.com> --- hw/ppc/spapr_cpu_core.

[Qemu-devel] [RFC PATCH 16/17] target/ppc/mmu_hash64: Fix printing unsigned as signed int

We were printing an unsigned value as a signed value, fix this. Signed-off-by: Suraj Jitindar Singh <sjitindarsi...@gmail.com> --- target/ppc/mmu-hash64.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index 0

[Qemu-devel] [RFC PATCH 06/17] target/ppc/POWER9: Direct all instr and data storage interrupts to the hypv

Jitindar Singh <sjitindarsi...@gmail.com> --- target/ppc/mmu-hash64.c | 20 ++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index 3a2acb8..fe7da18 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-ha

[Qemu-devel] [RFC PATCH 02/17] hw/ppc/spapr: Add POWER9 to pseries cpu models

Add POWER9 cpu to list of spapr core models which allows it to be specified as the cpu model for a pseries guest (e.g. -machine pseries -cpu POWER9). Signed-off-by: Suraj Jitindar Singh <sjitindarsi...@gmail.com> --- hw/ppc/spapr_cpu_core.c | 3 +++ 1 file changed, 3 insertions(+) diff

[Qemu-devel] [RFC PATCH 07/17] target/ppc/POWER9: Add partition table pointer to sPAPRMachineState

POWER9 uses a partition table to store information relating to how address translation is performed on a per partition basis. Add a data area for this to the sPAPRMachineState struct and (re)allocate it on machine reset. Signed-off-by: Suraj Jitindar Singh <sjitindarsi...@gmail.com> ---

Re: [Qemu-devel] [PATCHv5 for 2.9 3/6] pseries: Implement HPT resizing

On Tue, 2016-12-20 at 16:58 +1100, David Gibson wrote: > This patch implements hypercalls allowing a PAPR guest to resize its > own > hash page table.  This will eventually allow for more flexible memory > hotplug. > > The implementation is partially asynchronous, handled in a special > thread >

Re: [Qemu-devel] [RFC PATCH v2 08/12] spapr: Only setup HTP if necessary.

On Tue, 2017-02-28 at 14:19 +1100, David Gibson wrote: > On Tue, Feb 28, 2017 at 01:25:17PM +1100, Suraj Jitindar Singh wrote: > > > > On Tue, 2017-02-28 at 11:28 +1100, David Gibson wrote: > > > > > > s/HTP/HPT/ in subject line. > > > > > >

Re: [Qemu-devel] [PATCH] ppc: fix ppc_set_compat() with KVM PR

n QEMU anyway. > > [1] http://patchwork.ozlabs.org/patch/782039/ > > Signed-off-by: Greg Kurz <gr...@kaod.org> I meant to send a follow up but it fell on my priority list so thanks for this Looks good to me Reviewed-by: Suraj Jitindar Singh <sjitindarsi...@gmail.com>

Re: [Qemu-devel] [PATCH] target/ppc: Only set PCR in kvm if actually in a compat mode

On Mon, 2017-07-03 at 19:20 +1000, David Gibson wrote: > On Mon, Jul 03, 2017 at 01:18:38PM +1000, Suraj Jitindar Singh wrote: > > On Fri, 2017-06-30 at 14:03 +1000, David Gibson wrote: > > > On Thu, Jun 29, 2017 at 02:59:39PM +1000, Suraj Jitindar Singh > > > w

Re: [Qemu-devel] CPU hotplug on POWER9 (TCG) fails in ppc_radix64_handle_mmu_fault

Hi Cedric, On Wed, 2017-07-12 at 19:19 +0200, Cédric Le Goater wrote: > Hi,  > > Today, if you try to hotplug a CPU on a POWER9 guest (TCG), it fails > with an assert on the LPCR_UPRT bit missing in > ppc_radix64_handle_mmu_fault() > >   (qemu) device_add

Re: [Qemu-devel] [PATCH] target/ppc: fix CPU hotplug when radix is enabled (TCG)

ix and > update > the default LPCR to keep new CPUs in sync. > > Signed-off-by: Cédric Le Goater <c...@kaod.org> Reviewed-by: Suraj Jitindar Singh <sjitindarsi...@gmail.com> > --- >  target/ppc/translate_init.c | 10 +- >  1 file changed, 9 insertions(+), 1 deletion(

Re: [Qemu-devel] [Qemu-ppc] [PATCH] target/ppc/cpu-models: set POWER9_v1.0 as POWER9 DD1

On Wed, 2017-06-28 at 18:41 +0200, Greg Kurz wrote: > On Wed, 28 Jun 2017 18:18:06 +0200 > Laurent Vivier wrote: > > > On 28/06/2017 13:59, Greg Kurz wrote: > > > On Wed, 28 Jun 2017 12:23:06 +0200 > > > Cédric Le Goater wrote: > > >    > > > > On 06/28/2017

[Qemu-devel] [PATCH] target/ppc: Only set PCR in kvm if actually in a compat mode

a compat mode of 0 set pcr and arch_compat in the vcore struct to zero, both of which are initialised to zero anyway. Fixes: 37f516defa2e ("pseries: Reset CPU compatibility mode") Signed-off-by: Suraj Jitindar Singh <sjitindarsi...@gmail.com> --- Based on: dwg/ppc-for-2.10 tar

Re: [Qemu-devel] [Qemu-ppc] [PATCH] target/ppc/cpu-models: set POWER9_v1.0 as POWER9 DD1

On Thu, 2017-06-29 at 15:37 +1000, Suraj Jitindar Singh wrote: > On Wed, 2017-06-28 at 18:41 +0200, Greg Kurz wrote: > > On Wed, 28 Jun 2017 18:18:06 +0200 > > Laurent Vivier <lviv...@redhat.com> wrote: > > > > > On 28/06/2017 13:59, Greg Kurz wrote: > &

Re: [Qemu-devel] [PATCH] target/ppc: Only set PCR in kvm if actually in a compat mode

On Fri, 2017-06-30 at 14:03 +1000, David Gibson wrote: > On Thu, Jun 29, 2017 at 02:59:39PM +1000, Suraj Jitindar Singh wrote: > > The Processor Compatibility Register (PCR) I used to set the > > compatibility mode of the processor using the SET_ONE_REG ioctl on > > KV

[Qemu-devel] [Qemu-PPC] [PATCH 1/3] target/ppc: Refactor tcg radix mmu code

() function into the caller. This means the ppc_radix64_walk_tree() function can be used without protection checking which is useful for debugging. ppc_radix64_walk_tree() no longer needs to take the rwx and prot variables. Signed-off-by: Suraj Jitindar Singh <sjitindarsi...@gmail.com> --- target/p

[Qemu-devel] [Qemu-PPC] [PATCH 3/3] target/ppc: Add debug function to dump radix mmu translations

. This is called when "info tlb" is invoked in the qemu console. Previously this command had no output when invoked with a radix guest. Signed-off-by: Suraj Jitindar Singh <sjitindarsi...@gmail.com> --- target/ppc/mmu-radix64.c | 49

[Qemu-devel] [Qemu-PPC] [PATCH 0/3] target/ppc: Implement radix mmu debug functions

is already implemented for the hash mmu. A slight refactor of the radix mmu emulation code was necessary to enable the debug code to call existing functions. Suraj Jitindar Singh (3): target/ppc: Refactor tcg radix mmu code target/ppc: Add debug function for radix mmu translation target/ppc

[Qemu-devel] [Qemu-PPC] [PATCH 2/3] target/ppc: Add debug function for radix mmu translation

reuse ppc_radix64_walk_tree() which is used by the radix fault handler since the process of walking the radix tree is identical. Reported-by: Balbir Singh <bsinghar...@gmail.com> Signed-off-by: Suraj Jitindar Singh <sjitindarsi...@gmail.com> --- target/ppc/mmu-ra

Re: [Qemu-devel] [Qemu-ppc] [PATCHv5 2/4] pseries: Move CPU compatibility property to machine

machine property > instead of the now deprecated cpu property. > > Signed-off-by: David Gibson <da...@gibson.dropbear.id.au> Looks good to me and no longer segfaults :) Tried a few configurations and behaves as expected: Tested-by: Suraj Jitindar Singh <sjitindarsi...@gmail.com> &

Re: [Qemu-devel] [Qemu-ppc] [PATCHv5 0/4] Clean up compatibility mode handling

On Thu, 2017-06-08 at 14:17 +1000, David Gibson wrote: > On Fri, Jun 02, 2017 at 01:15:03PM +1000, David Gibson wrote: > > This is a rebased and revised version of my patches revising CPU > > compatiblity mode handling on ppc, last posted in November.  Since > > then, many of the patches have

Re: [Qemu-devel] [PATCH] monitor: Add -a (all) option to info registers

On Wed, 2017-06-07 at 20:16 +0100, Dr. David Alan Gilbert wrote: > * Suraj Jitindar Singh (sjitindarsi...@gmail.com) wrote: > > The info registers command in the qemu monitor is used to dump > > register > > values. > > > > Currently this command uses

[Qemu-devel] [PATCH 1/5] target/ppc: Implement large decrementer support for TCG

of the hypervisor decrementer is dependant on the cpu model, >= POWER9 -> large hypervisor decrementer. Signed-off-by: Suraj Jitindar Singh <sjitindarsi...@gmail.com> --- hw/ppc/ppc.c| 81 +++-- target/ppc/cpu-qom.h| 1 + targ

[Qemu-devel] [PATCH 5/5] target/ppc: Add cmd line option to disable the large decrementer

). A required option is supplied to force large decrementer, qemu will fail to start if the host doesn't support it. There is also a default option where the large decrementer will be enabled/disabled based on the capabilities of the hypervisor. Signed-off-by: Suraj Jitindar Singh <sjitinda

[Qemu-devel] [PATCH V2] monitor: Add -a (all) option to info registers

the monitor cpu and the re-running the command for each cpu in the system. I would be nice if there was an easier way to do this. Add the "-a" option to the info registers command to dump the register values for all cpus. Signed-off-by: Suraj Jitindar Singh <sjitindarsi...@gmail.com&

[Qemu-devel] [PATCH 2/5] target/ppc: Implement large decrementer support for KVM

to use the decrementer in large decrementer mode. This means adding functions to query the large decrementer support of the hypervisor and to enable the large decrementer with the hypervisor. Signed-off-by: Suraj Jitindar Singh <sjitindarsi...@gmail.com> --- target/ppc/kvm.c

[Qemu-devel] [PATCH 0/5] target/ppc: Implement support for the Large Decrementer

be disabled on the command line to ensure migration between hosts with differing levels of support or decrementer size. This patch series is based on the branch dwg/ppc-for-2.10 Suraj Jitindar Singh (5): target/ppc: Implement large decrementer support for TCG target/ppc: Implement large

[Qemu-devel] [PATCH 3/5] target/ppc: Implement migration support for large decrementer

Jitindar Singh <sjitindarsi...@gmail.com> --- hw/ppc/spapr.c | 63 ++ include/hw/ppc/spapr.h | 1 + 2 files changed, 64 insertions(+) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 5d10366..6ba869a 100644 --- a/hw/ppc/spapr.c +++ b/

[Qemu-devel] [PATCH 4/5] target/ppc: Enable the large decrementer for TCG and KVM guests

ER9 and the ibm,dec-bits device-tree property of the cpu node is present. Add the ibm,dec-bits property to the device-tree when the hypervisor can support it. After CAS enable the large decrementer if the guest is going to use it, this means setting the LPCR_LD bit. Signed-off-by: Suraj Jitindar Si

Re: [Qemu-devel] [Qemu-ppc] [RFC PATCH v2 4/4] spapr: Fix migration of Radix guests

On Tue, 2017-05-23 at 10:18 +0530, Bharata B Rao wrote: > On Mon, May 22, 2017 at 04:30:50PM +1000, Suraj Jitindar Singh wrote: > > On Fri, 2017-05-19 at 11:10 +0530, Bharata B Rao wrote: > > > Fix migration of radix guests by ensuring that we issue > > > KVM_PPC_CONF

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