(VSX_SCALAR_MOVE) is added since these
instructions vary only slightly from each other.
Macros to support VSX XX2 and XX3 form opcodes are also added.
These macros handle the overloading of opcode 2 space (instruction
bits 26:30) caused by AX and BX bits (29 and 30, respectively).
Signed-off-by: Tom Musta
This patch adds the VSX Splat Word (xxsplatw) instruction.
This is the first instruction to use the UIM immediate field
and consequently a decoder is also added.
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc/translate.c | 50
1
defined by the V2.06
Power ISA
(aka Power7).
b) The vector and scalar move instructions.
c) The logical instructions defined by V2.06.
d) Assorted permute and select instructions.
Tom Musta (13):
Abandon GEN_VSX_* macros
Add lxsdx
Add lxvdsx
Add lxvw4x
Add stxsdx
Add stxvw4x
Abandon GEN_VSX_* macros
This patch eliminates the GEN_VSX_LXVNX/GEN_VSX_STXVNX macros which
did not provide significant value above the general GEN_HANDLER_E
macro.
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc/translate.c | 12 ++--
1 files changed, 2 insertions(+), 10
This patch adds the Load VSX Vector Doubleword Splat Indexed
(lxvdsx) instruction.
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc/translate.c | 16
1 files changed, 16 insertions(+), 0 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
with two macros
(GEN_XXSEL_ROW and GEN_XX_SEL).
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc/translate.c | 83
1 files changed, 83 insertions(+), 0 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index
This patch adds the Load VSX Scalar Doubleowrd Indexed (lxsdx)
instruction.
The lower 8 bytes of the target register are undefined; this
implementation leaves those bytes unaltered.
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc/translate.c | 16
1 files changed
This patch adds the Store VSX Vector Word*4 Indexed (stxvw4x)
instruction.
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc/translate.c | 28
1 files changed, 28 insertions(+), 0 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
Single-Precision
- xvnabssp - Vector Negative Absolute Value Single-Precision
- xvnegsp - Vector Negate Single-Precision
- xvcpsgnsp - Vector Copy Sign Single-Precision
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc/translate.c | 68
This patch adds the Load VSX Vector Word*4 Indexed (lxvw4x)
instruction.
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc/translate.c | 31 +++
1 files changed, 31 insertions(+), 0 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
This patch adds the Store VSX Scalar Doubleword Indexed (stxsdx)
instruction.
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc/translate.c | 15 +++
1 files changed, 15 insertions(+), 0 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index
This patch adds the VSX logical instructions that are defined
by the Version 2.06 Power ISA (aka Power7):
- xxland
- xxlandc
- xxlor
- xxlxor
- xxlnor
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc/translate.c | 29 +
1 files changed, 29
This patch adds the VSX Merge High Word and VSX Merge Low Word
instructions.
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc/translate.c | 44
1 files changed, 44 insertions(+), 0 deletions(-)
diff --git a/target-ppc/translate.c b
This patch adds the VSX Shift Left Double by Word Immediate
(xxsldwi) instruction.
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc/translate.c | 62
1 files changed, 62 insertions(+), 0 deletions(-)
diff --git a/target-ppc
On 10/9/2013 3:09 PM, Richard Henderson wrote:
On 10/04/2013 06:23 AM, Tom Musta wrote:
+tcg_gen_andi_i64(a0, a0, 0xul); \
+tcg_gen_shli_i64(a1, a1, 32); \
+tcg_gen_shri_i64(b0, b0, 32
On 10/9/2013 3:13 PM, Richard Henderson wrote:
On 10/04/2013 06:24 AM, Tom Musta wrote:
+tcg_gen_and_i64(b, b, c);
+tcg_gen_not_i64(c, c);
+tcg_gen_and_i64(a, a, c);
tcg_gen_andc_i64.
+#define GEN_XXSEL() \
+GEN_XXSEL_ROW(0x00) \
+GEN_XXSEL_ROW(0x01) \
Why bother with defining
defined by the V2.06 Power ISA
(aka Power7).
b) The vector and scalar move instructions.
c) The logical instructions defined by V2.06.
d) Assorted permute and select instructions.
V2: reworked patches 4, 10, 11 and 12 per comments from Richard Henderson
(thanks, Richard!)
Tom Musta (13
This patch eliminates the GEN_VSX_LXVNX/GEN_VSX_STXVNX macros which
did not provide significant value above the general GEN_HANDLER_E
macro.
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc/translate.c | 12 ++--
1 files changed, 2 insertions(+), 10 deletions(-)
diff --git
This patch adds the Load VSX Scalar Doubleowrd Indexed (lxsdx)
instruction.
The lower 8 bytes of the target register are undefined; this
implementation leaves those bytes unaltered.
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc/translate.c | 16
1 files changed
This patch adds the Load VSX Vector Doubleword Splat Indexed
(lxvdsx) instruction.
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc/translate.c | 16
1 files changed, 16 insertions(+), 0 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
This patch adds the Load VSX Vector Word*4 Indexed (lxvw4x)
instruction.
V2: changed to use deposit_i64 per Richard Henderson's review.
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc/translate.c | 29 +
1 files changed, 29 insertions(+), 0 deletions
This patch adds the Store VSX Scalar Doubleword Indexed (stxsdx)
instruction.
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc/translate.c | 15 +++
1 files changed, 15 insertions(+), 0 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index
This patch adds the Store VSX Vector Word*4 Indexed (stxvw4x)
instruction.
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc/translate.c | 28
1 files changed, 28 insertions(+), 0 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
(VSX_SCALAR_MOVE) is added since these
instructions vary only slightly from each other.
Macros to support VSX XX2 and XX3 form opcodes are also added.
These macros handle the overloading of opcode 2 space (instruction
bits 26:30) caused by AX and BX bits (29 and 30, respectively).
Signed-off-by: Tom Musta
Single-Precision
- xvnabssp - Vector Negative Absolute Value Single-Precision
- xvnegsp - Vector Negate Single-Precision
- xvcpsgnsp - Vector Copy Sign Single-Precision
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc/translate.c | 68
This patch adds the VSX logical instructions that are defined
by the Version 2.06 Power ISA (aka Power7):
- xxland
- xxlandc
- xxlor
- xxlxor
- xxlnor
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc/translate.c | 29 +
1 files changed, 29
This patch adds the VSX Merge High Word and VSX Merge Low Word
instructions.
V2: Now implemented using deposit (per Richard Henderson's comment)
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc/translate.c | 41 +
1 files changed, 41
with two macros
(GEN_XXSEL_ROW and GEN_XX_SEL).
V2: (1) eliminated unecessary XXSEL macro (2) tighter implementation
using tcg_gen_andc_i64.
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc/translate.c | 76
1 files changed, 76
This patch adds the VSX Splat Word (xxsplatw) instruction.
This is the first instruction to use the UIM immediate field
and consequently a decoder is also added.
V2: reworked implementation per Richard Henderson's comments.
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc
This patch adds the VSX Shift Left Double by Word Immediate
(xxsldwi) instruction.
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc/translate.c | 62
1 files changed, 62 insertions(+), 0 deletions(-)
diff --git a/target-ppc
The comment preceding the float64_to_uint64 routine suggests that
the implementation is broken. And this is, indeed, the case.
This patch properly implements the conversion of a 64-bit floating
point number to an unsigned, 64 bit integer.
Note that the patch does not pass scripts/checkpatch.pl
The comment preceding the float64_to_uint64 routine suggests that
the implementation is broken. And this is, indeed, the case.
This patch properly implements the conversion of a 64-bit floating
point number to an unsigned, 64 bit integer.
Note that the patch does not pass scripts/checkpatch.pl
On 10/17/2013 11:31 AM, Stefan Weil wrote:
Am 17.10.2013 11:40, schrieb Alexander Graf:
Missing a SoB line.
Alex
There is already a mix of coding styles in fpu/softfloat.c, and your
patch adds large regions of new code.
Therefore I expect that such contributions should respect the QEMU
the softfloat-2a or -2b
license.
V2: Added softfloat license statement.
V3: Modified to meet QEMU coding conventions.
Signed-off-by: Tom Musta tommu...@gmail.com
---
fpu/softfloat.c | 95 ++-
1 files changed, 87 insertions(+), 8 deletions(-)
diff
On 10/22/2013 1:31 AM, Paolo Bonzini wrote:
Il 11/10/2013 14:02, Tom Musta ha scritto:
+case OP_CPSGN: { \
+TCGv_i64 xa = tcg_temp_new(); \
+tcg_gen_mov_i64(xa, cpu_vsrh(xA(ctx-opcode
From 37b74a6ca422e62b349692188c457bf6127a3a83 Mon Sep 17 00:00:00 2001
From: Tom Musta tommu...@gmail.com
Date: Thu, 3 Oct 2013 10:09:50 -0500
Subject: [PATCH 07/13] Add VSX Scalar Move Instructions
To: qemu-...@nongnu.org
This patch adds the VSX scalar move instructions:
- xsabsdp (Scalar
Single-Precision
- xvnabssp - Vector Negative Absolute Value Single-Precision
- xvnegsp - Vector Negate Single-Precision
- xvcpsgnsp - Vector Copy Sign Single-Precision
V3: Per Paolo Bonzini's suggestion, used a temporary for the
sign mask and andc.
Signed-off-by: Tom Musta tommu...@gmail.com
library and the existing PowerPC floating point helper code.
As with the previous series, the Power ISA V2.06 instructions are added
but the V2.07 instructions are not. The latter will be implemented in a
future patch series.
Tom Musta (19):
Add New softfloat Routines for VSX
Add set_fprf
/msg02622.html
for details.
This contribution can be licensed under either the softfloat-2a or -2b
license.
Signed-off-by: Tom Musta tommu...@gmail.com
---
fpu/softfloat.c | 45 +
include/fpu/softfloat.h | 22 ++
2 files
of the FPRF
field is made conditional via a parameter.
All invocations of this routine in existing instructions are
modified to pass 1 and thus retain their current behavior.
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc/fpu_helper.c | 103 +--
1
This patch adds the VSX floating point add instructions that are
defined by V2.06 of the PowerPC ISA: xsadddp, xvadddp and xvaddsp.
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc/fpu_helper.c | 46 ++
target-ppc/helper.h |6
This patch adds general support that will be used by the VSX helper
routines:
- a union describing the various VSR subfields.
- access routines to get and set VSRs
- VSX decoders
- a general routine to generate a handler that invokes a VSX
helper.
Signed-off-by: Tom Musta tommu
This patch adds the floating point subtraction instructions defined
by V2.06 of the PowerPC ISA: xssubdp, xvsubdp and xvsubsp.
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc/fpu_helper.c | 46 ++
target-ppc/helper.h |3
This patch adds the VSX floating point multiply instructions defined
by V2.06 of the PowerPC ISA: xsmuldp, xvmuldp, xvmulsp.
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc/fpu_helper.c | 47 +++
target-ppc/helper.h |3 +++
target
This patch adds the VSX floating point divide instructions defined
by V2.06 of the PowerPC ISA: xsdivdp, xvdivdp, xvdivsp.
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc/fpu_helper.c | 52 +++
target-ppc/helper.h |3 ++
target
This patch adds the VSX floating point reciprocal square root
estimate instructions defined by V2.06 of the PowerPC ISA: xsrsqrtedp,
xvrsqrtedp, xvrsqrtesp.
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc/fpu_helper.c | 44
target-ppc
This patch adds the VSX floating point square root instructions
defined by V2.06 of the PowerPC ISA: xssqrtdp, xvsqrtdp, xvsqrtsp.
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc/fpu_helper.c | 43 +++
target-ppc/helper.h |3
This patch adds the VSX floating point test for software square
root instructions defined by V2.06 of the PowerPC ISA: xstsqrtdp,
xvtsqrtdp, xvtsqrtsp.
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc/fpu_helper.c | 52 +++
target-ppc
This patch adds the VSX scalar floating point compare ordered
and unordered instructions.
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc/fpu_helper.c | 39 +++
target-ppc/helper.h |2 ++
target-ppc/translate.c |4
3 files
as well as one might
think. Therefore specific routines for comparing 64 and 32
bit floating point numbers are implemented in the PowerPC
helper code.
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc/fpu_helper.c | 162 +++
target-ppc/helper.h
- xsnmaddmdp, xvnmaddmdp, xvnmaddmsp
- xsnmsubadp, xvnmsubadp, xvnmsubasp
- xsnmsubmdp, xvnmsubmdp, xvnmsubmsp
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc/fpu_helper.c | 106 +++
target-ppc/helper.h | 24 +++
target-ppc
This patch adds the VSX floating point compare vector instructions:
- xvcmpeqdp[.], xvcmpgedp[.], xvcmpgtdp[.]
- xvcmpeqsp[.], xvcmpgesp[.], xvcmpgtsp[.]
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc/fpu_helper.c | 58 +++
target
This patch adds the VSX instructions that convert between floating
point formats: xscvdpsp, xscvspdp, xvcvdpsp, xvcvspdp.
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc/fpu_helper.c | 46 ++
target-ppc/helper.h |4
target
This patch adds the VSX Round to Floating Point Integer instructions:
- xsrdpi, xsrdpic, xsrdpim, xsrdpip, xsrdpiz
- xvrdpi, xvrdpic, xvrdpim, xvrdpip, xvrdpiz
- xvrspi, xvrspic, xvrspim, xvrspip, xvrspiz
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc/fpu_helper.c | 68
, xvcvuxddp, xvcvuxwdp
- xvcvsxdsp, xscvsxwsp, xvcvuxdsp, xvcvuxwsp
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc/fpu_helper.c | 108 +++
target-ppc/helper.h | 22 ++
target-ppc/translate.c | 44 +++
3
This patch adds the VSX floating point reciprocal estimate instructions
defined by V2.06 of the PowerPC ISA: xsredp, xvredp, xvresp.
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc/fpu_helper.c | 35 +++
target-ppc/helper.h |3 +++
target-ppc
This patch adds the VSX floating point test for software divide
instructions defined by V2.06 of the PowerPC ISA: xstdivdp, xvtdivdp,
and xvtdivsp.
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc/fpu_helper.c | 55 +++
target-ppc/helper.h
On 10/24/2013 1:51 PM, Richard Henderson wrote:
On 10/24/2013 09:19 AM, Tom Musta wrote:
+#define GEN_VSX_HELPER_2(name, op1, op2, inval, type) \
+static void gen_##name(DisasContext * ctx
On 10/24/2013 3:45 PM, Richard Henderson wrote:
On 10/24/2013 09:26 AM, Tom Musta wrote:
Because of the Power ISA definitions of maximum and minimum
on various boundary cases, the standard softfloat comparison
routines (e.g. float64_lt) do not work as well as one might
think. Therefore
Peter: Thanks for your feedback. Responses below.
On 10/25/2013 6:55 AM, Peter Maydell wrote:
On 24 October 2013 17:17, Tom Musta tommu...@gmail.com wrote:
This patch adds routines to the softfloat library that are useful for
the PowerPC VSX implementation. The routines are, however
On 10/25/2013 6:44 AM, Peter Maydell wrote:
On 25 October 2013 12:34, Alex Bennée alex.ben...@linaro.org wrote:
Is it worth adding some sort of test into make check to defend these
softfloat functions against unintentional breakage? It would certainly
be worthwhile as soon as multiple arches
On 10/24/2013 3:38 PM, Richard Henderson wrote:
On 10/24/2013 09:25 AM, Tom Musta wrote:
\
snip
+ft1 = tp##_to_##btp(s-fld[i], env-fp_status); \
+ft0 = btp##_##sum(ft0, ft1, env-fp_status
On 10/24/2013 5:10 PM, Peter Maydell wrote:
Can't you use the min and max softfloat functions? Those are
there specifically because the corner cases mean you can't
implement them using the comparisons. (For instance for
the example you quote of max(-0.0, +0.0) they return +0.0
as you require.)
On 10/24/2013 3:38 PM, Richard Henderson wrote:
On 10/24/2013 09:25 AM, Tom Musta wrote:
\
+ft0 = tp##_to_##btp(xa.fld[i], env-fp_status); \
+ft1 = tp##_to_##btp(m-fld[i], env-fp_status
On 10/25/2013 11:42 AM, Richard Henderson wrote:
I believe that a better implementation could use float*_muladd, and check the
result for float_flag_invalid. If set, compute the intermediate product so you
can figure out the VXISI setting. But we'd expect that to be an unlikely path.
From 89de52ee03f68cef1f3343d3275162427ec22ded Mon Sep 17 00:00:00 2001
From: Tom Musta tommu...@gmail.com
Date: Tue, 29 Oct 2013 07:52:19 -0500
Subject:
To: qemu-...@nongnu.org
This is the third series of patches to add PowerPC VSX emulation support
to QEMU.
This series adds the floating point
the softfloat-2a or -2b
license.
V2: Added softfloat license statement.
V3: Modified to meet QEMU coding conventions.
Signed-off-by: Tom Musta tommu...@gmail.com
---
fpu/softfloat.c | 95 ++-
1 files changed, 87 insertions(+), 8 deletions(-)
diff
-by: Tom Musta tommu...@gmail.com
---
fpu/softfloat.c | 45 +
include/fpu/softfloat.h |1 +
2 files changed, 46 insertions(+), 0 deletions(-)
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
index 3070eaa..cb03dca 100644
--- a/fpu/softfloat.c
of the FPRF
field is made conditional via a parameter.
All invocations of this routine in existing instructions are
modified to pass 1 and thus retain their current behavior.
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc/fpu_helper.c | 103 +--
1
This patch adds the floating point addition and subtraction
instructions defined by V2.06 of the PowerPC ISA: xssubdp,
xvsubdp and xvsubsp.
V2: re-implemented helper macro and combined add and substract.
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc/fpu_helper.c | 51
This patch adds general support that will be used by the VSX helper
routines:
- a union describing the various VSR subfields.
- access routines to get and set VSRs
- VSX decoders
- a general routine to generate a handler that invokes a VSX
helper.
Signed-off-by: Tom Musta tommu
This patch adds the VSX floating point divide instructions defined
by V2.06 of the PowerPC ISA: xsdivdp, xvdivdp, xvdivsp.
V2: re-implemented the VSX_DIV macro.
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc/fpu_helper.c | 49
This patch adds the VSX floating point multiply instructions defined
by V2.06 of the PowerPC ISA: xsmuldp, xvmuldp, xvmulsp.
V2: re-implemented VSX_MUL macro.
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc/fpu_helper.c | 46 ++
target
This patch adds the VSX floating point reciprocal estimate instructions
defined by V2.06 of the PowerPC ISA: xsredp, xvredp, xvresp.
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc/fpu_helper.c | 35 +++
target-ppc/helper.h |3 +++
target-ppc
This patch adds the VSX floating point square root instructions
defined by V2.06 of the PowerPC ISA: xssqrtdp, xvsqrtdp, xvsqrtsp.
V2: re-implemented the VSX_SQRT macro.
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc/fpu_helper.c | 44
This patch adds the VSX floating point test for software square
root instructions defined by V2.06 of the PowerPC ISA: xstsqrtdp,
xvtsqrtdp, xvtsqrtsp.
V2: (a) using locally implemented ppc_float*_get_unbiased_exp
routines (b) eliminated dependency on float*_is_denormal().
Signed-off-by: Tom
-off-by: Tom Musta tommu...@gmail.com
---
target-ppc/fpu_helper.c | 67 +++
target-ppc/helper.h |3 ++
target-ppc/translate.c |6
3 files changed, 76 insertions(+), 0 deletions(-)
diff --git a/target-ppc/fpu_helper.c b/target-ppc
- xsnmaddmdp, xvnmaddmdp, xvnmaddmsp
- xsnmsubadp, xvnmsubadp, xvnmsubasp
- xsnmsubmdp, xvnmsubmdp, xvnmsubmsp
V2: reworked implementation per comments from Richard Henderson and
Peter Maydell.
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc/fpu_helper.c | 100
This patch adds the VSX scalar floating point compare ordered
and unordered instructions.
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc/fpu_helper.c | 39 +++
target-ppc/helper.h |2 ++
target-ppc/translate.c |4
3 files
This patch adds the VSX instructions that convert between floating
point formats: xscvdpsp, xscvspdp, xvcvdpsp, xvcvspdp.
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc/fpu_helper.c | 46 ++
target-ppc/helper.h |4
target
as well as one might
think. Therefore specific routines for comparing 64 and 32
bit floating point numbers are implemented in the PowerPC
helper code.
V2: consolidated into a single macro, using the softfloat
float*_max/float*_min routines.
Signed-off-by: Tom Musta tommu...@gmail.com
---
target
This patch adds the VSX floating point compare vector instructions:
- xvcmpeqdp[.], xvcmpgedp[.], xvcmpgtdp[.]
- xvcmpeqsp[.], xvcmpgesp[.], xvcmpgtsp[.]
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc/fpu_helper.c | 57 +++
target
, xvcvuxddp, xvcvuxwdp
- xvcvsxdsp, xscvsxwsp, xvcvuxdsp, xvcvuxwsp
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc/fpu_helper.c | 107 +++
target-ppc/helper.h | 22 ++
target-ppc/translate.c | 44 +++
3
This patch adds the VSX Round to Floating Point Integer instructions:
- xsrdpi, xsrdpic, xsrdpim, xsrdpip, xsrdpiz
- xvrdpi, xvrdpic, xvrdpim, xvrdpip, xvrdpiz
- xvrspi, xvrspic, xvrspim, xvrspip, xvrspiz
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc/fpu_helper.c | 68
This patch adds the VSX floating point reciprocal square root
estimate instructions defined by V2.06 of the PowerPC ISA: xsrsqrtedp,
xvrsqrtedp, xvrsqrtesp.
V2: re-implemented VSX_RSQRTE macro.
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc/fpu_helper.c | 45
On 10/31/2013 5:58 PM, Alexander Graf wrote:
On 11.10.2013, at 05:57, Tom Musta tommu...@gmail.com wrote:
This patch adds the Load VSX Scalar Doubleowrd Indexed (lxsdx)
instruction.
The lower 8 bytes of the target register are undefined; this
implementation leaves those bytes unaltered
instructions.
V2: reworked patches 4, 10, 11 and 12 per comments from Richard Henderson
(thanks, Richard!)
V3: reworked patches 7 8 per comments from Paolo Bonzini (thanks, Paulo)
Tom Musta (13):
Abandon GEN_VSX_* macros
Add lxsdx
Add lxvdsx
Add lxvw4x
Add stxsdx
Add stxvw4x
Add
This patch eliminates the GEN_VSX_LXVNX/GEN_VSX_STXVNX macros which
did not provide significant value above the general GEN_HANDLER_E
macro.
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc/translate.c | 12 ++--
1 files changed, 2 insertions(+), 10 deletions(-)
diff --git
This patch adds the Store VSX Scalar Doubleword Indexed (stxsdx)
instruction.
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc/translate.c | 15 +++
1 files changed, 15 insertions(+), 0 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index
This patch adds the Load VSX Scalar Doubleowrd Indexed (lxsdx)
instruction.
The lower 8 bytes of the target register are undefined; this
implementation leaves those bytes unaltered.
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc/translate.c | 16
1 files changed
This patch adds the Load VSX Vector Word*4 Indexed (lxvw4x)
instruction.
V2: changed to use deposit_i64 per Richard Henderson's review.
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc/translate.c | 29 +
1 files changed, 29 insertions(+), 0 deletions
This patch adds the Load VSX Vector Doubleword Splat Indexed
(lxvdsx) instruction.
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc/translate.c | 16
1 files changed, 16 insertions(+), 0 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
This patch adds the VSX logical instructions that are defined
by the Version 2.06 Power ISA (aka Power7):
- xxland
- xxlandc
- xxlor
- xxlxor
- xxlnor
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc/translate.c | 29 +
1 files changed, 29
Single-Precision
- xvnabssp - Vector Negative Absolute Value Single-Precision
- xvnegsp - Vector Negate Single-Precision
- xvcpsgnsp - Vector Copy Sign Single-Precision
V3: Per Paolo Bonzini's suggestion, used a temporary for the
sign mask and andc.
Signed-off-by: Tom Musta tommu...@gmail.com
with two macros
(GEN_XXSEL_ROW and GEN_XX_SEL).
V2: (1) eliminated unecessary XXSEL macro (2) tighter implementation
using tcg_gen_andc_i64.
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc/translate.c | 76
1 files changed, 76 insertions
Paolo Bonzini, moved the sign mask into a
temporary and used andc.
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc/translate.c | 69
1 files changed, 69 insertions(+), 0 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc
This patch adds the VSX Splat Word (xxsplatw) instruction.
This is the first instruction to use the UIM immediate field
and consequently a decoder is also added.
V2: reworked implementation per Richard Henderson's comments.
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc/translate.c
This patch adds the VSX Merge High Word and VSX Merge Low Word
instructions.
V2: Now implemented using deposit (per Richard Henderson's comment)
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc/translate.c | 41 +
1 files changed, 41
This patch adds the Store VSX Vector Word*4 Indexed (stxvw4x)
instruction.
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc/translate.c | 28
1 files changed, 28 insertions(+), 0 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
This patch adds the VSX Shift Left Double by Word Immediate
(xxsldwi) instruction.
Signed-off-by: Tom Musta tommu...@gmail.com
---
target-ppc/translate.c | 62
1 files changed, 62 insertions(+), 0 deletions(-)
diff --git a/target-ppc
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