Add the cpufreq device to arm64 virt machine
Signed-off-by: Heyi Guo
Signed-off-by: Ying Fang
---
default-configs/aarch64-softmmu.mak | 1 +
hw/acpi/Kconfig | 4
hw/arm/virt.c | 13 +
3 files changed, 18 insertions(+)
diff --git a
The generic register descriptor describes the localtion of a
fixed width register within any of the ACPI-defined address space.
This is needed to declare the ACPI CPPC registers.
Signed-off-by: Heyi Guo
Signed-off-by: Ying Fang
---
hw/acpi/aml-build.c | 22
work.
Ying Fang (4):
acpi: add aml_generic_register
acpi/cppc: add ACPI CPPC registers
arm_virt: add the cpufreq device model
arm_virt: create the cpufreq device
default-configs/aarch64-softmmu.mak | 1 +
hw/acpi/Kconfig | 4 +
hw/acpi/Makefile.objs
same value, since we don't support guest performance scaling.
Performance counters are also not emulated and they simply return 1
if readed, and guest should fallback to use the desired performance
value as the current performance.
Signed-off-by: Heyi Guo
Signed-off-by: Ying Fang
---
hw
The Continuous Performance Control Package is used to
describe the ACPI CPPC registers.
Signed-off-by: Heyi Guo
Signed-off-by: Ying Fang
---
hw/arm/virt-acpi-build.c| 74 -
hw/arm/virt.c | 1 +
include/hw/acpi/acpi-defs.h | 32
The generic register descriptor describes the localtion of a
fixed width register within any of the ACPI-defined address space.
This is needed to declare the ACPI CPPC registers.
Signed-off-by: Heyi Guo
Signed-off-by: Ying Fang
---
hw/acpi/aml-build.c | 22
work.
Ying Fang (4):
acpi: Add aml_generic_register
acpi/cppc: Add ACPI CPPC registers
arm: Add the cpufreq device model
arm: Create the cpufreq device
default-configs/aarch64-softmmu.mak | 1 +
hw/acpi/Kconfig | 4 +
hw/acpi/Makefile.objs | 1 +
hw
Add the cpufreq device to arm64 virt machine
Signed-off-by: Heyi Guo
Signed-off-by: Ying Fang
---
default-configs/aarch64-softmmu.mak | 1 +
hw/acpi/Kconfig | 4
hw/arm/virt.c | 13 +
3 files changed, 18 insertions(+)
diff --git a
same value, since we don't support guest performance scaling.
Performance counters are also not emulated and they simply return 1
if readed, and guest should fallback to use the desired performance
value as the current performance.
Signed-off-by: Heyi Guo
Signed-off-by: Ying Fang
---
hw
The Continuous Performance Control Package is used to
describe the ACPI CPPC registers.
Signed-off-by: Heyi Guo
Signed-off-by: Ying Fang
---
hw/arm/virt-acpi-build.c| 74 -
hw/arm/virt.c | 1 +
include/hw/acpi/acpi-defs.h | 32
On 2017/11/29 17:42, Dr. David Alan Gilbert wrote:
> * Ying Fang (fangyi...@huawei.com) wrote:
>>
>> On 2017/11/28 18:18, Dr. David Alan Gilbert wrote:
>>> * fangying (fangyi...@huawei.com) wrote:
>>>> QEMU will abort when vhost-user process is
On 2017/12/1 22:39, Michael S. Tsirkin wrote:
> On Fri, Dec 01, 2017 at 01:58:32PM +0800, fangying wrote:
>> QEMU will abort when vhost-user process is restarted during migration
>> when vhost_log_global_start/stop is called. The reason is clear that
>> vhost_dev_set_log returns -1 because network
On 2017/12/7 0:34, Michael S. Tsirkin wrote:
> On Wed, Dec 06, 2017 at 09:30:27PM +0800, Ying Fang wrote:
>>
>> On 2017/12/1 22:39, Michael S. Tsirkin wrote:
>>> On Fri, Dec 01, 2017 at 01:58:32PM +0800, fangying wrote:
>>>> QEMU will abort when vhost-user p
在 2017/11/16 3:39, Dr. David Alan Gilbert 写道:
> * Yori Fang (fangyi...@huawei.com) wrote:
>>
>>
>> 在 2017/11/14 19:40, Marc-André Lureau 写道:
>>> Hi
>>>
>>> On Tue, Nov 14, 2017 at 8:09 AM, fangying wrote:
Hi all,
We have a vm running migration with vhost-user as network backend, we
se network connection is temporarily
>> lost. To handle this situation, let's cancel migration here.
>>
>> Signed-off-by: Ying Fang
>
> I thought we had agreed not to use migrate_fd_cancel here - that's for
> cancelling not erroring.
>
> Dave
We can no
On 2019/1/16 4:15, John Snow wrote:
>
>
> On 1/8/19 10:20 PM, Ying Fang wrote:
>>
>>
>> On 2019/1/8 20:46, Kevin Wolf wrote:
>>> Am 29.12.2018 um 07:33 hat Ying Fang geschrieben:
>>>> Hi.
>>>> Recently one of our customer complained
ping
On 2018/12/29 14:33, Ying Fang wrote:
> Hi.
> Recently one of our customer complained about the I/O performance of QEMU
> emulated host cdrom device.
> I did some investigation on it and there was still some point I could not
> figure out. So I had to ask for your help.
&
On 2019/1/8 20:46, Kevin Wolf wrote:
> Am 29.12.2018 um 07:33 hat Ying Fang geschrieben:
>> Hi.
>> Recently one of our customer complained about the I/O performance of QEMU
>> emulated host cdrom device.
>> I did some investigation on it and there was still some p
tx_prepare and
it is proved to have the hang fixed in our test.
This hang is not observed on the x86 platform however it can be easily
reproduced on the aarch64 platform, thus it is architecture related.
Not sure if this is revelant to Commit eabc977973103527bbb8fed69c91cfaa6691f8ab
Signed-off-b
tx_prepare and
it is proved to have the hang fixed in our test.
This hang is not observed on the x86 platform however it can be easily
reproduced on the aarch64 platform, thus it is architecture related.
Not sure if this is revelant to Commit eabc977973103527bbb8fed69c91cfaa6691f8ab
Signed-off-b
On 2020/4/2 16:47, Paolo Bonzini wrote:
On 02/04/20 04:44, Ying Fang wrote:
Normal VM runtime is not affected by this hang since there is always some
timer timeout or subsequent io worker come and notify the main thead.
To fix this problem, a memory barrier is added to aio_ctx_prepare and
it
On 8/7/2020 4:13 PM, Kevin Wolf wrote:
Am 07.08.2020 um 09:42 hat Ying Fang geschrieben:
On 8/6/2020 5:13 PM, Kevin Wolf wrote:
Am 05.08.2020 um 04:38 hat Ying Fang geschrieben:
From: fangying
When qemu or qemu-nbd process uses a qcow2 image and configured with
'cache = none'
Hi, Ike.
I think this tricky bug was fixed by Paolo last month.
Please try patch
https://git.qemu.org/?p=qemu.git;a=commitdiff;h=5710a3e09f9b85801e5ce70797a4a511e5fc9e2c.
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs
allocated cluster.
Signed-off-by: Ying Fang
diff --git a/block/qcow2-cache.c b/block/qcow2-cache.c
index 7444b9c..ab6e812 100644
--- a/block/qcow2-cache.c
+++ b/block/qcow2-cache.c
@@ -266,6 +266,22 @@ int qcow2_cache_flush(BlockDriverState *bs, Qcow2Cache *c)
return result;
}
oesn't really run on aarch64 platform for smbios test can't run on
uefi only platform yet.
Signed-off-by: Ying Fang
Signed-off-by: Heyi Guo
---
tests/bios-tables-test.c | 42
1 file changed, 42 insertions(+)
diff --git a/tests/bios-tables-test.c b/
quot; in option names to "-"
- check if option value is too large to fit in SMBIOS type 4 speed
fields.
Cc: "Michael S. Tsirkin"
Cc: Igor Mammedov
Ying Fang (2):
hw/smbios: add options for type 4 max-speed and current-speed
tests/bios-tables-test: add smbios cpu speed
or the max speed and current speed of processor, for
"max speed" identifies a capability of the system, and "current speed"
identifies the processor's speed at boot (see smbios spec), but some
applications do not tell the differences.
Reviewed-by: Igor Mammedov
Signed-off-by
On 8/6/2020 2:01 PM, Michael S. Tsirkin wrote:
On Thu, Aug 06, 2020 at 11:56:32AM +0800, Ying Fang wrote:
From: fangying
Hi, this patchset was previously posted by my teamate Heyi Guo several
months ago, however we missed the merge window. It is reposted here to
make it an end. Thanks
On 8/5/2020 10:43 AM, no-re...@patchew.org wrote:
Patchew URL: https://patchew.org/QEMU/20200805023826.184-1-fangyi...@huawei.com/
Hi,
This series failed the docker-quick@centos7 build test. Please find the testing
commands and
their output below. If you have Docker installed, you can pro
On 8/6/2020 5:13 PM, Kevin Wolf wrote:
Am 05.08.2020 um 04:38 hat Ying Fang geschrieben:
From: fangying
When qemu or qemu-nbd process uses a qcow2 image and configured with
'cache = none', it will write to the qcow2 image with a cache to cache
L2 tables, however the process will
On 3/1/2021 11:50 PM, Michael S. Tsirkin wrote:
On Mon, Mar 01, 2021 at 10:39:19AM +0100, Andrew Jones wrote:
On Fri, Feb 26, 2021 at 10:23:03AM +0800, Ying Fang wrote:
On 2/25/2021 7:47 PM, Andrew Jones wrote:
On Thu, Feb 25, 2021 at 04:56:26PM +0800, Ying Fang wrote:
Add the processor
On 3/1/2021 5:48 PM, Andrew Jones wrote:
On Fri, Feb 26, 2021 at 04:41:45PM +0800, Ying Fang wrote:
On 2/25/2021 8:02 PM, Andrew Jones wrote:
On Thu, Feb 25, 2021 at 04:56:22PM +0800, Ying Fang wrote:
An accurate cpu topology may help improve the cpu scheduler's decision
making
virtual-topology-for-virtual-machines-friend-or-foe-dario-faggioli-suse
[1] https://lists.gnu.org/archive/html/qemu-devel/2020-11/msg02166.html
[2]
https://patchwork.ozlabs.org/project/qemu-devel/cover/20180704124923.32483-1-drjo...@redhat.com
Ying Fang (5):
device_tree: Add qemu_fdt_add_path
Add the Processor Properties Topology Table (PPTT) to present
CPU topology information to the guest. A three-level cpu
topology is built in accord with the linux kernel currently does.
Tested-by: Jiajie Li
Signed-off-by: Ying Fang
---
hw/arm/virt-acpi-build.c | 50
socket description
(2) build_processor_hierarchy for processor description
(3) build_smt_hierarchy for thread (logic processor) description
Signed-off-by: Ying Fang
Signed-off-by: Henglong Fan
---
hw/acpi/aml-build.c | 40 +
include/hw/acpi/acpi-defs.h
qemu_fdt_add_path() works like qemu_fdt_add_subnode(), except
it also adds any missing parent nodes. We also tweak an error
message of qemu_fdt_add_subnode().
Signed-off-by: Andrew Jones
Signed-off-by: Ying Fang
---
include/sysemu/device_tree.h | 1 +
softmmu/device_tree.c| 45
rework based on Andrew Jones's contribution at
https://lists.gnu.org/archive/html/qemu-arm/2018-07/msg00076.html
Signed-off-by: Ying Fang
---
hw/arm/virt-acpi-build.c | 14 ++
hw/arm/virt.c| 2 ++
2 files changed, 12 insertions(+), 4 deletions(-)
diff --git a/hw/arm
Support device tree CPU topology descriptions.
Signed-off-by: Ying Fang
---
hw/arm/virt.c | 38 +-
include/hw/arm/virt.h | 1 +
2 files changed, 38 insertions(+), 1 deletion(-)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 371147f3ae..c133b342b8
On 2/25/2021 7:03 PM, Andrew Jones wrote:
Hi Ying Fang,
I don't see any change in this patch from what I have in my
tree, so this should be
From: Andrew Jones
Thanks,
drew
Yes, I picked it from your qemu branch:
https://github.com/rhdrjones/qemu/c
On 2/25/2021 7:16 PM, Andrew Jones wrote:
Hi Ying Fang,
The only difference between this and what I have in my tree[*]
is the removal of the socket node (which has been in the Linux
docs since June 2019). Any reason why you removed that node? In
any case, I think I deserve a bit more credit
On 2/25/2021 9:25 PM, Andrew Jones wrote:
On Thu, Feb 25, 2021 at 08:54:40PM +0800, Ying Fang wrote:
On 2/25/2021 7:03 PM, Andrew Jones wrote:
Hi Ying Fang,
I don't see any change in this patch from what I have in my
tree, so this should be
From: Andrew Jones
Thanks,
drew
Y
On 2/25/2021 7:47 PM, Andrew Jones wrote:
On Thu, Feb 25, 2021 at 04:56:26PM +0800, Ying Fang wrote:
Add the processor hierarchy node structures to build ACPI information
for CPU topology. Since the private resources may be used to describe
cache hierarchy and it is variable among different
ACPI differences has been
dropped from the commit message of [*]. I'm not sure why.
Will fix that. I will add SOB of you then you can help to comment on it.
Thanks,
drew
On Thu, Feb 25, 2021 at 04:56:27PM +0800, Ying Fang wrote:
Add the Processor Properties Topology Table (PPTT) to present
CP
On 2/25/2021 8:02 PM, Andrew Jones wrote:
On Thu, Feb 25, 2021 at 04:56:22PM +0800, Ying Fang wrote:
An accurate cpu topology may help improve the cpu scheduler's decision
making when dealing with multi-core system. So cpu topology description
is helpful to provide guest with the right
On 10/14/2020 2:08 AM, Andrew Jones wrote:
On Tue, Oct 13, 2020 at 12:11:20PM +, Zengtao (B) wrote:
Cc valentin
-Original Message-
From: Qemu-devel
[mailto:qemu-devel-bounces+prime.zeng=hisilicon@nongnu.org]
On Behalf Of Ying Fang
Sent: Thursday, September 17, 2020 11:20 AM
On 10/10/2020 10:27 AM, cenjiahui wrote:
Hi Kevin,
Could you please spend some time reviewing and commenting on this patch series.
Thanks,
Jiahui Cen
This feature is confirmed effective in a cloud storage environment since
it can help to improve the availability without pausing the entire
On 10/15/2020 3:59 PM, Andrew Jones wrote:
On Thu, Oct 15, 2020 at 10:07:16AM +0800, Ying Fang wrote:
On 10/14/2020 2:08 AM, Andrew Jones wrote:
On Tue, Oct 13, 2020 at 12:11:20PM +, Zengtao (B) wrote:
Cc valentin
-Original Message-
From: Qemu-devel
[mailto:qemu-devel
On 10/16/2020 6:07 PM, Andrew Jones wrote:
On Fri, Oct 16, 2020 at 05:40:02PM +0800, Ying Fang wrote:
On 10/15/2020 3:59 PM, Andrew Jones wrote:
On Thu, Oct 15, 2020 at 10:07:16AM +0800, Ying Fang wrote:
On 10/14/2020 2:08 AM, Andrew Jones wrote:
On Tue, Oct 13, 2020 at 12:11:20PM
ve unused variable
hw/arm/virt: Replace smp_parse with one that prefers cores
device_tree: Add qemu_fdt_add_path
hw/arm/virt: DT: add cpu-map
Ying Fang (8):
hw: add compat machines for 5.3
hw/arm/virt-acpi-build: distinguish possible and present cpus Message
hw/acpi/aml-build: add proces
From: Andrew Jones
We no longer use the smp_cpus virtual machine state variable.
Remove it.
Signed-off-by: Andrew Jones
---
hw/arm/virt.c | 2 --
include/hw/arm/virt.h | 1 -
2 files changed, 3 deletions(-)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 0069fa1298..ea24b576c6 100644
From: Andrew Jones
Prefer to spell out the smp.cpus and smp.max_cpus machine state
variables in order to make grepping easier and to avoid any
confusion as to what cpu count is being used where.
Signed-off-by: Andrew Jones
---
hw/arm/virt-acpi-build.c | 8 +++
hw/arm/virt.c| 5
Add the CPUCacheInfo structure to hold CPU cache information for ARM cpus.
A classic three level cache topology is used here. The default cache
capacity is given and userspace can overwrite these values.
Signed-off-by: Ying Fang
---
target/arm/cpu.c | 42
Support devicetree CPU cache information descriptions
Signed-off-by: Ying Fang
---
hw/arm/virt.c | 92 +++
1 file changed, 92 insertions(+)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index d23b941020..adcfa52854 100644
--- a/hw/arm/virt.c
+++ b
From: Andrew Jones
Support devicetree CPU topology descriptions.
Signed-off-by: Andrew Jones
Signed-off-by: Ying Fang
---
hw/arm/virt.c | 40 +++-
include/hw/arm/virt.h | 1 +
2 files changed, 40 insertions(+), 1 deletion(-)
diff --git a/hw/arm
) description structure
Signed-off-by: Ying Fang
Signed-off-by: Henglong Fan
---
hw/acpi/aml-build.c | 37 +
include/hw/acpi/aml-build.h | 7 +++
2 files changed, 44 insertions(+)
diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
index
To build cache information, An AcpiCacheInfo structure is defined to
hold the Type 1 cache structure according to ACPI spec v6.3 5.2.29.2.
A helper function build_cache_hierarchy is introduced to encode the
cache information.
Signed-off-by: Ying Fang
---
hw/acpi/aml-build.c | 26
Add the Processor Properties Topology Table (PPTT) to present CPU topology
information to the guest.
Signed-off-by: Andrew Jones
Signed-off-by: Ying Fang
---
hw/arm/virt-acpi-build.c | 42
1 file changed, 42 insertions(+)
diff --git a/hw/arm/virt-acpi
Add 5.2 machine types for arm/i440fx/q35/s390x/spapr.
Signed-off-by: Ying Fang
---
hw/arm/virt.c | 9 -
hw/core/machine.c | 3 +++
hw/i386/pc.c | 3 +++
hw/i386/pc_piix.c | 15 ++-
hw/i386/pc_q35.c | 14
When building ACPI tables regarding CPUs we should always build
them for the number of possible CPUs, not the number of present
CPUs. We then ensure only the present CPUs are enabled.
Signed-off-by: Andrew Jones
Signed-off-by: Ying Fang
---
hw/arm/virt-acpi-build.c | 17 -
1
From: Andrew Jones
The virt machine type has never used the CPU topology parameters, other
than number of online CPUs and max CPUs. When choosing how to allocate
those CPUs the default has been to assume cores. In preparation for
using the other CPU topology parameters let's use an smp_parse that
From: Andrew Jones
qemu_fdt_add_path() works like qemu_fdt_add_subnode(), except
it also adds any missing parent nodes. We also tweak an error
message of qemu_fdt_add_subnode().
We'll make use of the new function in a coming patch.
Signed-off-by: Andrew Jones
---
device_tree.c
A helper struct AcpiCacheOffset is introduced to describe the offset
of three level caches. The cache hierarchy is built according to
ACPI spec v6.3 5.2.29.2. Let's enable CPU cache topology now.
Signed-off-by: Ying Fang
---
hw/acpi/aml-build.c | 19 +-
hw/arm/virt
Kindly ping for it.
Thanks for Stefan's suggestion, we have re-implement the concept by
introducing the 'retry' feature base on the werror=/rerror= mechanism.
Hope this thread won't be missed. Any comments and reviews are wellcome.
Thanks.
Ying Fang.
On 12/15/2020 8:30
smp is the true source for "smp_cpus" and "max_cpus",
avoid passing them in function parameters, preferring instead to get
them from the state.
No functional change intended.
Signed-off-by: Andrew Jones
Reviewed-by: Ying Fang
---
hw/arm/virt-acpi-build.c
Hi Gerd, Daniel.
We noticed that if VncSharePolicy was configured with
VNC_SHARE_POLICY_FORCE_SHARED mode and
multiple vnc clients opened vnc connections, some clients could go blank screen
at high probability.
This problem can be reproduced when we regularly reboot suse12sp3 in graphic
mode bo
his more much likely to happen.
>
> Buglink: https://bugzilla.redhat.com/show_bug.cgi?id=1662260
> Reported-by: Ying Fang
> Signed-off-by: Gerd Hoffmann
Reviewed-by: Ying Fang
> ---
> ui/vnc.c | 6 ++
> 1 file changed, 6 insertions(+)
>
> diff --git a/ui/vnc.c b/ui/vnc.c
&
)
Cc: zhanghailiang
Signed-off-by: Ying Fang
---
hw/usb/hcd-xhci.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/usb/hcd-xhci.c b/hw/usb/hcd-xhci.c
index f578264948..471759cd4c 100644
--- a/hw/usb/hcd-xhci.c
+++ b/hw/usb/hcd-xhci.c
@@ -2161,6 +2161,7 @@ static TRBCCode xhci_address_slot
0xdfd278d7 in os_host_main_loop_wait util/main-loop.c:241
#20 0xdfd278d7 in main_loop_wait util/main-loop.c:517
#21 0xdf67b5e7 in main_loop vl.c:1806
#22 0xdf15d453 in main vl.c:4488
Cc: zhanghailiang
Signed-off-by: Ying Fang
---
migration/migration.c | 6 ++
1 file
0xdfd278d7 in os_host_main_loop_wait util/main-loop.c:241
#20 0xdfd278d7 in main_loop_wait util/main-loop.c:517
#21 0xdf67b5e7 in main_loop vl.c:1806
#22 0xdf15d453 in main vl.c:4488
Cc: zhanghailiang
Signed-off-by: Ying Fang
---
migration/migration.c | 2 ++
1 file
qemu_clock_run_all_timers util/qemu-timer.c:692
#10 0xbbdab9a3 in main_loop_wait util/main-loop.c:524
#11 0xbb6ff5e7 in main_loop vl.c:1806
#12 0xbb1e1453 in main vl.c:4488
Signed-off-by: Ying Fang
---
hw/usb/hcd-xhci.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw
On 2020/4/7 22:07, Paolo Bonzini wrote:
ARM machines and other weakly-ordered architectures have been suffering
for a long time from hangs in qemu-img and qemu-io. For QEMU binaries
these are mitigated by the timers that sooner or later fire in the main
loop, but these will not happen for the
and therefore it is even weaker than C11 ATOMIC_RELAXED;
on x86, ATOMIC_RELAXED compiles to a locked operation.
Analyzed-by: Ying Fang
Signed-off-by: Paolo Bonzini
---
util/aio-posix.c | 16 ++--
util/aio-win32.c | 17 ++---
util/async.c | 16 --
On 2020/4/8 23:05, Paolo Bonzini wrote:
On 08/04/20 11:12, Ying Fang wrote:
On 2020/4/7 22:07, Paolo Bonzini wrote:
ARM machines and other weakly-ordered architectures have been suffering
for a long time from hangs in qemu-img and qemu-io. For QEMU binaries
these are mitigated by the
On 2020/6/1 20:29, Andrew Jones wrote:
On Mon, Jun 01, 2020 at 08:07:31PM +0800, Ying Fang wrote:
On 2020/6/1 16:07, Andrew Jones wrote:
On Sat, May 30, 2020 at 04:56:26PM +0800, Ying Fang wrote:
About the kvm-no-adjvtime CPU property
Hi Andrew,
To adjust virutal time, a new kvm cpu
On 2020/6/1 20:41, Peter Maydell wrote:
On Sat, 30 May 2020 at 10:22, Ying Fang wrote:
Virtual time adjustment was implemented for virt-5.0 machine type,
but the cpu property was enabled only for host-passthrough and
max cpu model. Let's add it for arm cortex series cpu which ha
Virtual time adjustment was implemented for virt-5.0 machine type,
but the cpu property was enabled only for host-passthrough and
max cpu model. Let's add it for arm cpu which has the gernic
timer feature enabled.
Signed-off-by: Ying Fang
---
v2:
- move kvm_arm_add_vcpu_properties
On 6/3/2020 4:26 PM, Andrew Jones wrote:
On Wed, Jun 03, 2020 at 10:02:08AM +0800, Ying Fang wrote:
Virtual time adjustment was implemented for virt-5.0 machine type,
but the cpu property was enabled only for host-passthrough and
max cpu model. Let's add it for arm cpu which has the g
Hi Richard,
Recently we are doing some tests on forward migration based on
arm virt machine. And we found the patch below breaks forward
migration compatibility from virt-4.2 to virt-5.0 above machine
type. The patch which breaks this down given by git bisect is
commit f9506e162c33e87b609549157d
On 6/3/2020 4:53 PM, Andrew Jones wrote:
On Tue, Jun 02, 2020 at 03:47:22PM +0800, Ying Fang wrote:
On 2020/6/1 20:29, Andrew Jones wrote:
On Mon, Jun 01, 2020 at 08:07:31PM +0800, Ying Fang wrote:
On 2020/6/1 16:07, Andrew Jones wrote:
On Sat, May 30, 2020 at 04:56:26PM +0800, Ying
ping
On 6/4/2020 4:51 PM, Ying Fang wrote:
Hi Richard,
Recently we are doing some tests on forward migration based on
arm virt machine. And we found the patch below breaks forward
migration compatibility from virt-4.2 to virt-5.0 above machine
type. The patch which breaks this down given by
From: fangying
Virtual time adjustment was implemented for virt-5.0 machine type,
but the cpu property was enabled only for host-passthrough and
max cpu model. Let's add it for arm cpu which has the generic timer
feature enabled.
Suggested-by: Andrew Jones
Signed-off-by: Ying Fang
-
On 6/8/2020 8:49 PM, Andrew Jones wrote:
On Mon, Jun 08, 2020 at 08:12:43PM +0800, Ying Fang wrote:
From: fangying
Virtual time adjustment was implemented for virt-5.0 machine type,
but the cpu property was enabled only for host-passthrough and
max cpu model. Let's add it for arm cpu
About the kvm-no-adjvtime CPU property
Hi Andrew,
To adjust virutal time, a new kvm cpu property kvm-no-adjvtime
was introduced to 5.0 virt machine types. However the cpu
property was enabled only for host-passthrough and max cpu model.
As for other cpu model like cortex-a57, cortex-a53, cortex-a
Virtual time adjustment was implemented for virt-5.0 machine type,
but the cpu property was enabled only for host-passthrough and
max cpu model. Let's add it for arm cortex series cpu which has
the gernic timer feature enabled.
Signed-off-by: Ying Fang
diff --git a/target/arm/cpu.c b/targe
On 2020/6/1 16:07, Andrew Jones wrote:
On Sat, May 30, 2020 at 04:56:26PM +0800, Ying Fang wrote:
About the kvm-no-adjvtime CPU property
Hi Andrew,
To adjust virutal time, a new kvm cpu property kvm-no-adjvtime
was introduced to 5.0 virt machine types. However the cpu
property was enabled
On 11/30/2020 9:00 PM, Peter Maydell wrote:
On Mon, 9 Nov 2020 at 03:05, Ying Fang wrote:
Add the CPUCacheInfo structure to hold cpu cache information for ARM cpus.
A classic three level cache topology is used here. The default cache
capacity is given and userspace can overwrite these
To disable I/O hang, all hanging AIOs need to be drained. A rehandle status
field is introduced to notify rehandle mechanism not to rehandle failed AIOs
when I/O hang is disabled.
Signed-off-by: Ying Fang
Signed-off-by: Jiahui Cen
---
block/block-backend.c | 85
I/O hang timeout should be different under different situations. So it is
better to provide an option for user to determine I/O hang timeout for
each block device.
Signed-off-by: Jiahui Cen
Signed-off-by: Ying Fang
---
blockdev.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a
nning smoothly when I/O is recovred with this feature enabled.
Ying Fang (7):
block-backend: introduce I/O rehandle info
block-backend: rehandle block aios when EIO
block-backend: add I/O hang timeout
block-backend: add I/O hang drain when disbale
virtio-blk: disable I/O hang when rese
Not all errors would be fixed, so it is better to add a rehandle timeout
for I/O hang.
Signed-off-by: Jiahui Cen
Signed-off-by: Ying Fang
---
block/block-backend.c | 99 +-
include/sysemu/block-backend.h | 2 +
2 files changed, 100 insertions(+), 1
-off-by: Ying Fang
---
block/block-backend.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/block/block-backend.c b/block/block-backend.c
index 24dd0670d1..bf104a7cf5 100644
--- a/block/block-backend.c
+++ b/block/block-backend.c
@@ -35,6 +35,18 @@
static AioContext
All AIOs including the hanging AIOs need to be drained when resetting
virtio-blk. So it is necessary to disable I/O hang before resetting
and enable I/O hang again after resetting if I/O hang is enabled.
Signed-off-by: Ying Fang
Signed-off-by: Jiahui Cen
---
hw/block/virtio-blk.c | 8
situations,
the returned error is often an EIO.
To avoid this unavailablity, we can store the failed AIOs, and resend them
later. If the error is temporary, the retries can succeed and the AIOs can
be successfully completed.
Signed-off-by: Ying Fang
Signed-off-by: Jiahui Cen
---
block/block
Sometimes hypervisor management tools like libvirt may need to monitor
I/O hang events. Let's report I/O hang and I/O hang timeout event via qapi.
Signed-off-by: Jiahui Cen
Signed-off-by: Ying Fang
---
block/block-backend.c | 3 +++
qapi/block-core.json | 26
MPIDR helps to provide an additional PE identification in a multiprocessor
system. This patch adds support for setting MPIDR from userspace, so that
MPIDR is consistent with CPU topology configured.
Signed-off-by: Ying Fang
---
target/arm/kvm64.c | 46
MPIDR helps to provide an additional PE identification in a multiprocessor
system. This patch adds support for setting MPIDR from userspace, so that
MPIDR is consistent with CPU topology configured.
Signed-off-by: Ying Fang
---
target/arm/kvm32.c | 46
From: Andrew Jones
qemu_fdt_add_path works like qemu_fdt_add_subnode, except it
also recursively adds any missing parent nodes.
Cc: Peter Crosthwaite
Cc: Alexander Graf
Signed-off-by: Andrew Jones
---
device_tree.c| 24
include/sysemu/device_tree.h |
From: Andrew Jones
Support devicetree CPU topology descriptions.
Signed-off-by: Andrew Jones
---
hw/arm/virt.c | 37 -
include/hw/arm/virt.h | 1 +
2 files changed, 37 insertions(+), 1 deletion(-)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index ac
Signed-off-by: Ying Fang
---
linux-headers/linux/kvm.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h
index a28c366737..461a2302e7 100644
--- a/linux-headers/linux/kvm.h
+++ b/linux-headers/linux/kvm.h
@@ -1031,6 +1031,7 @@ struct
Add the CPUCacheInfo structure to hold CPU cache information for ARM cpus.
A classic three level cache topology is used here. The default cache
capacity is given and userspace can overwrite these values.
Signed-off-by: Ying Fang
---
target/arm/cpu.c | 42
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