I'm going to close this bug as it seems like the issue that RTOS Pharos
raised is not an issue.
@Teodori Serge please open a new issue if you have a bug. Make sure to
include as much detail as possible and steps to reproduce it.
** Changed in: qemu
Status: New => Invalid
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You received
Hello as far as I can tell, there is a major problem with PLIC
implementation. When decompiling DTB on virt board with X harts, I see
that hartid 0 has MEI and SEI, hartid 1 has MEI and SEI, etc... But when
configuring context 1 (hartid 0 SEI) no interrupt is generated, but
context 0, 2, 4 etc... w
Thank you for the explanation. I actually built it for "Virt" machine.
I'll try the "sifive_u" when I can.
But I guess your explanation is correct so this bug could be closed from
my part.
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On Tue, Mar 24, 2020 at 4:20 PM RTOS Pharos <1815...@bugs.launchpad.net> wrote:
>
> Hi,
>
> After some debugging (and luck), the problem (at least in the Virt
> board) was that the PLIC code inside QEMU addresses the core x 2 instead
> of just the core (core=hart). That is why it worked for core 0
Hi,
After some debugging (and luck), the problem (at least in the Virt
board) was that the PLIC code inside QEMU addresses the core x 2 instead
of just the core (core=hart). That is why it worked for core 0 (0x2 = 0)
but for core 1 it has to address the PLIC memory area for core 2.
For example, t
