Re: [PATCH] target/arm: add PMU feature to cortex-r5 and cortex-r5f

[Peter Maydell]

On Tue, 14 Jan 2020 at 12:44, Philippe Mathieu-Daudé  wrote:
>
> On 1/14/20 11:59 AM, Clement Deschamps wrote:
>
> Maybe describe here:
>
> The PMU is not optional on cortex-r5 and cortex-r5f (see
> the "Features" chapter of the Technical Reference Manual).
>
> > Signed-off-by: Clement Deschamps 
>
> Reviewed-by: Philippe Mathieu-Daudé 



Applied to target-arm.next, thanks (with the suggested
improvement to the commit message).

-- PMM

Re: [PATCH] target/arm: add PMU feature to cortex-r5 and cortex-r5f

[Philippe Mathieu-Daudé]

On 1/14/20 11:59 AM, Clement Deschamps wrote:

Maybe describe here:

The PMU is not optional on cortex-r5 and cortex-r5f (see
the "Features" chapter of the Technical Reference Manual).


Signed-off-by: Clement Deschamps 


Reviewed-by: Philippe Mathieu-Daudé 


---
See cortex-r5 TRM - 1.3 Features

PMU is not optional on cortex-r5 and cortex-r5f
---
  target/arm/cpu.c | 1 +
  1 file changed, 1 insertion(+)

diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index d62fd5fdc6..64cd0a7d73 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2121,6 +2121,7 @@ static void cortex_r5_initfn(Object *obj)
  set_feature(>env, ARM_FEATURE_V7);
  set_feature(>env, ARM_FEATURE_V7MP);
  set_feature(>env, ARM_FEATURE_PMSA);
+set_feature(>env, ARM_FEATURE_PMU);
  cpu->midr = 0x411fc153; /* r1p3 */
  cpu->id_pfr0 = 0x0131;
  cpu->id_pfr1 = 0x001;

[PATCH] target/arm: add PMU feature to cortex-r5 and cortex-r5f

[Clement Deschamps]

Signed-off-by: Clement Deschamps 
---
See cortex-r5 TRM - 1.3 Features

PMU is not optional on cortex-r5 and cortex-r5f
---
 target/arm/cpu.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index d62fd5fdc6..64cd0a7d73 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2121,6 +2121,7 @@ static void cortex_r5_initfn(Object *obj)
 set_feature(>env, ARM_FEATURE_V7);
 set_feature(>env, ARM_FEATURE_V7MP);
 set_feature(>env, ARM_FEATURE_PMSA);
+set_feature(>env, ARM_FEATURE_PMU);
 cpu->midr = 0x411fc153; /* r1p3 */
 cpu->id_pfr0 = 0x0131;
 cpu->id_pfr1 = 0x001;
-- 
2.24.1