Re: [PATCH 02/19] target/arm: Rename isar_feature_aa32_simd_r32

2020-02-21 Thread Peter Maydell 
On Fri, 14 Feb 2020 at 18:15, Richard Henderson
 wrote:
>
> The old name, isar_feature_aa32_fp_d32, does not reflect
> the MVFR0 field name, SIMDReg.
>
> Signed-off-by: Richard Henderson 
> ---

Reviewed-by: Peter Maydell 

Can you wrap the long line checkpatch complains about, please?

thanks
-- PMM

Re: [PATCH 02/19] target/arm: Rename isar_feature_aa32_simd_r32

2020-02-14 Thread Philippe Mathieu-Daudé 

On 2/14/20 7:15 PM, Richard Henderson wrote:

The old name, isar_feature_aa32_fp_d32, does not reflect
the MVFR0 field name, SIMDReg.

Signed-off-by: Richard Henderson 
---
  target/arm/cpu.h   |  2 +-
  target/arm/translate-vfp.inc.c | 52 +-
  2 files changed, 27 insertions(+), 27 deletions(-)


Reviewed-by: Philippe Mathieu-Daudé

[PATCH 02/19] target/arm: Rename isar_feature_aa32_simd_r32

2020-02-14 Thread Richard Henderson 
The old name, isar_feature_aa32_fp_d32, does not reflect
the MVFR0 field name, SIMDReg.

Signed-off-by: Richard Henderson 
---
 target/arm/cpu.h   |  2 +-
 target/arm/translate-vfp.inc.c | 52 +-
 2 files changed, 27 insertions(+), 27 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 28cb2be6fc..f7139db02d 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3412,7 +3412,7 @@ static inline bool isar_feature_aa32_fp16_arith(const 
ARMISARegisters *id)
 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1;
 }
 
-static inline bool isar_feature_aa32_fp_d32(const ARMISARegisters *id)
+static inline bool isar_feature_aa32_simd_r32(const ARMISARegisters *id)
 {
 /* Return true if D16-D31 are implemented */
 return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) >= 2;
diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c
index bf90ac0e5b..96a1d727c6 100644
--- a/target/arm/translate-vfp.inc.c
+++ b/target/arm/translate-vfp.inc.c
@@ -201,7 +201,7 @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a)
 }
 
 /* UNDEF accesses to D16-D31 if they don't exist */
-if (dp && !dc_isar_feature(aa32_fp_d32, s) &&
+if (dp && !dc_isar_feature(aa32_simd_r32, s) &&
 ((a->vm | a->vn | a->vd) & 0x10)) {
 return false;
 }
@@ -334,7 +334,7 @@ static bool trans_VMINMAXNM(DisasContext *s, arg_VMINMAXNM 
*a)
 }
 
 /* UNDEF accesses to D16-D31 if they don't exist */
-if (dp && !dc_isar_feature(aa32_fp_d32, s) &&
+if (dp && !dc_isar_feature(aa32_simd_r32, s) &&
 ((a->vm | a->vn | a->vd) & 0x10)) {
 return false;
 }
@@ -420,7 +420,7 @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a)
 }
 
 /* UNDEF accesses to D16-D31 if they don't exist */
-if (dp && !dc_isar_feature(aa32_fp_d32, s) &&
+if (dp && !dc_isar_feature(aa32_simd_r32, s) &&
 ((a->vm | a->vd) & 0x10)) {
 return false;
 }
@@ -484,7 +484,7 @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a)
 }
 
 /* UNDEF accesses to D16-D31 if they don't exist */
-if (dp && !dc_isar_feature(aa32_fp_d32, s) && (a->vm & 0x10)) {
+if (dp && !dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) {
 return false;
 }
 
@@ -556,7 +556,7 @@ static bool trans_VMOV_to_gp(DisasContext *s, 
arg_VMOV_to_gp *a)
 uint32_t offset;
 
 /* UNDEF accesses to D16-D31 if they don't exist */
-if (!dc_isar_feature(aa32_fp_d32, s) && (a->vn & 0x10)) {
+if (!dc_isar_feature(aa32_simd_r32, s) && (a->vn & 0x10)) {
 return false;
 }
 
@@ -615,7 +615,7 @@ static bool trans_VMOV_from_gp(DisasContext *s, 
arg_VMOV_from_gp *a)
 uint32_t offset;
 
 /* UNDEF accesses to D16-D31 if they don't exist */
-if (!dc_isar_feature(aa32_fp_d32, s) && (a->vn & 0x10)) {
+if (!dc_isar_feature(aa32_simd_r32, s) && (a->vn & 0x10)) {
 return false;
 }
 
@@ -662,7 +662,7 @@ static bool trans_VDUP(DisasContext *s, arg_VDUP *a)
 }
 
 /* UNDEF accesses to D16-D31 if they don't exist */
-if (!dc_isar_feature(aa32_fp_d32, s) && (a->vn & 0x10)) {
+if (!dc_isar_feature(aa32_simd_r32, s) && (a->vn & 0x10)) {
 return false;
 }
 
@@ -912,7 +912,7 @@ static bool trans_VMOV_64_dp(DisasContext *s, 
arg_VMOV_64_dp *a)
  */
 
 /* UNDEF accesses to D16-D31 if they don't exist */
-if (!dc_isar_feature(aa32_fp_d32, s) && (a->vm & 0x10)) {
+if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) {
 return false;
 }
 
@@ -978,7 +978,7 @@ static bool trans_VLDR_VSTR_dp(DisasContext *s, 
arg_VLDR_VSTR_dp *a)
 TCGv_i64 tmp;
 
 /* UNDEF accesses to D16-D31 if they don't exist */
-if (!dc_isar_feature(aa32_fp_d32, s) && (a->vd & 0x10)) {
+if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) {
 return false;
 }
 
@@ -1101,7 +1101,7 @@ static bool trans_VLDM_VSTM_dp(DisasContext *s, 
arg_VLDM_VSTM_dp *a)
 }
 
 /* UNDEF accesses to D16-D31 if they don't exist */
-if (!dc_isar_feature(aa32_fp_d32, s) && (a->vd + n) > 16) {
+if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd + n) > 16) {
 return false;
 }
 
@@ -1309,7 +1309,7 @@ static bool do_vfp_3op_dp(DisasContext *s, VFPGen3OpDPFn 
*fn,
 TCGv_ptr fpst;
 
 /* UNDEF accesses to D16-D31 if they don't exist */
-if (!dc_isar_feature(aa32_fp_d32, s) && ((vd | vn | vm) & 0x10)) {
+if (!dc_isar_feature(aa32_simd_r32, s) && ((vd | vn | vm) & 0x10)) {
 return false;
 }
 
@@ -1458,7 +1458,7 @@ static bool do_vfp_2op_dp(DisasContext *s, VFPGen2OpDPFn 
*fn, int vd, int vm)
 TCGv_i64 f0, fd;
 
 /* UNDEF accesses to D16-D31 if they don't exist */
-if (!dc_isar_feature(aa32_fp_d32, s) && ((vd | vm) & 0x10)) {
+if (!dc_isar_feature(aa32_simd_r32, s) && ((vd | vm) & 0x10)) {
 return false;
 }
 
@@ -1822,7 +1822,7 @@ static bool trans_VFM_dp(DisasContext *s, arg_VFM_dp *a)
 }