subject:"\[PATCH 2\/5\] ppc\/pnv\: Add support for NMI interface"

Re: [PATCH 2/5] ppc/pnv: Add support for NMI interface

2020-04-03 Thread Nicholas Piggin

Cédric Le Goater's on April 4, 2020 1:47 am:
> On 4/3/20 3:12 PM, Nicholas Piggin wrote:
>> Nicholas Piggin's on April 3, 2020 5:57 pm:
>>> Cédric Le Goater's on March 26, 2020 2:38 am:
 [ Please use c...@kaod.org ! ]

 On 3/25/20 3:41 PM, Nicholas Piggin wrote:
> This implements the NMI interface for the PNV machine, similarly to
> commit 3431648272d ("spapr: Add support for new NMI interface") for
> SPAPR.
>
> Signed-off-by: Nicholas Piggin 

 one minor comment,

 Reviewed-by: Cédric Le Goater 

> ---
>  hw/ppc/pnv.c | 30 +-
>  1 file changed, 29 insertions(+), 1 deletion(-)
>
> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
> index b75ad06390..671535ebe6 100644
> --- a/hw/ppc/pnv.c
> +++ b/hw/ppc/pnv.c
> @@ -27,6 +27,7 @@
>  #include "sysemu/runstate.h"
>  #include "sysemu/cpus.h"
>  #include "sysemu/device_tree.h"
> +#include "sysemu/hw_accel.h"
>  #include "target/ppc/cpu.h"
>  #include "qemu/log.h"
>  #include "hw/ppc/fdt.h"
> @@ -34,6 +35,7 @@
>  #include "hw/ppc/pnv.h"
>  #include "hw/ppc/pnv_core.h"
>  #include "hw/loader.h"
> +#include "hw/nmi.h"
>  #include "exec/address-spaces.h"
>  #include "qapi/visitor.h"
>  #include "monitor/monitor.h"
> @@ -1955,10 +1957,35 @@ static void pnv_machine_set_hb(Object *obj, bool 
> value, Error **errp)
>  }
>  }
>
> +static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg)
> +{
> +PowerPCCPU *cpu = POWERPC_CPU(cs);
> +CPUPPCState *env = &cpu->env;
> +
> +cpu_synchronize_state(cs);
> +ppc_cpu_do_system_reset(cs);
> +/*
> + * SRR1[42:45] is set to 0100 which the ISA defines as implementation

 I see 'System Reset' in ISA 3.0
> + * dependent. POWER processors use this for xscom triggered 
> interrupts,
> + * which come from the BMC or NMI IPIs.
> + */
> +env->spr[SPR_SRR1] |= PPC_BIT(43);

 So we could have used the skiboot SPR_SRR1_PM_WAKE_SRESET define ? 
>>>
>>> Ah, that's only for power-saving wakeup. But you got me to dig further
>>> and I think I've got a few things wrong here.
>>>
>>> The architectural power save wakeup due to sreset bit 43 needs to be
>>> set, probably in excp_helper.c if (msr_pow) test.
>>>
>>> case POWERPC_EXCP_RESET: /* System reset exception  
>>>  */
>>> /* A power-saving exception sets ME, otherwise it is unchanged */
>>> if (msr_pow) {
>>> /* indicate that we resumed from power save mode */
>>> msr |= 0x1;
>>> new_msr |= ((target_ulong)1 << MSR_ME);
>>> }
>> 
>> Sorry I'm wrong, that's the old MSR_POW thing I guess G5 had it.
>> 
>> 'stop' state wakeup is powerpc_reset_wakeup of course, which seems to
>> do the right thing with SRR1.
>> 
>> Something like this patch should fix this issue in the ppc-5.1 branch.
>> This appears to do the right thing with SRR1 in testing with Linux.
>> 
>> ---
>>  hw/ppc/pnv.c | 21 +++--
>>  1 file changed, 15 insertions(+), 6 deletions(-)
>> 
>> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
>> index ac83b8698b..596ccfd99e 100644
>> --- a/hw/ppc/pnv.c
>> +++ b/hw/ppc/pnv.c
>> @@ -1964,12 +1964,21 @@ static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, 
>> run_on_cpu_data arg)
>>  
>>  cpu_synchronize_state(cs);
>>  ppc_cpu_do_system_reset(cs);
>> -/*
>> - * SRR1[42:45] is set to 0100 which the ISA defines as implementation
>> - * dependent. POWER processors use this for xscom triggered interrupts,
>> - * which come from the BMC or NMI IPIs.
>> - */
>> -env->spr[SPR_SRR1] |= PPC_BIT(43);
>> +if (env->spr[SPR_SRR1] & PPC_BITMASK(46, 47)) {
>> +/* system reset caused wake from power saving state */
>> +if (!(env->spr[SPR_SRR1] & PPC_BIT(43))) {
>> +warn_report("ppc_cpu_do_system_reset does not set system reset 
>> wakeup reason");
>> +env->spr[SPR_SRR1] |= PPC_BIT(43);
>> +}
>> +} else {
>> +/*
>> + * For non-powersave wakeup system resets, SRR1[42:45] are defined to
>> + * be implementation dependent. Set to 0b0010, which POWER9 UM defines
>> + * to be interrupt caused by SCOM, which can come from the BMC or NMI
>> + * IPIs.
>> + */
>> +env->spr[SPR_SRR1] |= PPC_BIT(44);
>> +}
>>  }
> 
> That looks correct according to the UM.
> 
> Do we care about the other non-powersave wakeup system resets ? 
> 
>   0011 Interrupt caused by hypervisor door bell.
>   0101 Interrupt caused by privileged door bell.

I think that's a typo in the UM, and those are powersave ones.

> 
> The reason is that I sometime see CPU lockups under load, or with a KVM 
> guest, 
> and I haven't found why yet.

I can't tell what's going on there, does it keep taking e80 interrupts
and never clear the

Re: [PATCH 2/5] ppc/pnv: Add support for NMI interface

2020-04-03 Thread Cédric Le Goater

On 4/3/20 3:12 PM, Nicholas Piggin wrote:
> Nicholas Piggin's on April 3, 2020 5:57 pm:
>> Cédric Le Goater's on March 26, 2020 2:38 am:
>>> [ Please use c...@kaod.org ! ]
>>>
>>> On 3/25/20 3:41 PM, Nicholas Piggin wrote:
 This implements the NMI interface for the PNV machine, similarly to
 commit 3431648272d ("spapr: Add support for new NMI interface") for
 SPAPR.

 Signed-off-by: Nicholas Piggin 
>>>
>>> one minor comment,
>>>
>>> Reviewed-by: Cédric Le Goater 
>>>
 ---
  hw/ppc/pnv.c | 30 +-
  1 file changed, 29 insertions(+), 1 deletion(-)

 diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
 index b75ad06390..671535ebe6 100644
 --- a/hw/ppc/pnv.c
 +++ b/hw/ppc/pnv.c
 @@ -27,6 +27,7 @@
  #include "sysemu/runstate.h"
  #include "sysemu/cpus.h"
  #include "sysemu/device_tree.h"
 +#include "sysemu/hw_accel.h"
  #include "target/ppc/cpu.h"
  #include "qemu/log.h"
  #include "hw/ppc/fdt.h"
 @@ -34,6 +35,7 @@
  #include "hw/ppc/pnv.h"
  #include "hw/ppc/pnv_core.h"
  #include "hw/loader.h"
 +#include "hw/nmi.h"
  #include "exec/address-spaces.h"
  #include "qapi/visitor.h"
  #include "monitor/monitor.h"
 @@ -1955,10 +1957,35 @@ static void pnv_machine_set_hb(Object *obj, bool 
 value, Error **errp)
  }
  }

 +static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg)
 +{
 +PowerPCCPU *cpu = POWERPC_CPU(cs);
 +CPUPPCState *env = &cpu->env;
 +
 +cpu_synchronize_state(cs);
 +ppc_cpu_do_system_reset(cs);
 +/*
 + * SRR1[42:45] is set to 0100 which the ISA defines as implementation
>>>
>>> I see 'System Reset' in ISA 3.0
 + * dependent. POWER processors use this for xscom triggered 
 interrupts,
 + * which come from the BMC or NMI IPIs.
 + */
 +env->spr[SPR_SRR1] |= PPC_BIT(43);
>>>
>>> So we could have used the skiboot SPR_SRR1_PM_WAKE_SRESET define ? 
>>
>> Ah, that's only for power-saving wakeup. But you got me to dig further
>> and I think I've got a few things wrong here.
>>
>> The architectural power save wakeup due to sreset bit 43 needs to be
>> set, probably in excp_helper.c if (msr_pow) test.
>>
>> case POWERPC_EXCP_RESET: /* System reset exception   
>> */
>> /* A power-saving exception sets ME, otherwise it is unchanged */
>> if (msr_pow) {
>> /* indicate that we resumed from power save mode */
>> msr |= 0x1;
>> new_msr |= ((target_ulong)1 << MSR_ME);
>> }
> 
> Sorry I'm wrong, that's the old MSR_POW thing I guess G5 had it.
> 
> 'stop' state wakeup is powerpc_reset_wakeup of course, which seems to
> do the right thing with SRR1.
> 
> Something like this patch should fix this issue in the ppc-5.1 branch.
> This appears to do the right thing with SRR1 in testing with Linux.
> 
> ---
>  hw/ppc/pnv.c | 21 +++--
>  1 file changed, 15 insertions(+), 6 deletions(-)
> 
> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
> index ac83b8698b..596ccfd99e 100644
> --- a/hw/ppc/pnv.c
> +++ b/hw/ppc/pnv.c
> @@ -1964,12 +1964,21 @@ static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, 
> run_on_cpu_data arg)
>  
>  cpu_synchronize_state(cs);
>  ppc_cpu_do_system_reset(cs);
> -/*
> - * SRR1[42:45] is set to 0100 which the ISA defines as implementation
> - * dependent. POWER processors use this for xscom triggered interrupts,
> - * which come from the BMC or NMI IPIs.
> - */
> -env->spr[SPR_SRR1] |= PPC_BIT(43);
> +if (env->spr[SPR_SRR1] & PPC_BITMASK(46, 47)) {
> +/* system reset caused wake from power saving state */
> +if (!(env->spr[SPR_SRR1] & PPC_BIT(43))) {
> +warn_report("ppc_cpu_do_system_reset does not set system reset 
> wakeup reason");
> +env->spr[SPR_SRR1] |= PPC_BIT(43);
> +}
> +} else {
> +/*
> +  * For non-powersave wakeup system resets, SRR1[42:45] are defined to
> +  * be implementation dependent. Set to 0b0010, which POWER9 UM defines
> +  * to be interrupt caused by SCOM, which can come from the BMC or NMI
> +  * IPIs.
> + */
> +env->spr[SPR_SRR1] |= PPC_BIT(44);
> +}
>  }

That looks correct according to the UM.

Do we care about the other non-powersave wakeup system resets ? 

  0011 Interrupt caused by hypervisor door bell.
  0101 Interrupt caused by privileged door bell.

The reason is that I sometime see CPU lockups under load, or with a KVM guest, 
and I haven't found why yet.

Thanks,


C. 


[  259.069436] virbr0: port 2(tap0) entered forwarding state
[  259.069523] virbr0: topology change detected, propagating
[  384.427337] watchdog: CPU 1 detected hard LOCKUP on other CPUs 0
[  384.428566] watchdog: CPU 1 TB:255514422948, last SMP heartbeat 
TB:246648941120 (17315ms ago)
[  384.528958] watchdog: CPU 0 Hard LOCK

Re: [PATCH 2/5] ppc/pnv: Add support for NMI interface

2020-04-03 Thread Nicholas Piggin

Nicholas Piggin's on April 3, 2020 5:57 pm:
> Cédric Le Goater's on March 26, 2020 2:38 am:
>> [ Please use c...@kaod.org ! ]
>> 
>> On 3/25/20 3:41 PM, Nicholas Piggin wrote:
>>> This implements the NMI interface for the PNV machine, similarly to
>>> commit 3431648272d ("spapr: Add support for new NMI interface") for
>>> SPAPR.
>>> 
>>> Signed-off-by: Nicholas Piggin 
>> 
>> one minor comment,
>> 
>> Reviewed-by: Cédric Le Goater 
>> 
>>> ---
>>>  hw/ppc/pnv.c | 30 +-
>>>  1 file changed, 29 insertions(+), 1 deletion(-)
>>> 
>>> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
>>> index b75ad06390..671535ebe6 100644
>>> --- a/hw/ppc/pnv.c
>>> +++ b/hw/ppc/pnv.c
>>> @@ -27,6 +27,7 @@
>>>  #include "sysemu/runstate.h"
>>>  #include "sysemu/cpus.h"
>>>  #include "sysemu/device_tree.h"
>>> +#include "sysemu/hw_accel.h"
>>>  #include "target/ppc/cpu.h"
>>>  #include "qemu/log.h"
>>>  #include "hw/ppc/fdt.h"
>>> @@ -34,6 +35,7 @@
>>>  #include "hw/ppc/pnv.h"
>>>  #include "hw/ppc/pnv_core.h"
>>>  #include "hw/loader.h"
>>> +#include "hw/nmi.h"
>>>  #include "exec/address-spaces.h"
>>>  #include "qapi/visitor.h"
>>>  #include "monitor/monitor.h"
>>> @@ -1955,10 +1957,35 @@ static void pnv_machine_set_hb(Object *obj, bool 
>>> value, Error **errp)
>>>  }
>>>  }
>>> 
>>> +static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg)
>>> +{
>>> +PowerPCCPU *cpu = POWERPC_CPU(cs);
>>> +CPUPPCState *env = &cpu->env;
>>> +
>>> +cpu_synchronize_state(cs);
>>> +ppc_cpu_do_system_reset(cs);
>>> +/*
>>> + * SRR1[42:45] is set to 0100 which the ISA defines as implementation
>> 
>> I see 'System Reset' in ISA 3.0
>>> + * dependent. POWER processors use this for xscom triggered interrupts,
>>> + * which come from the BMC or NMI IPIs.
>>> + */
>>> +env->spr[SPR_SRR1] |= PPC_BIT(43);
>> 
>> So we could have used the skiboot SPR_SRR1_PM_WAKE_SRESET define ? 
> 
> Ah, that's only for power-saving wakeup. But you got me to dig further
> and I think I've got a few things wrong here.
> 
> The architectural power save wakeup due to sreset bit 43 needs to be
> set, probably in excp_helper.c if (msr_pow) test.
> 
> case POWERPC_EXCP_RESET: /* System reset exception   
> */
> /* A power-saving exception sets ME, otherwise it is unchanged */
> if (msr_pow) {
> /* indicate that we resumed from power save mode */
> msr |= 0x1;
> new_msr |= ((target_ulong)1 << MSR_ME);
> }

Sorry I'm wrong, that's the old MSR_POW thing I guess G5 had it.

'stop' state wakeup is powerpc_reset_wakeup of course, which seems to
do the right thing with SRR1.

Something like this patch should fix this issue in the ppc-5.1 branch.
This appears to do the right thing with SRR1 in testing with Linux.

---
 hw/ppc/pnv.c | 21 +++--
 1 file changed, 15 insertions(+), 6 deletions(-)

diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index ac83b8698b..596ccfd99e 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -1964,12 +1964,21 @@ static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, 
run_on_cpu_data arg)
 
 cpu_synchronize_state(cs);
 ppc_cpu_do_system_reset(cs);
-/*
- * SRR1[42:45] is set to 0100 which the ISA defines as implementation
- * dependent. POWER processors use this for xscom triggered interrupts,
- * which come from the BMC or NMI IPIs.
- */
-env->spr[SPR_SRR1] |= PPC_BIT(43);
+if (env->spr[SPR_SRR1] & PPC_BITMASK(46, 47)) {
+/* system reset caused wake from power saving state */
+if (!(env->spr[SPR_SRR1] & PPC_BIT(43))) {
+warn_report("ppc_cpu_do_system_reset does not set system reset 
wakeup reason");
+env->spr[SPR_SRR1] |= PPC_BIT(43);
+}
+} else {
+/*
+* For non-powersave wakeup system resets, SRR1[42:45] are defined to
+* be implementation dependent. Set to 0b0010, which POWER9 UM defines
+* to be interrupt caused by SCOM, which can come from the BMC or NMI
+* IPIs.
+ */
+env->spr[SPR_SRR1] |= PPC_BIT(44);
+}
 }
 
 static void pnv_nmi(NMIState *n, int cpu_index, Error **errp)
-- 
2.23.0

Re: [PATCH 2/5] ppc/pnv: Add support for NMI interface

2020-04-03 Thread Nicholas Piggin

Cédric Le Goater's on March 26, 2020 2:38 am:
> [ Please use c...@kaod.org ! ]
> 
> On 3/25/20 3:41 PM, Nicholas Piggin wrote:
>> This implements the NMI interface for the PNV machine, similarly to
>> commit 3431648272d ("spapr: Add support for new NMI interface") for
>> SPAPR.
>> 
>> Signed-off-by: Nicholas Piggin 
> 
> one minor comment,
> 
> Reviewed-by: Cédric Le Goater 
> 
>> ---
>>  hw/ppc/pnv.c | 30 +-
>>  1 file changed, 29 insertions(+), 1 deletion(-)
>> 
>> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
>> index b75ad06390..671535ebe6 100644
>> --- a/hw/ppc/pnv.c
>> +++ b/hw/ppc/pnv.c
>> @@ -27,6 +27,7 @@
>>  #include "sysemu/runstate.h"
>>  #include "sysemu/cpus.h"
>>  #include "sysemu/device_tree.h"
>> +#include "sysemu/hw_accel.h"
>>  #include "target/ppc/cpu.h"
>>  #include "qemu/log.h"
>>  #include "hw/ppc/fdt.h"
>> @@ -34,6 +35,7 @@
>>  #include "hw/ppc/pnv.h"
>>  #include "hw/ppc/pnv_core.h"
>>  #include "hw/loader.h"
>> +#include "hw/nmi.h"
>>  #include "exec/address-spaces.h"
>>  #include "qapi/visitor.h"
>>  #include "monitor/monitor.h"
>> @@ -1955,10 +1957,35 @@ static void pnv_machine_set_hb(Object *obj, bool 
>> value, Error **errp)
>>  }
>>  }
>> 
>> +static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg)
>> +{
>> +PowerPCCPU *cpu = POWERPC_CPU(cs);
>> +CPUPPCState *env = &cpu->env;
>> +
>> +cpu_synchronize_state(cs);
>> +ppc_cpu_do_system_reset(cs);
>> +/*
>> + * SRR1[42:45] is set to 0100 which the ISA defines as implementation
> 
> I see 'System Reset' in ISA 3.0
>> + * dependent. POWER processors use this for xscom triggered interrupts,
>> + * which come from the BMC or NMI IPIs.
>> + */
>> +env->spr[SPR_SRR1] |= PPC_BIT(43);
> 
> So we could have used the skiboot SPR_SRR1_PM_WAKE_SRESET define ? 

Ah, that's only for power-saving wakeup. But you got me to dig further
and I think I've got a few things wrong here.

The architectural power save wakeup due to sreset bit 43 needs to be
set, probably in excp_helper.c if (msr_pow) test.

case POWERPC_EXCP_RESET: /* System reset exception   */
/* A power-saving exception sets ME, otherwise it is unchanged */
if (msr_pow) {
/* indicate that we resumed from power save mode */
msr |= 0x1;
new_msr |= ((target_ulong)1 << MSR_ME);
}

For non-power save wakeup, it's all implementation defined. POWER9 UM 
has the table, but I got the damn bit wrong, I was probably looking in
the ISA table by mistake. It's bit 44 for that case. Linux doesn't tend 
to care about that case, but it does care about the power save wakeup
case, so this patch seems to generally "work", but I'll have to fix it.

Thanks,
Nick

Re: [PATCH 2/5] ppc/pnv: Add support for NMI interface

2020-03-30 Thread David Gibson

On Tue, Mar 31, 2020 at 02:07:42PM +1100, Alexey Kardashevskiy wrote:
> 
> 
> On 26/03/2020 01:41, Nicholas Piggin wrote:
> > This implements the NMI interface for the PNV machine, similarly to
> > commit 3431648272d ("spapr: Add support for new NMI interface") for
> > SPAPR.
> > 
> > Signed-off-by: Nicholas Piggin 
> > ---
> >  hw/ppc/pnv.c | 30 +-
> >  1 file changed, 29 insertions(+), 1 deletion(-)
> > 
> > diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
> > index b75ad06390..671535ebe6 100644
> > --- a/hw/ppc/pnv.c
> > +++ b/hw/ppc/pnv.c
> > @@ -27,6 +27,7 @@
> >  #include "sysemu/runstate.h"
> >  #include "sysemu/cpus.h"
> >  #include "sysemu/device_tree.h"
> > +#include "sysemu/hw_accel.h"
> >  #include "target/ppc/cpu.h"
> >  #include "qemu/log.h"
> >  #include "hw/ppc/fdt.h"
> > @@ -34,6 +35,7 @@
> >  #include "hw/ppc/pnv.h"
> >  #include "hw/ppc/pnv_core.h"
> >  #include "hw/loader.h"
> > +#include "hw/nmi.h"
> >  #include "exec/address-spaces.h"
> >  #include "qapi/visitor.h"
> >  #include "monitor/monitor.h"
> > @@ -1955,10 +1957,35 @@ static void pnv_machine_set_hb(Object *obj, bool 
> > value, Error **errp)
> >  }
> >  }
> >  
> > +static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg)
> > +{
> > +PowerPCCPU *cpu = POWERPC_CPU(cs);
> > +CPUPPCState *env = &cpu->env;
> > +
> > +cpu_synchronize_state(cs);
> > +ppc_cpu_do_system_reset(cs);
> > +/*
> > + * SRR1[42:45] is set to 0100 which the ISA defines as implementation
> > + * dependent. POWER processors use this for xscom triggered interrupts,
> > + * which come from the BMC or NMI IPIs.
> > + */
> > +env->spr[SPR_SRR1] |= PPC_BIT(43);
> > +}
> > +
> > +static void pnv_nmi(NMIState *n, int cpu_index, Error **errp)
> > +{
> > +CPUState *cs;
> > +
> > +CPU_FOREACH(cs) {
> > +async_run_on_cpu(cs, pnv_cpu_do_nmi_on_cpu, RUN_ON_CPU_NULL);
> > +}
> > +}
> > +
> >  static void pnv_machine_class_init(ObjectClass *oc, void *data)
> >  {
> >  MachineClass *mc = MACHINE_CLASS(oc);
> >  InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc);
> > +NMIClass *nc = NMI_CLASS(oc);
> >  
> >  mc->desc = "IBM PowerNV (Non-Virtualized)";
> >  mc->init = pnv_init;
> > @@ -1975,6 +2002,7 @@ static void pnv_machine_class_init(ObjectClass *oc, 
> > void *data)
> >  mc->default_ram_size = INITRD_LOAD_ADDR + INITRD_MAX_SIZE;
> >  mc->default_ram_id = "pnv.ram";
> >  ispc->print_info = pnv_pic_print_info;
> > +nc->nmi_monitor_handler = pnv_nmi;
> >  
> >  object_class_property_add_bool(oc, "hb-mode",
> > pnv_machine_get_hb, pnv_machine_set_hb,
> > @@ -2038,7 +2066,7 @@ static const TypeInfo types[] = {
> >  .class_size= sizeof(PnvMachineClass),
> >  .interfaces = (InterfaceInfo[]) {
> >  { TYPE_INTERRUPT_STATS_PROVIDER },
> > -{ },
> > +{ TYPE_NMI },
> 
> 
> The interface list must end with {}, otherwise QEMU crashes very early.
> Thanks,

I've fixed that inline now.

> 
> 
> >  },
> >  },
> >  {
> > 
> 

-- 
David Gibson| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au  | minimalist, thank you.  NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson


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Re: [PATCH 2/5] ppc/pnv: Add support for NMI interface

2020-03-30 Thread Alexey Kardashevskiy




On 26/03/2020 01:41, Nicholas Piggin wrote:
> This implements the NMI interface for the PNV machine, similarly to
> commit 3431648272d ("spapr: Add support for new NMI interface") for
> SPAPR.
> 
> Signed-off-by: Nicholas Piggin 
> ---
>  hw/ppc/pnv.c | 30 +-
>  1 file changed, 29 insertions(+), 1 deletion(-)
> 
> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
> index b75ad06390..671535ebe6 100644
> --- a/hw/ppc/pnv.c
> +++ b/hw/ppc/pnv.c
> @@ -27,6 +27,7 @@
>  #include "sysemu/runstate.h"
>  #include "sysemu/cpus.h"
>  #include "sysemu/device_tree.h"
> +#include "sysemu/hw_accel.h"
>  #include "target/ppc/cpu.h"
>  #include "qemu/log.h"
>  #include "hw/ppc/fdt.h"
> @@ -34,6 +35,7 @@
>  #include "hw/ppc/pnv.h"
>  #include "hw/ppc/pnv_core.h"
>  #include "hw/loader.h"
> +#include "hw/nmi.h"
>  #include "exec/address-spaces.h"
>  #include "qapi/visitor.h"
>  #include "monitor/monitor.h"
> @@ -1955,10 +1957,35 @@ static void pnv_machine_set_hb(Object *obj, bool 
> value, Error **errp)
>  }
>  }
>  
> +static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg)
> +{
> +PowerPCCPU *cpu = POWERPC_CPU(cs);
> +CPUPPCState *env = &cpu->env;
> +
> +cpu_synchronize_state(cs);
> +ppc_cpu_do_system_reset(cs);
> +/*
> + * SRR1[42:45] is set to 0100 which the ISA defines as implementation
> + * dependent. POWER processors use this for xscom triggered interrupts,
> + * which come from the BMC or NMI IPIs.
> + */
> +env->spr[SPR_SRR1] |= PPC_BIT(43);
> +}
> +
> +static void pnv_nmi(NMIState *n, int cpu_index, Error **errp)
> +{
> +CPUState *cs;
> +
> +CPU_FOREACH(cs) {
> +async_run_on_cpu(cs, pnv_cpu_do_nmi_on_cpu, RUN_ON_CPU_NULL);
> +}
> +}
> +
>  static void pnv_machine_class_init(ObjectClass *oc, void *data)
>  {
>  MachineClass *mc = MACHINE_CLASS(oc);
>  InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc);
> +NMIClass *nc = NMI_CLASS(oc);
>  
>  mc->desc = "IBM PowerNV (Non-Virtualized)";
>  mc->init = pnv_init;
> @@ -1975,6 +2002,7 @@ static void pnv_machine_class_init(ObjectClass *oc, 
> void *data)
>  mc->default_ram_size = INITRD_LOAD_ADDR + INITRD_MAX_SIZE;
>  mc->default_ram_id = "pnv.ram";
>  ispc->print_info = pnv_pic_print_info;
> +nc->nmi_monitor_handler = pnv_nmi;
>  
>  object_class_property_add_bool(oc, "hb-mode",
> pnv_machine_get_hb, pnv_machine_set_hb,
> @@ -2038,7 +2066,7 @@ static const TypeInfo types[] = {
>  .class_size= sizeof(PnvMachineClass),
>  .interfaces = (InterfaceInfo[]) {
>  { TYPE_INTERRUPT_STATS_PROVIDER },
> -{ },
> +{ TYPE_NMI },


The interface list must end with {}, otherwise QEMU crashes very early.
Thanks,


>  },
>  },
>  {
> 

-- 
Alexey

Re: [PATCH 2/5] ppc/pnv: Add support for NMI interface

2020-03-25 Thread David Gibson

On Thu, Mar 26, 2020 at 12:41:44AM +1000, Nicholas Piggin wrote:
> This implements the NMI interface for the PNV machine, similarly to
> commit 3431648272d ("spapr: Add support for new NMI interface") for
> SPAPR.
> 
> Signed-off-by: Nicholas Piggin 

Applied to ppc-for-5.1.

> ---
>  hw/ppc/pnv.c | 30 +-
>  1 file changed, 29 insertions(+), 1 deletion(-)
> 
> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
> index b75ad06390..671535ebe6 100644
> --- a/hw/ppc/pnv.c
> +++ b/hw/ppc/pnv.c
> @@ -27,6 +27,7 @@
>  #include "sysemu/runstate.h"
>  #include "sysemu/cpus.h"
>  #include "sysemu/device_tree.h"
> +#include "sysemu/hw_accel.h"
>  #include "target/ppc/cpu.h"
>  #include "qemu/log.h"
>  #include "hw/ppc/fdt.h"
> @@ -34,6 +35,7 @@
>  #include "hw/ppc/pnv.h"
>  #include "hw/ppc/pnv_core.h"
>  #include "hw/loader.h"
> +#include "hw/nmi.h"
>  #include "exec/address-spaces.h"
>  #include "qapi/visitor.h"
>  #include "monitor/monitor.h"
> @@ -1955,10 +1957,35 @@ static void pnv_machine_set_hb(Object *obj, bool 
> value, Error **errp)
>  }
>  }
>  
> +static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg)
> +{
> +PowerPCCPU *cpu = POWERPC_CPU(cs);
> +CPUPPCState *env = &cpu->env;
> +
> +cpu_synchronize_state(cs);
> +ppc_cpu_do_system_reset(cs);
> +/*
> + * SRR1[42:45] is set to 0100 which the ISA defines as implementation
> + * dependent. POWER processors use this for xscom triggered interrupts,
> + * which come from the BMC or NMI IPIs.
> + */
> +env->spr[SPR_SRR1] |= PPC_BIT(43);
> +}
> +
> +static void pnv_nmi(NMIState *n, int cpu_index, Error **errp)
> +{
> +CPUState *cs;
> +
> +CPU_FOREACH(cs) {
> +async_run_on_cpu(cs, pnv_cpu_do_nmi_on_cpu, RUN_ON_CPU_NULL);
> +}
> +}
> +
>  static void pnv_machine_class_init(ObjectClass *oc, void *data)
>  {
>  MachineClass *mc = MACHINE_CLASS(oc);
>  InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc);
> +NMIClass *nc = NMI_CLASS(oc);
>  
>  mc->desc = "IBM PowerNV (Non-Virtualized)";
>  mc->init = pnv_init;
> @@ -1975,6 +2002,7 @@ static void pnv_machine_class_init(ObjectClass *oc, 
> void *data)
>  mc->default_ram_size = INITRD_LOAD_ADDR + INITRD_MAX_SIZE;
>  mc->default_ram_id = "pnv.ram";
>  ispc->print_info = pnv_pic_print_info;
> +nc->nmi_monitor_handler = pnv_nmi;
>  
>  object_class_property_add_bool(oc, "hb-mode",
> pnv_machine_get_hb, pnv_machine_set_hb,
> @@ -2038,7 +2066,7 @@ static const TypeInfo types[] = {
>  .class_size= sizeof(PnvMachineClass),
>  .interfaces = (InterfaceInfo[]) {
>  { TYPE_INTERRUPT_STATS_PROVIDER },
> -{ },
> +{ TYPE_NMI },
>  },
>  },
>  {

-- 
David Gibson| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au  | minimalist, thank you.  NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson


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Re: [PATCH 2/5] ppc/pnv: Add support for NMI interface

2020-03-25 Thread Cédric Le Goater

[ Please use c...@kaod.org ! ]

On 3/25/20 3:41 PM, Nicholas Piggin wrote:
> This implements the NMI interface for the PNV machine, similarly to
> commit 3431648272d ("spapr: Add support for new NMI interface") for
> SPAPR.
> 
> Signed-off-by: Nicholas Piggin 

one minor comment,

Reviewed-by: Cédric Le Goater 

> ---
>  hw/ppc/pnv.c | 30 +-
>  1 file changed, 29 insertions(+), 1 deletion(-)
> 
> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
> index b75ad06390..671535ebe6 100644
> --- a/hw/ppc/pnv.c
> +++ b/hw/ppc/pnv.c
> @@ -27,6 +27,7 @@
>  #include "sysemu/runstate.h"
>  #include "sysemu/cpus.h"
>  #include "sysemu/device_tree.h"
> +#include "sysemu/hw_accel.h"
>  #include "target/ppc/cpu.h"
>  #include "qemu/log.h"
>  #include "hw/ppc/fdt.h"
> @@ -34,6 +35,7 @@
>  #include "hw/ppc/pnv.h"
>  #include "hw/ppc/pnv_core.h"
>  #include "hw/loader.h"
> +#include "hw/nmi.h"
>  #include "exec/address-spaces.h"
>  #include "qapi/visitor.h"
>  #include "monitor/monitor.h"
> @@ -1955,10 +1957,35 @@ static void pnv_machine_set_hb(Object *obj, bool 
> value, Error **errp)
>  }
>  }
> 
> +static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg)
> +{
> +PowerPCCPU *cpu = POWERPC_CPU(cs);
> +CPUPPCState *env = &cpu->env;
> +
> +cpu_synchronize_state(cs);
> +ppc_cpu_do_system_reset(cs);
> +/*
> + * SRR1[42:45] is set to 0100 which the ISA defines as implementation

I see 'System Reset' in ISA 3.0

> + * dependent. POWER processors use this for xscom triggered interrupts,
> + * which come from the BMC or NMI IPIs.
> + */
> +env->spr[SPR_SRR1] |= PPC_BIT(43);

So we could have used the skiboot SPR_SRR1_PM_WAKE_SRESET define ? 

> +}
> +
> +static void pnv_nmi(NMIState *n, int cpu_index, Error **errp)
> +{
> +CPUState *cs;
> +
> +CPU_FOREACH(cs) {
> +async_run_on_cpu(cs, pnv_cpu_do_nmi_on_cpu, RUN_ON_CPU_NULL);
> +}
> +}
> +
>  static void pnv_machine_class_init(ObjectClass *oc, void *data)
>  {
>  MachineClass *mc = MACHINE_CLASS(oc);
>  InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc);
> +NMIClass *nc = NMI_CLASS(oc);
> 
>  mc->desc = "IBM PowerNV (Non-Virtualized)";
>  mc->init = pnv_init;
> @@ -1975,6 +2002,7 @@ static void pnv_machine_class_init(ObjectClass *oc, 
> void *data)
>  mc->default_ram_size = INITRD_LOAD_ADDR + INITRD_MAX_SIZE;
>  mc->default_ram_id = "pnv.ram";
>  ispc->print_info = pnv_pic_print_info;
> +nc->nmi_monitor_handler = pnv_nmi;
> 
>  object_class_property_add_bool(oc, "hb-mode",
> pnv_machine_get_hb, pnv_machine_set_hb,
> @@ -2038,7 +2066,7 @@ static const TypeInfo types[] = {
>  .class_size= sizeof(PnvMachineClass),
>  .interfaces = (InterfaceInfo[]) {
>  { TYPE_INTERRUPT_STATS_PROVIDER },
> -{ },
> +{ TYPE_NMI },
>  },
>  },
>  {
>

[PATCH 2/5] ppc/pnv: Add support for NMI interface

2020-03-25 Thread Nicholas Piggin

This implements the NMI interface for the PNV machine, similarly to
commit 3431648272d ("spapr: Add support for new NMI interface") for
SPAPR.

Signed-off-by: Nicholas Piggin 
---
 hw/ppc/pnv.c | 30 +-
 1 file changed, 29 insertions(+), 1 deletion(-)

diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index b75ad06390..671535ebe6 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -27,6 +27,7 @@
 #include "sysemu/runstate.h"
 #include "sysemu/cpus.h"
 #include "sysemu/device_tree.h"
+#include "sysemu/hw_accel.h"
 #include "target/ppc/cpu.h"
 #include "qemu/log.h"
 #include "hw/ppc/fdt.h"
@@ -34,6 +35,7 @@
 #include "hw/ppc/pnv.h"
 #include "hw/ppc/pnv_core.h"
 #include "hw/loader.h"
+#include "hw/nmi.h"
 #include "exec/address-spaces.h"
 #include "qapi/visitor.h"
 #include "monitor/monitor.h"
@@ -1955,10 +1957,35 @@ static void pnv_machine_set_hb(Object *obj, bool value, 
Error **errp)
 }
 }
 
+static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg)
+{
+PowerPCCPU *cpu = POWERPC_CPU(cs);
+CPUPPCState *env = &cpu->env;
+
+cpu_synchronize_state(cs);
+ppc_cpu_do_system_reset(cs);
+/*
+ * SRR1[42:45] is set to 0100 which the ISA defines as implementation
+ * dependent. POWER processors use this for xscom triggered interrupts,
+ * which come from the BMC or NMI IPIs.
+ */
+env->spr[SPR_SRR1] |= PPC_BIT(43);
+}
+
+static void pnv_nmi(NMIState *n, int cpu_index, Error **errp)
+{
+CPUState *cs;
+
+CPU_FOREACH(cs) {
+async_run_on_cpu(cs, pnv_cpu_do_nmi_on_cpu, RUN_ON_CPU_NULL);
+}
+}
+
 static void pnv_machine_class_init(ObjectClass *oc, void *data)
 {
 MachineClass *mc = MACHINE_CLASS(oc);
 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc);
+NMIClass *nc = NMI_CLASS(oc);
 
 mc->desc = "IBM PowerNV (Non-Virtualized)";
 mc->init = pnv_init;
@@ -1975,6 +2002,7 @@ static void pnv_machine_class_init(ObjectClass *oc, void 
*data)
 mc->default_ram_size = INITRD_LOAD_ADDR + INITRD_MAX_SIZE;
 mc->default_ram_id = "pnv.ram";
 ispc->print_info = pnv_pic_print_info;
+nc->nmi_monitor_handler = pnv_nmi;
 
 object_class_property_add_bool(oc, "hb-mode",
pnv_machine_get_hb, pnv_machine_set_hb,
@@ -2038,7 +2066,7 @@ static const TypeInfo types[] = {
 .class_size= sizeof(PnvMachineClass),
 .interfaces = (InterfaceInfo[]) {
 { TYPE_INTERRUPT_STATS_PROVIDER },
-{ },
+{ TYPE_NMI },
 },
 },
 {
-- 
2.23.0

Re: [PATCH 2/5] ppc/pnv: Add support for NMI interface

Re: [PATCH 2/5] ppc/pnv: Add support for NMI interface

Re: [PATCH 2/5] ppc/pnv: Add support for NMI interface

Re: [PATCH 2/5] ppc/pnv: Add support for NMI interface

Re: [PATCH 2/5] ppc/pnv: Add support for NMI interface

Re: [PATCH 2/5] ppc/pnv: Add support for NMI interface

Re: [PATCH 2/5] ppc/pnv: Add support for NMI interface

Re: [PATCH 2/5] ppc/pnv: Add support for NMI interface

[PATCH 2/5] ppc/pnv: Add support for NMI interface

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