Re: [PATCH v13 2/7] hw/core/machine: topology functions capabilities added

[Jonathan Cameron via]

On Wed, 11 Jun 2025 16:56:13 +0100
Alireza Sanaee  wrote:

> Add two functions one of which finds the lowest level cache defined in
> the cache description input, and the other checks if caches are defined
> at a particular level.
> 
> Signed-off-by: Alireza Sanaee 
> ---
>  hw/core/machine-smp.c | 52 +++
>  include/hw/boards.h   |  7 ++
>  2 files changed, 59 insertions(+)
> 
> diff --git a/hw/core/machine-smp.c b/hw/core/machine-smp.c
> index 0be0ac044c..a4d79e0aa4 100644
> --- a/hw/core/machine-smp.c
> +++ b/hw/core/machine-smp.c

> +
> +bool machine_check_cache_at_topo_level(const MachineState *ms,

Maybe avoid machine_check naming. It has too many other meanings!

machine_is_cache_at_topo_level() perhaps?

> +   CpuTopologyLevel level)
> +{
> +if (machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L3) == level ||
> +machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L2) == level ||
> +machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1I) == level 
> ||
> +machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1D) == level) 
> {
> +return true;
> +}
> +return false;
> +}

Re: [PATCH v13 2/7] hw/core/machine: topology functions capabilities added

[Zhao Liu]

On Wed, Jun 11, 2025 at 04:56:13PM +0100, Alireza Sanaee wrote:
> Date: Wed, 11 Jun 2025 16:56:13 +0100
> From: Alireza Sanaee 
> Subject: [PATCH v13 2/7] hw/core/machine: topology functions capabilities
>  added
> X-Mailer: git-send-email 2.34.1
> 
> Add two functions one of which finds the lowest level cache defined in
> the cache description input, and the other checks if caches are defined
> at a particular level.
> 
> Signed-off-by: Alireza Sanaee 
> ---
>  hw/core/machine-smp.c | 52 +++
>  include/hw/boards.h   |  7 ++
>  2 files changed, 59 insertions(+)

Reviewed-by: Zhao Liu 

[PATCH v13 2/7] hw/core/machine: topology functions capabilities added

[Alireza Sanaee via]

Add two functions one of which finds the lowest level cache defined in
the cache description input, and the other checks if caches are defined
at a particular level.

Signed-off-by: Alireza Sanaee 
---
 hw/core/machine-smp.c | 52 +++
 include/hw/boards.h   |  7 ++
 2 files changed, 59 insertions(+)

diff --git a/hw/core/machine-smp.c b/hw/core/machine-smp.c
index 0be0ac044c..a4d79e0aa4 100644
--- a/hw/core/machine-smp.c
+++ b/hw/core/machine-smp.c
@@ -406,3 +406,55 @@ bool machine_check_smp_cache(const MachineState *ms, Error 
**errp)
 
 return true;
 }
+
+/*
+ * This function assumes l3 and l2 have unified cache and l1 is split l1d
+ * and l1i, and further prepares the lowest cache level for a topology
+ * level.  The info will be fed to build_caches to create caches at the
+ * right level.
+ */
+bool machine_find_lowest_level_cache_at_topo_level(const MachineState *ms,
+   int *level_found,
+   CpuTopologyLevel topo_level)
+{
+
+CpuTopologyLevel level;
+
+level = machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1I);
+if (level == topo_level) {
+*level_found = 1;
+return true;
+}
+
+level = machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1D);
+if (level == topo_level) {
+*level_found = 1;
+return true;
+}
+
+level = machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L2);
+if (level == topo_level) {
+*level_found = 2;
+return true;
+}
+
+level = machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L3);
+if (level == topo_level) {
+*level_found = 3;
+return true;
+}
+
+return false;
+}
+
+bool machine_check_cache_at_topo_level(const MachineState *ms,
+   CpuTopologyLevel level)
+{
+if (machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L3) == level ||
+machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L2) == level ||
+machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1I) == level ||
+machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1D) == level) {
+return true;
+}
+return false;
+}
diff --git a/include/hw/boards.h b/include/hw/boards.h
index f424b2b505..b24da305c4 100644
--- a/include/hw/boards.h
+++ b/include/hw/boards.h
@@ -55,6 +55,13 @@ void machine_set_cache_topo_level(MachineState *ms, 
CacheLevelAndType cache,
   CpuTopologyLevel level);
 bool machine_check_smp_cache(const MachineState *ms, Error **errp);
 void machine_memory_devices_init(MachineState *ms, hwaddr base, uint64_t size);
+bool machine_check_cache_at_topo_level(const MachineState *ms,
+   CpuTopologyLevel level);
+
+bool machine_find_lowest_level_cache_at_topo_level(const MachineState *ms,
+   int *level_found,
+   CpuTopologyLevel 
topo_level);
+
 
 /**
  * machine_class_allow_dynamic_sysbus_dev: Add type to list of valid devices
-- 
2.43.0