A KVM-only build won't be able to run M-profile cpus.
Only enable the following ARMv7 M-Profile CPUs when TCG is available:
- Cortex-M3
- Cortex-M4
- Cortex-M33
Signed-off-by: Philippe Mathieu-Daudé
---
default-configs/arm-softmmu.mak | 8 --
target/arm/cpu.c| 176 ---
target/arm/cpu_v7m.c| 207
target/arm/Kconfig | 1 +
target/arm/Makefile.objs| 1 +
5 files changed, 209 insertions(+), 184 deletions(-)
create mode 100644 target/arm/cpu_v7m.c
diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index 3aa27f3b40..511d74da58 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -12,19 +12,11 @@ CONFIG_ARM_V7M=y
CONFIG_ARM_VIRT=y
CONFIG_CUBIEBOARD=y
CONFIG_EXYNOS4=y
-CONFIG_HIGHBANK=y
-CONFIG_MUSCA=y
-CONFIG_STELLARIS=y
CONFIG_REALVIEW=y
CONFIG_VEXPRESS=y
CONFIG_ZYNQ=y
-CONFIG_NETDUINO2=y
-CONFIG_NETDUINOPLUS2=y
-CONFIG_MPS2=y
CONFIG_RASPI=y
CONFIG_SABRELITE=y
-CONFIG_EMCRAFT_SF2=y
-CONFIG_MICROBIT=y
CONFIG_FSL_IMX7=y
CONFIG_FSL_IMX6UL=y
CONFIG_ALLWINNER_H3=y
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 84be8792f6..dfa7e64c7e 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -573,31 +573,6 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int
interrupt_request)
return true;
}
-#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
-static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
-{
-CPUClass *cc = CPU_GET_CLASS(cs);
-ARMCPU *cpu = ARM_CPU(cs);
-CPUARMState *env = >env;
-bool ret = false;
-
-/* ARMv7-M interrupt masking works differently than -A or -R.
- * There is no FIQ/IRQ distinction. Instead of I and F bits
- * masking FIQ and IRQ interrupts, an exception is taken only
- * if it is higher priority than the current execution priority
- * (which depends on state like BASEPRI, FAULTMASK and the
- * currently active exception).
- */
-if (interrupt_request & CPU_INTERRUPT_HARD
-&& (armv7m_nvic_can_take_pending_exception(env->nvic))) {
-cs->exception_index = EXCP_IRQ;
-cc->do_interrupt(cs);
-ret = true;
-}
-return ret;
-}
-#endif
-
void arm_cpu_update_virq(ARMCPU *cpu)
{
/*
@@ -1834,147 +1809,6 @@ static ObjectClass *arm_cpu_class_by_name(const char
*cpu_model)
/* CPU models. These are not needed for the AArch64 linux-user build. */
#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
-static void cortex_m0_initfn(Object *obj)
-{
-ARMCPU *cpu = ARM_CPU(obj);
-set_feature(>env, ARM_FEATURE_V6);
-set_feature(>env, ARM_FEATURE_M);
-
-cpu->midr = 0x410cc200;
-}
-
-static void cortex_m3_initfn(Object *obj)
-{
-ARMCPU *cpu = ARM_CPU(obj);
-set_feature(>env, ARM_FEATURE_V7);
-set_feature(>env, ARM_FEATURE_M);
-set_feature(>env, ARM_FEATURE_M_MAIN);
-cpu->midr = 0x410fc231;
-cpu->pmsav7_dregion = 8;
-cpu->id_pfr0 = 0x0030;
-cpu->id_pfr1 = 0x0200;
-cpu->isar.id_dfr0 = 0x0010;
-cpu->id_afr0 = 0x;
-cpu->isar.id_mmfr0 = 0x0030;
-cpu->isar.id_mmfr1 = 0x;
-cpu->isar.id_mmfr2 = 0x;
-cpu->isar.id_mmfr3 = 0x;
-cpu->isar.id_isar0 = 0x01141110;
-cpu->isar.id_isar1 = 0x02111000;
-cpu->isar.id_isar2 = 0x21112231;
-cpu->isar.id_isar3 = 0x0110;
-cpu->isar.id_isar4 = 0x01310102;
-cpu->isar.id_isar5 = 0x;
-cpu->isar.id_isar6 = 0x;
-}
-
-static void cortex_m4_initfn(Object *obj)
-{
-ARMCPU *cpu = ARM_CPU(obj);
-
-set_feature(>env, ARM_FEATURE_V7);
-set_feature(>env, ARM_FEATURE_M);
-set_feature(>env, ARM_FEATURE_M_MAIN);
-set_feature(>env, ARM_FEATURE_THUMB_DSP);
-cpu->midr = 0x410fc240; /* r0p0 */
-cpu->pmsav7_dregion = 8;
-cpu->isar.mvfr0 = 0x10110021;
-cpu->isar.mvfr1 = 0x1111;
-cpu->isar.mvfr2 = 0x;
-cpu->id_pfr0 = 0x0030;
-cpu->id_pfr1 = 0x0200;
-cpu->isar.id_dfr0 = 0x0010;
-cpu->id_afr0 = 0x;
-cpu->isar.id_mmfr0 = 0x0030;
-cpu->isar.id_mmfr1 = 0x;
-cpu->isar.id_mmfr2 = 0x;
-cpu->isar.id_mmfr3 = 0x;
-cpu->isar.id_isar0 = 0x01141110;
-cpu->isar.id_isar1 = 0x02111000;
-cpu->isar.id_isar2 = 0x21112231;
-cpu->isar.id_isar3 = 0x0110;
-cpu->isar.id_isar4 = 0x01310102;
-cpu->isar.id_isar5 = 0x;
-cpu->isar.id_isar6 = 0x;
-}
-
-static void cortex_m7_initfn(Object *obj)
-{
-ARMCPU *cpu = ARM_CPU(obj);
-
-set_feature(>env, ARM_FEATURE_V7);
-set_feature(>env, ARM_FEATURE_M);
-set_feature(>env, ARM_FEATURE_M_MAIN);
-set_feature(>env, ARM_FEATURE_THUMB_DSP);
-cpu->midr = 0x411fc272; /* r1p2 */
-cpu->pmsav7_dregion = 8;
-cpu->isar.mvfr0 = 0x10110221;
-cpu->isar.mvfr1 = 0x1211;
-cpu->isar.mvfr2 = 0x0040;
-
