Re: [PATCH v3 19/19] target/riscv/cpu: move priv spec functions to tcg-cpu.c
On Wed, Sep 20, 2023 at 9:24 PM Daniel Henrique Barboza
wrote:
>
> Priv spec validation is TCG specific. Move it to the TCG accel class.
>
> Signed-off-by: Daniel Henrique Barboza
> Reviewed-by: Andrew Jones
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu.c | 38 --
> target/riscv/cpu.h | 2 --
> target/riscv/tcg/tcg-cpu.c | 38 ++
> 3 files changed, 38 insertions(+), 40 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index e97ba3df93..eeeb08a35a 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -172,21 +172,6 @@ void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t
> ext_offset, bool en)
> *ext_enabled = en;
> }
>
> -int cpu_cfg_ext_get_min_version(uint32_t ext_offset)
> -{
> -const RISCVIsaExtData *edata;
> -
> -for (edata = isa_edata_arr; edata && edata->name; edata++) {
> -if (edata->ext_enable_offset != ext_offset) {
> -continue;
> -}
> -
> -return edata->min_version;
> -}
> -
> -g_assert_not_reached();
> -}
> -
> const char * const riscv_int_regnames[] = {
> "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1",
> "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3",
> @@ -925,29 +910,6 @@ static void riscv_cpu_disas_set_info(CPUState *s,
> disassemble_info *info)
> }
> }
>
> -void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu)
> -{
> -CPURISCVState *env = >env;
> -const RISCVIsaExtData *edata;
> -
> -/* Force disable extensions if priv spec version does not match */
> -for (edata = isa_edata_arr; edata && edata->name; edata++) {
> -if (isa_ext_is_enabled(cpu, edata->ext_enable_offset) &&
> -(env->priv_ver < edata->min_version)) {
> -isa_ext_update_enabled(cpu, edata->ext_enable_offset, false);
> -#ifndef CONFIG_USER_ONLY
> -warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx
> -" because privilege spec version does not match",
> -edata->name, env->mhartid);
> -#else
> -warn_report("disabling %s extension because "
> -"privilege spec version does not match",
> -edata->name);
> -#endif
> -}
> -}
> -}
> -
> #ifndef CONFIG_USER_ONLY
> static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp)
> {
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 3dfcd0732f..219fe2e9b5 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -711,9 +711,7 @@ enum riscv_pmu_event_idx {
> /* used by tcg/tcg-cpu.c*/
> void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en);
> bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset);
> -int cpu_cfg_ext_get_min_version(uint32_t ext_offset);
> void riscv_cpu_set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext);
> -void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu);
>
> typedef struct RISCVCPUMultiExtConfig {
> const char *name;
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index c326ab37a2..8c052d6fcd 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -99,6 +99,21 @@ static const struct TCGCPUOps riscv_tcg_ops = {
> #endif /* !CONFIG_USER_ONLY */
> };
>
> +static int cpu_cfg_ext_get_min_version(uint32_t ext_offset)
> +{
> +const RISCVIsaExtData *edata;
> +
> +for (edata = isa_edata_arr; edata && edata->name; edata++) {
> +if (edata->ext_enable_offset != ext_offset) {
> +continue;
> +}
> +
> +return edata->min_version;
> +}
> +
> +g_assert_not_reached();
> +}
> +
> static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uint32_t ext_offset,
> bool value)
> {
> @@ -226,6 +241,29 @@ static void riscv_cpu_validate_v(CPURISCVState *env,
> RISCVCPUConfig *cfg,
> }
> }
>
> +static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu)
> +{
> +CPURISCVState *env = >env;
> +const RISCVIsaExtData *edata;
> +
> +/* Force disable extensions if priv spec version does not match */
> +for (edata = isa_edata_arr; edata && edata->name; edata++) {
> +if (isa_ext_is_enabled(cpu, edata->ext_enable_offset) &&
> +(env->priv_ver < edata->min_version)) {
> +isa_ext_update_enabled(cpu, edata->ext_enable_offset, false);
> +#ifndef CONFIG_USER_ONLY
> +warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx
> +" because privilege spec version does not match",
> +edata->name, env->mhartid);
> +#else
> +warn_report("disabling %s extension because "
> +"privilege spec version does not match",
> +edata->name);
> +#endif
> +}
> +}
> +}
> +
> /*
>
Re: [PATCH v3 19/19] target/riscv/cpu: move priv spec functions to tcg-cpu.c
On 20/9/23 13:20, Daniel Henrique Barboza wrote: Priv spec validation is TCG specific. Move it to the TCG accel class. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones --- target/riscv/cpu.c | 38 -- target/riscv/cpu.h | 2 -- target/riscv/tcg/tcg-cpu.c | 38 ++ 3 files changed, 38 insertions(+), 40 deletions(-) Reviewed-by: Philippe Mathieu-Daudé
[PATCH v3 19/19] target/riscv/cpu: move priv spec functions to tcg-cpu.c
Priv spec validation is TCG specific. Move it to the TCG accel class.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Andrew Jones
---
target/riscv/cpu.c | 38 --
target/riscv/cpu.h | 2 --
target/riscv/tcg/tcg-cpu.c | 38 ++
3 files changed, 38 insertions(+), 40 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index e97ba3df93..eeeb08a35a 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -172,21 +172,6 @@ void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t
ext_offset, bool en)
*ext_enabled = en;
}
-int cpu_cfg_ext_get_min_version(uint32_t ext_offset)
-{
-const RISCVIsaExtData *edata;
-
-for (edata = isa_edata_arr; edata && edata->name; edata++) {
-if (edata->ext_enable_offset != ext_offset) {
-continue;
-}
-
-return edata->min_version;
-}
-
-g_assert_not_reached();
-}
-
const char * const riscv_int_regnames[] = {
"x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1",
"x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3",
@@ -925,29 +910,6 @@ static void riscv_cpu_disas_set_info(CPUState *s,
disassemble_info *info)
}
}
-void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu)
-{
-CPURISCVState *env = >env;
-const RISCVIsaExtData *edata;
-
-/* Force disable extensions if priv spec version does not match */
-for (edata = isa_edata_arr; edata && edata->name; edata++) {
-if (isa_ext_is_enabled(cpu, edata->ext_enable_offset) &&
-(env->priv_ver < edata->min_version)) {
-isa_ext_update_enabled(cpu, edata->ext_enable_offset, false);
-#ifndef CONFIG_USER_ONLY
-warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx
-" because privilege spec version does not match",
-edata->name, env->mhartid);
-#else
-warn_report("disabling %s extension because "
-"privilege spec version does not match",
-edata->name);
-#endif
-}
-}
-}
-
#ifndef CONFIG_USER_ONLY
static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp)
{
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 3dfcd0732f..219fe2e9b5 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -711,9 +711,7 @@ enum riscv_pmu_event_idx {
/* used by tcg/tcg-cpu.c*/
void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en);
bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset);
-int cpu_cfg_ext_get_min_version(uint32_t ext_offset);
void riscv_cpu_set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext);
-void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu);
typedef struct RISCVCPUMultiExtConfig {
const char *name;
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index c326ab37a2..8c052d6fcd 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -99,6 +99,21 @@ static const struct TCGCPUOps riscv_tcg_ops = {
#endif /* !CONFIG_USER_ONLY */
};
+static int cpu_cfg_ext_get_min_version(uint32_t ext_offset)
+{
+const RISCVIsaExtData *edata;
+
+for (edata = isa_edata_arr; edata && edata->name; edata++) {
+if (edata->ext_enable_offset != ext_offset) {
+continue;
+}
+
+return edata->min_version;
+}
+
+g_assert_not_reached();
+}
+
static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uint32_t ext_offset,
bool value)
{
@@ -226,6 +241,29 @@ static void riscv_cpu_validate_v(CPURISCVState *env,
RISCVCPUConfig *cfg,
}
}
+static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu)
+{
+CPURISCVState *env = >env;
+const RISCVIsaExtData *edata;
+
+/* Force disable extensions if priv spec version does not match */
+for (edata = isa_edata_arr; edata && edata->name; edata++) {
+if (isa_ext_is_enabled(cpu, edata->ext_enable_offset) &&
+(env->priv_ver < edata->min_version)) {
+isa_ext_update_enabled(cpu, edata->ext_enable_offset, false);
+#ifndef CONFIG_USER_ONLY
+warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx
+" because privilege spec version does not match",
+edata->name, env->mhartid);
+#else
+warn_report("disabling %s extension because "
+"privilege spec version does not match",
+edata->name);
+#endif
+}
+}
+}
+
/*
* Check consistency between chosen extensions while setting
* cpu->cfg accordingly.
--
2.41.0
