RE: [PATCH v3 2/6] hw/gpio/aspeed_sgpio: Add QOM property accessors for SGPIO pins

2025-12-10 Thread Kane Chen
> -Original Message-
> From: Yubin Zou 
> Sent: Thursday, December 11, 2025 7:29 AM
> To: [email protected]
> Cc: Cédric Le Goater ; Peter Maydell
> ; Steven Lee ; Troy
> Lee ; Jamin Lin ; Andrew
> Jeffery ; Joel Stanley ;
> Fabiano Rosas ; Laurent Vivier ;
> Paolo Bonzini ; Kane Chen
> ; Nabih Estefan ;
> [email protected]; Yubin Zou 
> Subject: [PATCH v3 2/6] hw/gpio/aspeed_sgpio: Add QOM property accessors
> for SGPIO pins
> 
> The `aspeed_sgpio_get_pin` and `aspeed_sgpio_set_pin` functions are
> implemented to get and set the level of individual SGPIO pins. These are then
> exposed as boolean properties on the SGPIO device object.
> 
> Signed-off-by: Yubin Zou 
> ---
>  hw/gpio/aspeed_sgpio.c | 78
> ++
>  1 file changed, 78 insertions(+)
> 
> diff --git a/hw/gpio/aspeed_sgpio.c b/hw/gpio/aspeed_sgpio.c index
> 8676fa7ced134f1f62dc9e30b42c5fe6db3de268..27c406d5042f423b914d53de
> 000b727cb7242dc9 100644
> --- a/hw/gpio/aspeed_sgpio.c
> +++ b/hw/gpio/aspeed_sgpio.c
> @@ -91,6 +91,73 @@ static void aspeed_sgpio_2700_write(void *opaque,
> hwaddr offset, uint64_t data,
>  }
>  }
> 
> +static bool aspeed_sgpio_get_pin_level(AspeedSGPIOState *s, int pin) {
> +uint32_t value = s->ctrl_regs[pin >> 1];
> +bool is_input = !(pin % 2);
> +uint32_t bit_mask = 0;
> +
> +if (is_input) {
> +bit_mask = SGPIO_SERIAL_IN_VAL_MASK;
> +} else {
> +bit_mask = SGPIO_SERIAL_OUT_VAL_MASK;
> +}
> +
> +return value & bit_mask;
> +}
> +
> +static void aspeed_sgpio_set_pin_level(AspeedSGPIOState *s, int pin,
> +bool level) {
> +uint32_t value = s->ctrl_regs[pin >> 1];
> +bool is_input = !(pin % 2);
> +uint32_t bit_mask = 0;
> +
> +if (is_input) {
> +bit_mask = SGPIO_SERIAL_IN_VAL_MASK;
> +} else {
> +bit_mask = SGPIO_SERIAL_OUT_VAL_MASK;
> +}
> +
> +if (level) {
> +value |= bit_mask;
> +} else {
> +value &= ~bit_mask;
> +}
> +s->ctrl_regs[pin >> 1] = value;
> +}
> +
> +static void aspeed_sgpio_get_pin(Object *obj, Visitor *v, const char *name,
> +void *opaque, Error **errp) {
> +bool level = true;
> +int pin = 0xfff;
> +AspeedSGPIOState *s = ASPEED_SGPIO(obj);
> +
> +if (sscanf(name, "sgpio%03d", &pin) != 1) {
> +error_setg(errp, "%s: error reading %s", __func__, name);
> +return;
> +}
> +level = aspeed_sgpio_get_pin_level(s, pin);
> +visit_type_bool(v, name, &level, errp); }
> +
> +static void aspeed_sgpio_set_pin(Object *obj, Visitor *v, const char *name,
> +void *opaque, Error **errp) {
> +bool level;
> +int pin = 0xfff;
> +AspeedSGPIOState *s = ASPEED_SGPIO(obj);
> +
> +if (!visit_type_bool(v, name, &level, errp)) {
> +return;
> +}
> +if (sscanf(name, "sgpio%03d", &pin) != 1) {
> +error_setg(errp, "%s: error reading %s", __func__, name);
> +return;
> +}
> +aspeed_sgpio_set_pin_level(s, pin, level); }
> +
>  static const MemoryRegionOps aspeed_gpio_2700_ops = {
>.read   = aspeed_sgpio_2700_read,
>.write  = aspeed_sgpio_2700_write,
> @@ -114,6 +181,16 @@ static void aspeed_sgpio_realize(DeviceState *dev,
> Error **errp)
>  sysbus_init_mmio(sbd, &s->iomem);
>  }
> 
> +static void aspeed_sgpio_init(Object *obj) {
> +for (int i = 0; i < ASPEED_SGPIO_MAX_PIN_PAIR * 2; i++) {
> +char *name = g_strdup_printf("sgpio%03d", i);
> +object_property_add(obj, name, "bool", aspeed_sgpio_get_pin,
> +aspeed_sgpio_set_pin, NULL, NULL);
> +g_autofree(name);
> +}
> +}

Please use "g_autofree char *name ". g_autofree(name); will cause a build 
failure.

> +
>  static void aspeed_sgpio_class_init(ObjectClass *klass, const void *data)  {
>  DeviceClass *dc = DEVICE_CLASS(klass); @@ -143,6 +220,7 @@ static
> const TypeInfo aspeed_sgpio_ast2700_info = {
>.name   = TYPE_ASPEED_SGPIO "-ast2700",
>.parent = TYPE_ASPEED_SGPIO,
>.class_init = aspeed_sgpio_2700_class_init,
> +  .instance_init  = aspeed_sgpio_init,
>  };
> 
>  static void aspeed_sgpio_register_types(void)
> 
> --
> 2.52.0.239.gd5f0c6e74e-goog

Best Regards,
Kane


[PATCH v3 2/6] hw/gpio/aspeed_sgpio: Add QOM property accessors for SGPIO pins

2025-12-10 Thread Yubin Zou
The `aspeed_sgpio_get_pin` and `aspeed_sgpio_set_pin` functions are
implemented to get and set the level of individual SGPIO pins. These
are then exposed as boolean properties on the SGPIO device object.

Signed-off-by: Yubin Zou 
---
 hw/gpio/aspeed_sgpio.c | 78 ++
 1 file changed, 78 insertions(+)

diff --git a/hw/gpio/aspeed_sgpio.c b/hw/gpio/aspeed_sgpio.c
index 
8676fa7ced134f1f62dc9e30b42c5fe6db3de268..27c406d5042f423b914d53de000b727cb7242dc9
 100644
--- a/hw/gpio/aspeed_sgpio.c
+++ b/hw/gpio/aspeed_sgpio.c
@@ -91,6 +91,73 @@ static void aspeed_sgpio_2700_write(void *opaque, hwaddr 
offset, uint64_t data,
 }
 }
 
+static bool aspeed_sgpio_get_pin_level(AspeedSGPIOState *s, int pin)
+{
+uint32_t value = s->ctrl_regs[pin >> 1];
+bool is_input = !(pin % 2);
+uint32_t bit_mask = 0;
+
+if (is_input) {
+bit_mask = SGPIO_SERIAL_IN_VAL_MASK;
+} else {
+bit_mask = SGPIO_SERIAL_OUT_VAL_MASK;
+}
+
+return value & bit_mask;
+}
+
+static void aspeed_sgpio_set_pin_level(AspeedSGPIOState *s, int pin, bool 
level)
+{
+uint32_t value = s->ctrl_regs[pin >> 1];
+bool is_input = !(pin % 2);
+uint32_t bit_mask = 0;
+
+if (is_input) {
+bit_mask = SGPIO_SERIAL_IN_VAL_MASK;
+} else {
+bit_mask = SGPIO_SERIAL_OUT_VAL_MASK;
+}
+
+if (level) {
+value |= bit_mask;
+} else {
+value &= ~bit_mask;
+}
+s->ctrl_regs[pin >> 1] = value;
+}
+
+static void aspeed_sgpio_get_pin(Object *obj, Visitor *v, const char *name,
+void *opaque, Error **errp)
+{
+bool level = true;
+int pin = 0xfff;
+AspeedSGPIOState *s = ASPEED_SGPIO(obj);
+
+if (sscanf(name, "sgpio%03d", &pin) != 1) {
+error_setg(errp, "%s: error reading %s", __func__, name);
+return;
+}
+level = aspeed_sgpio_get_pin_level(s, pin);
+visit_type_bool(v, name, &level, errp);
+}
+
+static void aspeed_sgpio_set_pin(Object *obj, Visitor *v, const char *name,
+void *opaque, Error **errp)
+{
+bool level;
+int pin = 0xfff;
+AspeedSGPIOState *s = ASPEED_SGPIO(obj);
+
+if (!visit_type_bool(v, name, &level, errp)) {
+return;
+}
+if (sscanf(name, "sgpio%03d", &pin) != 1) {
+error_setg(errp, "%s: error reading %s", __func__, name);
+return;
+}
+aspeed_sgpio_set_pin_level(s, pin, level);
+}
+
 static const MemoryRegionOps aspeed_gpio_2700_ops = {
   .read   = aspeed_sgpio_2700_read,
   .write  = aspeed_sgpio_2700_write,
@@ -114,6 +181,16 @@ static void aspeed_sgpio_realize(DeviceState *dev, Error 
**errp)
 sysbus_init_mmio(sbd, &s->iomem);
 }
 
+static void aspeed_sgpio_init(Object *obj)
+{
+for (int i = 0; i < ASPEED_SGPIO_MAX_PIN_PAIR * 2; i++) {
+char *name = g_strdup_printf("sgpio%03d", i);
+object_property_add(obj, name, "bool", aspeed_sgpio_get_pin,
+aspeed_sgpio_set_pin, NULL, NULL);
+g_autofree(name);
+}
+}
+
 static void aspeed_sgpio_class_init(ObjectClass *klass, const void *data)
 {
 DeviceClass *dc = DEVICE_CLASS(klass);
@@ -143,6 +220,7 @@ static const TypeInfo aspeed_sgpio_ast2700_info = {
   .name   = TYPE_ASPEED_SGPIO "-ast2700",
   .parent = TYPE_ASPEED_SGPIO,
   .class_init = aspeed_sgpio_2700_class_init,
+  .instance_init  = aspeed_sgpio_init,
 };
 
 static void aspeed_sgpio_register_types(void)

-- 
2.52.0.239.gd5f0c6e74e-goog