Re: [PATCH v3 3/3] disas: diassemble RISC-V Zbr0p93 instructions
On Wed, Mar 11, 2026 at 1:15 AM James Wainwright wrote: > > From: Emmanuel Blot > > Placed in a separate file as an unratified extension. > > Signed-off-by: James Wainwright Reviewed-by: Alistair Francis Alistair > --- > MAINTAINERS | 2 +- > disas/meson.build | 3 +- > disas/riscv-xlrbr.c | 79 + > disas/riscv-xlrbr.h | 19 +++ > disas/riscv.c | 2 ++ > 5 files changed, 103 insertions(+), 2 deletions(-) > create mode 100644 disas/riscv-xlrbr.c > create mode 100644 disas/riscv-xlrbr.h > > diff --git a/MAINTAINERS b/MAINTAINERS > index 847fd414bc..12f106f4c4 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -4154,7 +4154,7 @@ M: Alistair Francis > L: [email protected] > S: Maintained > F: tcg/riscv64/ > -F: disas/riscv.[ch] > +F: disas/riscv*.[ch] > > S390 TCG target > M: Richard Henderson > diff --git a/disas/meson.build b/disas/meson.build > index bbfa119783..42977a1f74 100644 > --- a/disas/meson.build > +++ b/disas/meson.build > @@ -7,7 +7,8 @@ common_ss.add(when: 'CONFIG_MIPS_DIS', if_true: > files('mips.c', 'nanomips.c')) > common_ss.add(when: 'CONFIG_RISCV_DIS', if_true: files( > 'riscv.c', > 'riscv-xthead.c', > -'riscv-xventana.c' > +'riscv-xventana.c', > +'riscv-xlrbr.c' > )) > common_ss.add(when: 'CONFIG_SH4_DIS', if_true: files('sh4.c')) > common_ss.add(when: 'CONFIG_SPARC_DIS', if_true: files('sparc.c')) > diff --git a/disas/riscv-xlrbr.c b/disas/riscv-xlrbr.c > new file mode 100644 > index 00..57cb434523 > --- /dev/null > +++ b/disas/riscv-xlrbr.c > @@ -0,0 +1,79 @@ > +/* > + * QEMU RISC-V Disassembler for xlrbr matching the unratified Zbr CRC32 > + * bitmanip extension v0.93. > + * > + * Copyright (c) 2023 Rivos Inc > + * > + * SPDX-License-Identifier: GPL-2.0-or-later > + */ > + > +#include "qemu/osdep.h" > + > +#include "disas/riscv.h" > +#include "disas/riscv-xlrbr.h" > + > +typedef enum { > +/* 0 is reserved for rv_op_illegal. */ > +rv_op_crc32_b = 1, > +rv_op_crc32_h = 2, > +rv_op_crc32_w = 3, > +rv_op_crc32_d = 4, > +rv_op_crc32c_b = 5, > +rv_op_crc32c_h = 6, > +rv_op_crc32c_w = 7, > +rv_op_crc32c_d = 8, > +} rv_xlrbr_op; > + > +const rv_opcode_data rv_xlrbr_opcode_data[] = { > +{ "illegal", rv_codec_illegal, rv_fmt_none, NULL, 0, 0, 0 }, > +{ "crc32.b", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, > +{ "crc32.h", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, > +{ "crc32.w", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, > +{ "crc32.d", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, > +{ "crc32c.b", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, > +{ "crc32c.h", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, > +{ "crc32c.w", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, > +{ "crc32c.d", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, > +}; > + > +void decode_xlrbr(rv_decode *dec, rv_isa isa) > +{ > +rv_inst inst = dec->inst; > +rv_opcode op = rv_op_illegal; > + > +switch ((inst >> 0) & 0b111) { > +case 0b0010011: > +switch ((inst >> 12) & 0b111) { > +case 0b001: > +switch ((inst >> 20 & 0b)) { > +case 0b0111: > +op = rv_op_crc32_b; > +break; > +case 0b01110001: > +op = rv_op_crc32_h; > +break; > +case 0b01110010: > +op = rv_op_crc32_w; > +break; > +case 0b01110011: > +op = rv_op_crc32_d; > +break; > +case 0b01111000: > +op = rv_op_crc32c_b; > +break; > +case 0b01111001: > +op = rv_op_crc32c_h; > +break; > +case 0b01111010: > +op = rv_op_crc32c_w; > +break; > +case 0b01111011: > +op = rv_op_crc32c_d; > +break; > +} > +break; > +} > +break; > +} > +dec->op = op; > +} > diff --git a/disas/riscv-xlrbr.h b/disas/riscv-xlrbr.h > new file mode 100644 > index 00..939a69ea6d > --- /dev/null > +++ b/disas/riscv-xlrbr.h > @@ -0,0 +1,19 @@ > +/* > + * QEMU RISC-V Disassembler for xlrbr matching the unratified Zbr CRC32 > + * bitmanip extension v0.93. > + * > + * Copyright (c) 2023 Rivos Inc > + * > + * SPDX-License-Identifier: GPL-2.0-or-later > + */ > + > +#ifndef DISAS_RISCV_XLRBR_H > +#define DISAS_RISCV_XLRBR_H > + > +#include "disas/riscv.h" > + > +extern const rv_opcode_data rv_xlrbr_opcode_data[]; > + > +void decode_xlrbr(rv_decode *, rv_isa); > + > +#endif /* DISAS_RISCV_XLRBR_H */ > diff --git a/disas/riscv.c b/disas/riscv.c > index 6f2667482d..d416a4d6b3 100644 > --- a/disas/riscv.c > +++ b/disas/riscv.c > @@ -26,6 +26,7 @@ > /* Vendor extensions */ > #include "disas/riscv-xthead.h" > #include "disas/riscv-xventana.h
[PATCH v3 3/3] disas: diassemble RISC-V Zbr0p93 instructions
From: Emmanuel Blot Placed in a separate file as an unratified extension. Signed-off-by: James Wainwright --- MAINTAINERS | 2 +- disas/meson.build | 3 +- disas/riscv-xlrbr.c | 79 + disas/riscv-xlrbr.h | 19 +++ disas/riscv.c | 2 ++ 5 files changed, 103 insertions(+), 2 deletions(-) create mode 100644 disas/riscv-xlrbr.c create mode 100644 disas/riscv-xlrbr.h diff --git a/MAINTAINERS b/MAINTAINERS index 847fd414bc..12f106f4c4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -4154,7 +4154,7 @@ M: Alistair Francis L: [email protected] S: Maintained F: tcg/riscv64/ -F: disas/riscv.[ch] +F: disas/riscv*.[ch] S390 TCG target M: Richard Henderson diff --git a/disas/meson.build b/disas/meson.build index bbfa119783..42977a1f74 100644 --- a/disas/meson.build +++ b/disas/meson.build @@ -7,7 +7,8 @@ common_ss.add(when: 'CONFIG_MIPS_DIS', if_true: files('mips.c', 'nanomips.c')) common_ss.add(when: 'CONFIG_RISCV_DIS', if_true: files( 'riscv.c', 'riscv-xthead.c', -'riscv-xventana.c' +'riscv-xventana.c', +'riscv-xlrbr.c' )) common_ss.add(when: 'CONFIG_SH4_DIS', if_true: files('sh4.c')) common_ss.add(when: 'CONFIG_SPARC_DIS', if_true: files('sparc.c')) diff --git a/disas/riscv-xlrbr.c b/disas/riscv-xlrbr.c new file mode 100644 index 00..57cb434523 --- /dev/null +++ b/disas/riscv-xlrbr.c @@ -0,0 +1,79 @@ +/* + * QEMU RISC-V Disassembler for xlrbr matching the unratified Zbr CRC32 + * bitmanip extension v0.93. + * + * Copyright (c) 2023 Rivos Inc + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" + +#include "disas/riscv.h" +#include "disas/riscv-xlrbr.h" + +typedef enum { +/* 0 is reserved for rv_op_illegal. */ +rv_op_crc32_b = 1, +rv_op_crc32_h = 2, +rv_op_crc32_w = 3, +rv_op_crc32_d = 4, +rv_op_crc32c_b = 5, +rv_op_crc32c_h = 6, +rv_op_crc32c_w = 7, +rv_op_crc32c_d = 8, +} rv_xlrbr_op; + +const rv_opcode_data rv_xlrbr_opcode_data[] = { +{ "illegal", rv_codec_illegal, rv_fmt_none, NULL, 0, 0, 0 }, +{ "crc32.b", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, +{ "crc32.h", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, +{ "crc32.w", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, +{ "crc32.d", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, +{ "crc32c.b", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, +{ "crc32c.h", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, +{ "crc32c.w", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, +{ "crc32c.d", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, +}; + +void decode_xlrbr(rv_decode *dec, rv_isa isa) +{ +rv_inst inst = dec->inst; +rv_opcode op = rv_op_illegal; + +switch ((inst >> 0) & 0b111) { +case 0b0010011: +switch ((inst >> 12) & 0b111) { +case 0b001: +switch ((inst >> 20 & 0b)) { +case 0b0111: +op = rv_op_crc32_b; +break; +case 0b01110001: +op = rv_op_crc32_h; +break; +case 0b01110010: +op = rv_op_crc32_w; +break; +case 0b01110011: +op = rv_op_crc32_d; +break; +case 0b01111000: +op = rv_op_crc32c_b; +break; +case 0b01111001: +op = rv_op_crc32c_h; +break; +case 0b01111010: +op = rv_op_crc32c_w; +break; +case 0b01111011: +op = rv_op_crc32c_d; +break; +} +break; +} +break; +} +dec->op = op; +} diff --git a/disas/riscv-xlrbr.h b/disas/riscv-xlrbr.h new file mode 100644 index 00..939a69ea6d --- /dev/null +++ b/disas/riscv-xlrbr.h @@ -0,0 +1,19 @@ +/* + * QEMU RISC-V Disassembler for xlrbr matching the unratified Zbr CRC32 + * bitmanip extension v0.93. + * + * Copyright (c) 2023 Rivos Inc + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef DISAS_RISCV_XLRBR_H +#define DISAS_RISCV_XLRBR_H + +#include "disas/riscv.h" + +extern const rv_opcode_data rv_xlrbr_opcode_data[]; + +void decode_xlrbr(rv_decode *, rv_isa); + +#endif /* DISAS_RISCV_XLRBR_H */ diff --git a/disas/riscv.c b/disas/riscv.c index 6f2667482d..d416a4d6b3 100644 --- a/disas/riscv.c +++ b/disas/riscv.c @@ -26,6 +26,7 @@ /* Vendor extensions */ #include "disas/riscv-xthead.h" #include "disas/riscv-xventana.h" +#include "disas/riscv-xlrbr.h" typedef enum { /* 0 is reserved for rv_op_illegal. */ @@ -5434,6 +5435,7 @@ static GString *disasm_inst(rv_isa isa, uint64_t pc, rv_inst inst, { has_xtheadmempair_p, xthead_opcode_data, decode_xtheadmempair }, { has_xtheadsync_p, xthead_opcode_data, decode_xtheadsync }, { has_XVentanaCondOps_p, ventana_opcode_data, decode_xventanacondops }, +
