Re: [PATCH v4 12/40] target/arm: Rename ARMMMUIdx*_S1E3 to ARMMMUIdx*_SE3

2019-12-04 Thread Alex Bennée 


Richard Henderson  writes:

> This is part of a reorganization to the set of mmu_idx.
> The EL3 regime only has a single stage translation, and
> is always secure.
>
> Signed-off-by: Richard Henderson 

Reviewed-by: Alex Bennée 

> ---
>  target/arm/cpu.h   |  4 ++--
>  target/arm/internals.h |  2 +-
>  target/arm/helper.c| 14 +++---
>  target/arm/translate.c |  2 +-
>  4 files changed, 11 insertions(+), 11 deletions(-)
>
> diff --git a/target/arm/cpu.h b/target/arm/cpu.h
> index e8ee316e05..f307de561a 100644
> --- a/target/arm/cpu.h
> +++ b/target/arm/cpu.h
> @@ -2867,7 +2867,7 @@ typedef enum ARMMMUIdx {
>  ARMMMUIdx_EL10_0 = 0 | ARM_MMU_IDX_A,
>  ARMMMUIdx_EL10_1 = 1 | ARM_MMU_IDX_A,
>  ARMMMUIdx_S1E2 = 2 | ARM_MMU_IDX_A,
> -ARMMMUIdx_S1E3 = 3 | ARM_MMU_IDX_A,
> +ARMMMUIdx_SE3 = 3 | ARM_MMU_IDX_A,
>  ARMMMUIdx_SE0 = 4 | ARM_MMU_IDX_A,
>  ARMMMUIdx_SE1 = 5 | ARM_MMU_IDX_A,
>  ARMMMUIdx_Stage2 = 6 | ARM_MMU_IDX_A,
> @@ -2893,7 +2893,7 @@ typedef enum ARMMMUIdxBit {
>  ARMMMUIdxBit_EL10_0 = 1 << 0,
>  ARMMMUIdxBit_EL10_1 = 1 << 1,
>  ARMMMUIdxBit_S1E2 = 1 << 2,
> -ARMMMUIdxBit_S1E3 = 1 << 3,
> +ARMMMUIdxBit_SE3 = 1 << 3,
>  ARMMMUIdxBit_SE0 = 1 << 4,
>  ARMMMUIdxBit_SE1 = 1 << 5,
>  ARMMMUIdxBit_Stage2 = 1 << 6,
> diff --git a/target/arm/internals.h b/target/arm/internals.h
> index 3600bf9122..50d258b0e1 100644
> --- a/target/arm/internals.h
> +++ b/target/arm/internals.h
> @@ -819,7 +819,7 @@ static inline bool regime_is_secure(CPUARMState *env, 
> ARMMMUIdx mmu_idx)
>  case ARMMMUIdx_MPriv:
>  case ARMMMUIdx_MUser:
>  return false;
> -case ARMMMUIdx_S1E3:
> +case ARMMMUIdx_SE3:
>  case ARMMMUIdx_SE0:
>  case ARMMMUIdx_SE1:
>  case ARMMMUIdx_MSPrivNegPri:
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index 377825431a..98d00b4549 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -3138,7 +3138,7 @@ static void ats_write(CPUARMState *env, const 
> ARMCPRegInfo *ri, uint64_t value)
>  /* stage 1 current state PL1: ATS1CPR, ATS1CPW */
>  switch (el) {
>  case 3:
> -mmu_idx = ARMMMUIdx_S1E3;
> +mmu_idx = ARMMMUIdx_SE3;
>  break;
>  case 2:
>  mmu_idx = ARMMMUIdx_Stage1_E1;
> @@ -3220,7 +3220,7 @@ static void ats_write64(CPUARMState *env, const 
> ARMCPRegInfo *ri,
>  mmu_idx = ARMMMUIdx_S1E2;
>  break;
>  case 6: /* AT S1E3R, AT S1E3W */
> -mmu_idx = ARMMMUIdx_S1E3;
> +mmu_idx = ARMMMUIdx_SE3;
>  break;
>  default:
>  g_assert_not_reached();
> @@ -3963,7 +3963,7 @@ static void tlbi_aa64_alle3_write(CPUARMState *env, 
> const ARMCPRegInfo *ri,
>  ARMCPU *cpu = env_archcpu(env);
>  CPUState *cs = CPU(cpu);
>  
> -tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_S1E3);
> +tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_SE3);
>  }
>  
>  static void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
> @@ -3988,7 +3988,7 @@ static void tlbi_aa64_alle3is_write(CPUARMState *env, 
> const ARMCPRegInfo *ri,
>  {
>  CPUState *cs = env_cpu(env);
>  
> -tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_S1E3);
> +tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_SE3);
>  }
>  
>  static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri,
> @@ -4016,7 +4016,7 @@ static void tlbi_aa64_vae3_write(CPUARMState *env, 
> const ARMCPRegInfo *ri,
>  CPUState *cs = CPU(cpu);
>  uint64_t pageaddr = sextract64(value << 12, 0, 56);
>  
> -tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S1E3);
> +tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_SE3);
>  }
>  
>  static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
> @@ -4065,7 +4065,7 @@ static void tlbi_aa64_vae3is_write(CPUARMState *env, 
> const ARMCPRegInfo *ri,
>  uint64_t pageaddr = sextract64(value << 12, 0, 56);
>  
>  tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr,
> - ARMMMUIdxBit_S1E3);
> + ARMMMUIdxBit_SE3);
>  }
>  
>  static void tlbi_aa64_ipas2e1_write(CPUARMState *env, const ARMCPRegInfo *ri,
> @@ -8567,7 +8567,7 @@ static inline uint32_t regime_el(CPUARMState *env, 
> ARMMMUIdx mmu_idx)
>  case ARMMMUIdx_Stage2:
>  case ARMMMUIdx_S1E2:
>  return 2;
> -case ARMMMUIdx_S1E3:
> +case ARMMMUIdx_SE3:
>  return 3;
>  case ARMMMUIdx_SE0:
>  return arm_el_is_aa64(env, 3) ? 1 : 3;
> diff --git a/target/arm/translate.c b/target/arm/translate.c
> index 787e34f258..6cf2fe2806 100644
> --- a/target/arm/translate.c
> +++ b/target/arm/translate.c
> @@ -156,7 +156,7 @@ static inline int get_a32_user_mem_index(DisasContext *s)
>  case ARMMMUIdx_EL10_0:
>  case ARMMMUIdx_EL10_1:
>  return arm_to_core_mmu_idx(ARMMMUIdx_EL10_0);
> -

[PATCH v4 12/40] target/arm: Rename ARMMMUIdx*_S1E3 to ARMMMUIdx*_SE3

2019-12-02 Thread Richard Henderson 
This is part of a reorganization to the set of mmu_idx.
The EL3 regime only has a single stage translation, and
is always secure.

Signed-off-by: Richard Henderson 
---
 target/arm/cpu.h   |  4 ++--
 target/arm/internals.h |  2 +-
 target/arm/helper.c| 14 +++---
 target/arm/translate.c |  2 +-
 4 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index e8ee316e05..f307de561a 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -2867,7 +2867,7 @@ typedef enum ARMMMUIdx {
 ARMMMUIdx_EL10_0 = 0 | ARM_MMU_IDX_A,
 ARMMMUIdx_EL10_1 = 1 | ARM_MMU_IDX_A,
 ARMMMUIdx_S1E2 = 2 | ARM_MMU_IDX_A,
-ARMMMUIdx_S1E3 = 3 | ARM_MMU_IDX_A,
+ARMMMUIdx_SE3 = 3 | ARM_MMU_IDX_A,
 ARMMMUIdx_SE0 = 4 | ARM_MMU_IDX_A,
 ARMMMUIdx_SE1 = 5 | ARM_MMU_IDX_A,
 ARMMMUIdx_Stage2 = 6 | ARM_MMU_IDX_A,
@@ -2893,7 +2893,7 @@ typedef enum ARMMMUIdxBit {
 ARMMMUIdxBit_EL10_0 = 1 << 0,
 ARMMMUIdxBit_EL10_1 = 1 << 1,
 ARMMMUIdxBit_S1E2 = 1 << 2,
-ARMMMUIdxBit_S1E3 = 1 << 3,
+ARMMMUIdxBit_SE3 = 1 << 3,
 ARMMMUIdxBit_SE0 = 1 << 4,
 ARMMMUIdxBit_SE1 = 1 << 5,
 ARMMMUIdxBit_Stage2 = 1 << 6,
diff --git a/target/arm/internals.h b/target/arm/internals.h
index 3600bf9122..50d258b0e1 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -819,7 +819,7 @@ static inline bool regime_is_secure(CPUARMState *env, 
ARMMMUIdx mmu_idx)
 case ARMMMUIdx_MPriv:
 case ARMMMUIdx_MUser:
 return false;
-case ARMMMUIdx_S1E3:
+case ARMMMUIdx_SE3:
 case ARMMMUIdx_SE0:
 case ARMMMUIdx_SE1:
 case ARMMMUIdx_MSPrivNegPri:
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 377825431a..98d00b4549 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -3138,7 +3138,7 @@ static void ats_write(CPUARMState *env, const 
ARMCPRegInfo *ri, uint64_t value)
 /* stage 1 current state PL1: ATS1CPR, ATS1CPW */
 switch (el) {
 case 3:
-mmu_idx = ARMMMUIdx_S1E3;
+mmu_idx = ARMMMUIdx_SE3;
 break;
 case 2:
 mmu_idx = ARMMMUIdx_Stage1_E1;
@@ -3220,7 +3220,7 @@ static void ats_write64(CPUARMState *env, const 
ARMCPRegInfo *ri,
 mmu_idx = ARMMMUIdx_S1E2;
 break;
 case 6: /* AT S1E3R, AT S1E3W */
-mmu_idx = ARMMMUIdx_S1E3;
+mmu_idx = ARMMMUIdx_SE3;
 break;
 default:
 g_assert_not_reached();
@@ -3963,7 +3963,7 @@ static void tlbi_aa64_alle3_write(CPUARMState *env, const 
ARMCPRegInfo *ri,
 ARMCPU *cpu = env_archcpu(env);
 CPUState *cs = CPU(cpu);
 
-tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_S1E3);
+tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_SE3);
 }
 
 static void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -3988,7 +3988,7 @@ static void tlbi_aa64_alle3is_write(CPUARMState *env, 
const ARMCPRegInfo *ri,
 {
 CPUState *cs = env_cpu(env);
 
-tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_S1E3);
+tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_SE3);
 }
 
 static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -4016,7 +4016,7 @@ static void tlbi_aa64_vae3_write(CPUARMState *env, const 
ARMCPRegInfo *ri,
 CPUState *cs = CPU(cpu);
 uint64_t pageaddr = sextract64(value << 12, 0, 56);
 
-tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S1E3);
+tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_SE3);
 }
 
 static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -4065,7 +4065,7 @@ static void tlbi_aa64_vae3is_write(CPUARMState *env, 
const ARMCPRegInfo *ri,
 uint64_t pageaddr = sextract64(value << 12, 0, 56);
 
 tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr,
- ARMMMUIdxBit_S1E3);
+ ARMMMUIdxBit_SE3);
 }
 
 static void tlbi_aa64_ipas2e1_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -8567,7 +8567,7 @@ static inline uint32_t regime_el(CPUARMState *env, 
ARMMMUIdx mmu_idx)
 case ARMMMUIdx_Stage2:
 case ARMMMUIdx_S1E2:
 return 2;
-case ARMMMUIdx_S1E3:
+case ARMMMUIdx_SE3:
 return 3;
 case ARMMMUIdx_SE0:
 return arm_el_is_aa64(env, 3) ? 1 : 3;
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 787e34f258..6cf2fe2806 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -156,7 +156,7 @@ static inline int get_a32_user_mem_index(DisasContext *s)
 case ARMMMUIdx_EL10_0:
 case ARMMMUIdx_EL10_1:
 return arm_to_core_mmu_idx(ARMMMUIdx_EL10_0);
-case ARMMMUIdx_S1E3:
+case ARMMMUIdx_SE3:
 case ARMMMUIdx_SE0:
 case ARMMMUIdx_SE1:
 return arm_to_core_mmu_idx(ARMMMUIdx_SE0);
-- 
2.17.1