NPCM8XX adds a few new registers and have a different set of reset
values to the CLK modules. This patch supports them.
This patch doesn't support the new clock values generated by these
registers. Currently no modules use these new clock values so they
are not necessary at this point.
Implementation of these clocks might be required when implementing
these modules.
Reviewed-by: Titus Rwantare
Reviewed-by: Peter Maydell
Signed-off-by: Hao Wu
---
hw/misc/npcm_clk.c | 113 +++--
include/hw/misc/npcm_clk.h | 10 +++-
2 files changed, 117 insertions(+), 6 deletions(-)
diff --git a/hw/misc/npcm_clk.c b/hw/misc/npcm_clk.c
index 78144b14e3..97559d4d07 100644
--- a/hw/misc/npcm_clk.c
+++ b/hw/misc/npcm_clk.c
@@ -1,5 +1,5 @@
/*
- * Nuvoton NPCM7xx Clock Control Registers.
+ * Nuvoton NPCM7xx/8xx Clock Control Registers.
*
* Copyright 2020 Google LLC
*
@@ -72,7 +72,57 @@ enum NPCM7xxCLKRegisters {
NPCM7XX_CLK_AHBCKFI,
NPCM7XX_CLK_SECCNT,
NPCM7XX_CLK_CNTR25M,
-NPCM7XX_CLK_REGS_END,
+};
+
+enum NPCM8xxCLKRegisters {
+NPCM8XX_CLK_CLKEN1,
+NPCM8XX_CLK_CLKSEL,
+NPCM8XX_CLK_CLKDIV1,
+NPCM8XX_CLK_PLLCON0,
+NPCM8XX_CLK_PLLCON1,
+NPCM8XX_CLK_SWRSTR,
+NPCM8XX_CLK_IPSRST1 = 0x20 / sizeof(uint32_t),
+NPCM8XX_CLK_IPSRST2,
+NPCM8XX_CLK_CLKEN2,
+NPCM8XX_CLK_CLKDIV2,
+NPCM8XX_CLK_CLKEN3,
+NPCM8XX_CLK_IPSRST3,
+NPCM8XX_CLK_WD0RCR,
+NPCM8XX_CLK_WD1RCR,
+NPCM8XX_CLK_WD2RCR,
+NPCM8XX_CLK_SWRSTC1,
+NPCM8XX_CLK_SWRSTC2,
+NPCM8XX_CLK_SWRSTC3,
+NPCM8XX_CLK_TIPRSTC,
+NPCM8XX_CLK_PLLCON2,
+NPCM8XX_CLK_CLKDIV3,
+NPCM8XX_CLK_CORSTC,
+NPCM8XX_CLK_PLLCONG,
+NPCM8XX_CLK_AHBCKFI,
+NPCM8XX_CLK_SECCNT,
+NPCM8XX_CLK_CNTR25M,
+/* Registers unique to NPCM8XX SoC */
+NPCM8XX_CLK_CLKEN4,
+NPCM8XX_CLK_IPSRST4,
+NPCM8XX_CLK_BUSTO,
+NPCM8XX_CLK_CLKDIV4,
+NPCM8XX_CLK_WD0RCRB,
+NPCM8XX_CLK_WD1RCRB,
+NPCM8XX_CLK_WD2RCRB,
+NPCM8XX_CLK_SWRSTC1B,
+NPCM8XX_CLK_SWRSTC2B,
+NPCM8XX_CLK_SWRSTC3B,
+NPCM8XX_CLK_TIPRSTCB,
+NPCM8XX_CLK_CORSTCB,
+NPCM8XX_CLK_IPSRSTDIS1,
+NPCM8XX_CLK_IPSRSTDIS2,
+NPCM8XX_CLK_IPSRSTDIS3,
+NPCM8XX_CLK_IPSRSTDIS4,
+NPCM8XX_CLK_CLKENDIS1,
+NPCM8XX_CLK_CLKENDIS2,
+NPCM8XX_CLK_CLKENDIS3,
+NPCM8XX_CLK_CLKENDIS4,
+NPCM8XX_CLK_THRTL_CNT,
};
/*
@@ -103,6 +153,46 @@ static const uint32_t
npcm7xx_cold_reset_values[NPCM7XX_CLK_NR_REGS] = {
[NPCM7XX_CLK_AHBCKFI] = 0x00c8,
};
+/*
+ * These reset values were taken from version 0.92 of the NPCM8xx data sheet.
+ */
+static const uint32_t npcm8xx_cold_reset_values[NPCM8XX_CLK_NR_REGS] = {
+[NPCM8XX_CLK_CLKEN1]= 0x,
+[NPCM8XX_CLK_CLKSEL]= 0x154a,
+[NPCM8XX_CLK_CLKDIV1] = 0x5413f855,
+[NPCM8XX_CLK_PLLCON0] = 0x00222101 | PLLCON_LOKI,
+[NPCM8XX_CLK_PLLCON1] = 0x00202101 | PLLCON_LOKI,
+[NPCM8XX_CLK_IPSRST1] = 0x1000,
+[NPCM8XX_CLK_IPSRST2] = 0x8000,
+[NPCM8XX_CLK_CLKEN2]= 0x,
+[NPCM8XX_CLK_CLKDIV2] = 0xaa4f8f9f,
+[NPCM8XX_CLK_CLKEN3]= 0x,
+[NPCM8XX_CLK_IPSRST3] = 0x0300,
+[NPCM8XX_CLK_WD0RCR]= 0x,
+[NPCM8XX_CLK_WD1RCR]= 0x,
+[NPCM8XX_CLK_WD2RCR]= 0x,
+[NPCM8XX_CLK_SWRSTC1] = 0x0003,
+[NPCM8XX_CLK_SWRSTC2] = 0x0001,
+[NPCM8XX_CLK_SWRSTC3] = 0x0001,
+[NPCM8XX_CLK_TIPRSTC] = 0x0001,
+[NPCM8XX_CLK_PLLCON2] = 0x00c02105 | PLLCON_LOKI,
+[NPCM8XX_CLK_CLKDIV3] = 0x9100,
+[NPCM8XX_CLK_CORSTC]= 0x0403,
+[NPCM8XX_CLK_PLLCONG] = 0x01228606 | PLLCON_LOKI,
+[NPCM8XX_CLK_AHBCKFI] = 0x00c8,
+[NPCM8XX_CLK_CLKEN4]= 0x,
+[NPCM8XX_CLK_CLKDIV4] = 0x70009000,
+[NPCM8XX_CLK_IPSRST4] = 0x0200,
+[NPCM8XX_CLK_WD0RCRB] = 0xfe71,
+[NPCM8XX_CLK_WD1RCRB] = 0xfe71,
+[NPCM8XX_CLK_WD2RCRB] = 0xfe71,
+[NPCM8XX_CLK_SWRSTC1B] = 0xfe71,
+[NPCM8XX_CLK_SWRSTC2B] = 0xfe71,
+[NPCM8XX_CLK_SWRSTC3B] = 0xfe71,
+[NPCM8XX_CLK_TIPRSTCB] = 0xfe71,
+[NPCM8XX_CLK_CORSTCB] = 0xfe71,
+};
+
/* The number of watchdogs that can trigger a reset. */
#define NPCM7XX_NR_WATCHDOGS(3)
@@ -1050,13 +1140,21 @@ static void npcm7xx_clk_class_init(ObjectClass *klass,
void *data)
NPCMCLKClass *c = NPCM_CLK_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
-QEMU_BUILD_BUG_ON(NPCM7XX_CLK_REGS_END > NPCM_CLK_MAX_NR_REGS);
-QEMU_BUILD_BUG_ON(NPCM7XX_CLK_REGS_END != NPCM7XX_CLK_NR_REGS);
dc->desc = "NPCM7xx Clock Control Registers";
c->nr_regs = NPCM7XX_CLK_NR_REGS;
c->cold_reset_values = npcm7xx_cold_reset_values;
}
+static void npcm8xx_clk_class_init(ObjectCla
