Re: [PATCH v4 148/163] tcg/tci: Remove support for add2/sub2

2025-04-16 Thread Pierrick Bouvier 

On 4/15/25 12:24, Richard Henderson wrote:

Signed-off-by: Richard Henderson 
---
  tcg/tci/tcg-target-has.h |  8 ++---
  tcg/tci.c| 66 +++-
  tcg/tci/tcg-target.c.inc | 28 -
  3 files changed, 9 insertions(+), 93 deletions(-)

diff --git a/tcg/tci/tcg-target-has.h b/tcg/tci/tcg-target-has.h
index 6063f32f7b..310d45ba62 100644
--- a/tcg/tci/tcg-target-has.h
+++ b/tcg/tci/tcg-target-has.h
@@ -8,13 +8,13 @@
  #define TCG_TARGET_HAS_H
  
  #define TCG_TARGET_HAS_qemu_st8_i32 0

-#define TCG_TARGET_HAS_add2_i32 1
-#define TCG_TARGET_HAS_sub2_i32 1
+#define TCG_TARGET_HAS_add2_i32 0
+#define TCG_TARGET_HAS_sub2_i32 0
  
  #if TCG_TARGET_REG_BITS == 64

  #define TCG_TARGET_HAS_extr_i64_i32 0
-#define TCG_TARGET_HAS_add2_i64 1
-#define TCG_TARGET_HAS_sub2_i64 1
+#define TCG_TARGET_HAS_add2_i64 0
+#define TCG_TARGET_HAS_sub2_i64 0
  #endif /* TCG_TARGET_REG_BITS == 64 */
  
  #define TCG_TARGET_HAS_qemu_ldst_i128   0

diff --git a/tcg/tci.c b/tcg/tci.c
index d65ff2b8f1..a18478a07a 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -179,17 +179,6 @@ static void tci_args_rc(uint32_t insn, TCGReg *r0, 
TCGReg *r1,
  *c5 = extract32(insn, 28, 4);
  }
  
-static void tci_args_rr(uint32_t insn, TCGReg *r0, TCGReg *r1,

-TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGReg *r5)
-{
-*r0 = extract32(insn, 8, 4);
-*r1 = extract32(insn, 12, 4);
-*r2 = extract32(insn, 16, 4);
-*r3 = extract32(insn, 20, 4);
-*r4 = extract32(insn, 24, 4);
-*r5 = extract32(insn, 28, 4);
-}
-
  static bool tci_compare32(uint32_t u0, uint32_t u1, TCGCond condition)
  {
  bool result = false;
@@ -370,13 +359,12 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState 
*env,
  for (;;) {
  uint32_t insn;
  TCGOpcode opc;
-TCGReg r0, r1, r2, r3, r4, r5;
+TCGReg r0, r1, r2, r3, r4;
  tcg_target_ulong t1;
  TCGCond condition;
  uint8_t pos, len;
  uint32_t tmp32;
  uint64_t tmp64, taddr;
-uint64_t T1, T2;
  MemOpIdx oi;
  int32_t ofs;
  void *ptr;
@@ -445,9 +433,9 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState 
*env,
  #if TCG_TARGET_REG_BITS == 32
  case INDEX_op_setcond2_i32:
  tci_args_rc(insn, &r0, &r1, &r2, &r3, &r4, &condition);
-T1 = tci_uint64(regs[r2], regs[r1]);
-T2 = tci_uint64(regs[r4], regs[r3]);
-regs[r0] = tci_compare64(T1, T2, condition);
+regs[r0] = tci_compare64(tci_uint64(regs[r2], regs[r1]),
+ tci_uint64(regs[r4], regs[r3]),
+ condition);
  break;
  #elif TCG_TARGET_REG_BITS == 64
  case INDEX_op_setcond:
@@ -717,22 +705,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState 
*env,
  tb_ptr = ptr;
  }
  break;
-#if TCG_TARGET_REG_BITS == 32 || TCG_TARGET_HAS_add2_i32
-case INDEX_op_add2_i32:
-tci_args_rr(insn, &r0, &r1, &r2, &r3, &r4, &r5);
-T1 = tci_uint64(regs[r3], regs[r2]);
-T2 = tci_uint64(regs[r5], regs[r4]);
-tci_write_reg64(regs, r1, r0, T1 + T2);
-break;
-#endif
-#if TCG_TARGET_REG_BITS == 32 || TCG_TARGET_HAS_sub2_i32
-case INDEX_op_sub2_i32:
-tci_args_rr(insn, &r0, &r1, &r2, &r3, &r4, &r5);
-T1 = tci_uint64(regs[r3], regs[r2]);
-T2 = tci_uint64(regs[r5], regs[r4]);
-tci_write_reg64(regs, r1, r0, T1 - T2);
-break;
-#endif
  case INDEX_op_bswap16:
  tci_args_rr(insn, &r0, &r1);
  regs[r0] = bswap16(regs[r1]);
@@ -786,24 +758,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState 
*env,
  tci_args_rrr(insn, &r0, &r1, &r2);
  regs[r0] = regs[r1] ? ctz64(regs[r1]) : regs[r2];
  break;
-#if TCG_TARGET_HAS_add2_i64
-case INDEX_op_add2_i64:
-tci_args_rr(insn, &r0, &r1, &r2, &r3, &r4, &r5);
-T1 = regs[r2] + regs[r4];
-T2 = regs[r3] + regs[r5] + (T1 < regs[r2]);
-regs[r0] = T1;
-regs[r1] = T2;
-break;
-#endif
-#if TCG_TARGET_HAS_add2_i64
-case INDEX_op_sub2_i64:
-tci_args_rr(insn, &r0, &r1, &r2, &r3, &r4, &r5);
-T1 = regs[r2] - regs[r4];
-T2 = regs[r3] - regs[r5] - (regs[r2] < regs[r4]);
-regs[r0] = T1;
-regs[r1] = T2;
-break;
-#endif
  
  /* Shift/rotate operations (64 bit). */
  
@@ -952,7 +906,7 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info)

  const char *op_name;
  uint32_t insn;
  TCGOpcode op;
-TCGReg r0, r1, r2, r3, r4, r5;
+TCGReg r0, r1, r2, r3, r4;
  tcg_target_ulong i1;

[PATCH v4 148/163] tcg/tci: Remove support for add2/sub2

2025-04-15 Thread Richard Henderson 
Signed-off-by: Richard Henderson 
---
 tcg/tci/tcg-target-has.h |  8 ++---
 tcg/tci.c| 66 +++-
 tcg/tci/tcg-target.c.inc | 28 -
 3 files changed, 9 insertions(+), 93 deletions(-)

diff --git a/tcg/tci/tcg-target-has.h b/tcg/tci/tcg-target-has.h
index 6063f32f7b..310d45ba62 100644
--- a/tcg/tci/tcg-target-has.h
+++ b/tcg/tci/tcg-target-has.h
@@ -8,13 +8,13 @@
 #define TCG_TARGET_HAS_H
 
 #define TCG_TARGET_HAS_qemu_st8_i32 0
-#define TCG_TARGET_HAS_add2_i32 1
-#define TCG_TARGET_HAS_sub2_i32 1
+#define TCG_TARGET_HAS_add2_i32 0
+#define TCG_TARGET_HAS_sub2_i32 0
 
 #if TCG_TARGET_REG_BITS == 64
 #define TCG_TARGET_HAS_extr_i64_i32 0
-#define TCG_TARGET_HAS_add2_i64 1
-#define TCG_TARGET_HAS_sub2_i64 1
+#define TCG_TARGET_HAS_add2_i64 0
+#define TCG_TARGET_HAS_sub2_i64 0
 #endif /* TCG_TARGET_REG_BITS == 64 */
 
 #define TCG_TARGET_HAS_qemu_ldst_i128   0
diff --git a/tcg/tci.c b/tcg/tci.c
index d65ff2b8f1..a18478a07a 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -179,17 +179,6 @@ static void tci_args_rc(uint32_t insn, TCGReg *r0, 
TCGReg *r1,
 *c5 = extract32(insn, 28, 4);
 }
 
-static void tci_args_rr(uint32_t insn, TCGReg *r0, TCGReg *r1,
-TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGReg *r5)
-{
-*r0 = extract32(insn, 8, 4);
-*r1 = extract32(insn, 12, 4);
-*r2 = extract32(insn, 16, 4);
-*r3 = extract32(insn, 20, 4);
-*r4 = extract32(insn, 24, 4);
-*r5 = extract32(insn, 28, 4);
-}
-
 static bool tci_compare32(uint32_t u0, uint32_t u1, TCGCond condition)
 {
 bool result = false;
@@ -370,13 +359,12 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState 
*env,
 for (;;) {
 uint32_t insn;
 TCGOpcode opc;
-TCGReg r0, r1, r2, r3, r4, r5;
+TCGReg r0, r1, r2, r3, r4;
 tcg_target_ulong t1;
 TCGCond condition;
 uint8_t pos, len;
 uint32_t tmp32;
 uint64_t tmp64, taddr;
-uint64_t T1, T2;
 MemOpIdx oi;
 int32_t ofs;
 void *ptr;
@@ -445,9 +433,9 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState 
*env,
 #if TCG_TARGET_REG_BITS == 32
 case INDEX_op_setcond2_i32:
 tci_args_rc(insn, &r0, &r1, &r2, &r3, &r4, &condition);
-T1 = tci_uint64(regs[r2], regs[r1]);
-T2 = tci_uint64(regs[r4], regs[r3]);
-regs[r0] = tci_compare64(T1, T2, condition);
+regs[r0] = tci_compare64(tci_uint64(regs[r2], regs[r1]),
+ tci_uint64(regs[r4], regs[r3]),
+ condition);
 break;
 #elif TCG_TARGET_REG_BITS == 64
 case INDEX_op_setcond:
@@ -717,22 +705,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState 
*env,
 tb_ptr = ptr;
 }
 break;
-#if TCG_TARGET_REG_BITS == 32 || TCG_TARGET_HAS_add2_i32
-case INDEX_op_add2_i32:
-tci_args_rr(insn, &r0, &r1, &r2, &r3, &r4, &r5);
-T1 = tci_uint64(regs[r3], regs[r2]);
-T2 = tci_uint64(regs[r5], regs[r4]);
-tci_write_reg64(regs, r1, r0, T1 + T2);
-break;
-#endif
-#if TCG_TARGET_REG_BITS == 32 || TCG_TARGET_HAS_sub2_i32
-case INDEX_op_sub2_i32:
-tci_args_rr(insn, &r0, &r1, &r2, &r3, &r4, &r5);
-T1 = tci_uint64(regs[r3], regs[r2]);
-T2 = tci_uint64(regs[r5], regs[r4]);
-tci_write_reg64(regs, r1, r0, T1 - T2);
-break;
-#endif
 case INDEX_op_bswap16:
 tci_args_rr(insn, &r0, &r1);
 regs[r0] = bswap16(regs[r1]);
@@ -786,24 +758,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState 
*env,
 tci_args_rrr(insn, &r0, &r1, &r2);
 regs[r0] = regs[r1] ? ctz64(regs[r1]) : regs[r2];
 break;
-#if TCG_TARGET_HAS_add2_i64
-case INDEX_op_add2_i64:
-tci_args_rr(insn, &r0, &r1, &r2, &r3, &r4, &r5);
-T1 = regs[r2] + regs[r4];
-T2 = regs[r3] + regs[r5] + (T1 < regs[r2]);
-regs[r0] = T1;
-regs[r1] = T2;
-break;
-#endif
-#if TCG_TARGET_HAS_add2_i64
-case INDEX_op_sub2_i64:
-tci_args_rr(insn, &r0, &r1, &r2, &r3, &r4, &r5);
-T1 = regs[r2] - regs[r4];
-T2 = regs[r3] - regs[r5] - (regs[r2] < regs[r4]);
-regs[r0] = T1;
-regs[r1] = T2;
-break;
-#endif
 
 /* Shift/rotate operations (64 bit). */
 
@@ -952,7 +906,7 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info)
 const char *op_name;
 uint32_t insn;
 TCGOpcode op;
-TCGReg r0, r1, r2, r3, r4, r5;
+TCGReg r0, r1, r2, r3, r4;
 tcg_target_ulong i1;
 int32_t s2;
 TCGCond c;
@@ -1125,16 +1079,6 @@ int print_insn_tci(bfd_vma addr, disassemble_info *i