Signed-off-by: Hao Wu
---
configs/devices/aarch64-softmmu/default.mak | 1 +
hw/arm/Kconfig | 13 +
hw/arm/meson.build | 1 +
hw/arm/npcm8xx.c| 804
include/hw/arm/npcm8xx.h| 107 +++
5 files changed, 926 insertions(+)
create mode 100644 hw/arm/npcm8xx.c
create mode 100644 include/hw/arm/npcm8xx.h
diff --git a/configs/devices/aarch64-softmmu/default.mak
b/configs/devices/aarch64-softmmu/default.mak
index f82a04c27d..93f4022ad6 100644
--- a/configs/devices/aarch64-softmmu/default.mak
+++ b/configs/devices/aarch64-softmmu/default.mak
@@ -8,3 +8,4 @@ include ../arm-softmmu/default.mak
# CONFIG_XLNX_ZYNQMP_ARM=n
# CONFIG_XLNX_VERSAL=n
# CONFIG_SBSA_REF=n
+# CONFIG_NPCM8XX=n
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index 256013ca80..6f4b0020ca 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -481,6 +481,19 @@ config NPCM7XX
select PCA954X
select USB_OHCI_SYSBUS
+config NPCM8XX
+bool
+default y
+depends on TCG && AARCH64
+select ARM_GIC
+select SMBUS
+select PL310 # cache controller
+select NPCM7XX
+select SERIAL
+select SSI
+select UNIMP
+
+
config FSL_IMX25
bool
default y
diff --git a/hw/arm/meson.build b/hw/arm/meson.build
index 490234b3b8..d7813c089c 100644
--- a/hw/arm/meson.build
+++ b/hw/arm/meson.build
@@ -12,6 +12,7 @@ arm_ss.add(when: 'CONFIG_MUSICPAL', if_true:
files('musicpal.c'))
arm_ss.add(when: 'CONFIG_NETDUINOPLUS2', if_true: files('netduinoplus2.c'))
arm_ss.add(when: 'CONFIG_OLIMEX_STM32_H405', if_true:
files('olimex-stm32-h405.c'))
arm_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx.c',
'npcm7xx_boards.c'))
+arm_ss.add(when: 'CONFIG_NPCM8XX', if_true: files('npcm8xx.c'))
arm_ss.add(when: 'CONFIG_REALVIEW', if_true: files('realview.c'))
arm_ss.add(when: 'CONFIG_SBSA_REF', if_true: files('sbsa-ref.c'))
arm_ss.add(when: 'CONFIG_STELLARIS', if_true: files('stellaris.c'))
diff --git a/hw/arm/npcm8xx.c b/hw/arm/npcm8xx.c
new file mode 100644
index 00..86f0360425
--- /dev/null
+++ b/hw/arm/npcm8xx.c
@@ -0,0 +1,804 @@
+/*
+ * Nuvoton NPCM8xx SoC family.
+ *
+ * Copyright 2022 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#include "qemu/osdep.h"
+
+#include "hw/arm/boot.h"
+#include "hw/arm/bsa.h"
+#include "hw/arm/npcm8xx.h"
+#include "hw/char/serial-mm.h"
+#include "hw/intc/arm_gic.h"
+#include "hw/loader.h"
+#include "hw/misc/unimp.h"
+#include "hw/qdev-clock.h"
+#include "hw/qdev-properties.h"
+#include "qapi/error.h"
+#include "qemu/units.h"
+#include "system/system.h"
+
+/*
+ * This covers the whole MMIO space. We'll use this to catch any MMIO accesses
+ * that aren't handled by a device.
+ */
+#define NPCM8XX_MMIO_BA 0x8000
+#define NPCM8XX_MMIO_SZ 0x7ffd
+
+/* OTP fuse array */
+#define NPCM8XX_OTP_BA 0xf0189000
+
+/* GIC Distributor */
+#define NPCM8XX_GICD_BA 0xdfff9000
+#define NPCM8XX_GICC_BA 0xdfffa000
+
+/* Core system modules. */
+#define NPCM8XX_CPUP_BA 0xf03fe000
+#define NPCM8XX_GCR_BA 0xf080
+#define NPCM8XX_CLK_BA 0xf0801000
+#define NPCM8XX_MC_BA 0xf0824000
+#define NPCM8XX_RNG_BA 0xf000b000
+
+/* ADC Module */
+#define NPCM8XX_ADC_BA 0xf000c000
+
+/* Internal AHB SRAM */
+#define NPCM8XX_RAM3_BA 0xc0008000
+#define NPCM8XX_RAM3_SZ (4 * KiB)
+
+/* Memory blocks at the end of the address space */
+#define NPCM8XX_RAM2_BA 0xfffb
+#define NPCM8XX_RAM2_SZ (256 * KiB)
+#define NPCM8XX_ROM_BA 0x0100
+#define NPCM8XX_ROM_SZ (64 * KiB)
+
+/* SDHCI Modules */
+#define NPCM8XX_MMC_BA 0xf0842000
+
+/* Run PLL1 at 1600 MHz */
+#define NPCM8XX_PLLCON1_FIXUP_VAL 0x00402101
+/* Run the CPU from PLL1 and UART from PLL2 */
+#define NPCM8XX_CLKSEL_FIXUP_VAL0x004aaba9
+
+/* Clock configuration values to be fixed up when bypassing bootloader */
+
+/*
+ * Interrupt lines going into the GIC. This does not include internal
Cortex-A35
+ * interrupts.
+ */
+enum NPCM8xxInterrupt {
+NPCM8XX_ADC_IRQ = 0,
+NPCM8XX_PECI_IRQ= 6,
+NPCM8XX_KCS_HIB_IRQ = 9,
+NPCM8XX_MMC_IRQ = 26,
+NPCM8XX_TIMER0_IRQ = 32, /* Timer Module 0 */
+NPCM8XX_TIMER1_IRQ,
+NPCM8XX_TIMER2_IRQ,
+NPCM8XX_TIMER3_IRQ,
+NPCM8XX_TIMER4_IRQ,
+NPCM8XX_TIMER5_IRQ,
