Re: [PATCH v4 159/163] tcg: Remove INDEX_op_qemu_st8_*

2025-04-16 Thread Pierrick Bouvier 

On 4/15/25 12:25, Richard Henderson wrote:

The i386 backend can now check TCGOP_FLAGS to select
the correct set of constraints.

Signed-off-by: Richard Henderson 
---
  include/tcg/tcg-opc.h| 4 
  tcg/aarch64/tcg-target-has.h | 1 -
  tcg/arm/tcg-target-has.h | 1 -
  tcg/i386/tcg-target-con-str.h| 2 +-
  tcg/i386/tcg-target-has.h| 3 ---
  tcg/loongarch64/tcg-target-has.h | 3 ---
  tcg/mips/tcg-target-has.h| 1 -
  tcg/ppc/tcg-target-has.h | 2 --
  tcg/riscv/tcg-target-has.h   | 1 -
  tcg/s390x/tcg-target-has.h   | 1 -
  tcg/sparc64/tcg-target-has.h | 1 -
  tcg/tci/tcg-target-has.h | 2 --
  tcg/optimize.c   | 1 -
  tcg/tcg-op-ldst.c| 9 ++---
  tcg/tcg.c| 4 
  docs/devel/tcg-ops.rst   | 6 --
  tcg/i386/tcg-target.c.inc| 9 -
  17 files changed, 7 insertions(+), 44 deletions(-)

diff --git a/include/tcg/tcg-opc.h b/include/tcg/tcg-opc.h
index a22433d8b5..0ce8332aab 100644
--- a/include/tcg/tcg-opc.h
+++ b/include/tcg/tcg-opc.h
@@ -133,10 +133,6 @@ DEF(qemu_ld_i64, DATA64_ARGS, 1, 1,
  DEF(qemu_st_i64, 0, DATA64_ARGS + 1, 1,
  TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
  
-/* Only used by i386 to cope with stupid register constraints. */

-DEF(qemu_st8_i32, 0, 1 + 1, 1,
-TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
-
  /* Only for 64-bit hosts at the moment. */
  DEF(qemu_ld_i128, 2, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
  DEF(qemu_st_i128, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
diff --git a/tcg/aarch64/tcg-target-has.h b/tcg/aarch64/tcg-target-has.h
index b155e37639..69e83efb69 100644
--- a/tcg/aarch64/tcg-target-has.h
+++ b/tcg/aarch64/tcg-target-has.h
@@ -14,7 +14,6 @@
  
  /* optional instructions */

  #define TCG_TARGET_HAS_extr_i64_i32 0
-#define TCG_TARGET_HAS_qemu_st8_i32 0
  
  /*

   * Without FEAT_LSE2, we must use LDXP+STXP to implement atomic 128-bit load,
diff --git a/tcg/arm/tcg-target-has.h b/tcg/arm/tcg-target-has.h
index 187269e5bd..3bbbde5d59 100644
--- a/tcg/arm/tcg-target-has.h
+++ b/tcg/arm/tcg-target-has.h
@@ -24,7 +24,6 @@ extern bool use_neon_instructions;
  #endif
  
  /* optional instructions */

-#define TCG_TARGET_HAS_qemu_st8_i32 0
  #define TCG_TARGET_HAS_qemu_ldst_i128   0
  #define TCG_TARGET_HAS_tst  1
  
diff --git a/tcg/i386/tcg-target-con-str.h b/tcg/i386/tcg-target-con-str.h

index 52142ab121..dbedff1f54 100644
--- a/tcg/i386/tcg-target-con-str.h
+++ b/tcg/i386/tcg-target-con-str.h
@@ -20,7 +20,7 @@ REGS('r', ALL_GENERAL_REGS)
  REGS('x', ALL_VECTOR_REGS)
  REGS('q', ALL_BYTEL_REGS) /* regs that can be used as a byte operand */
  REGS('L', ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS)  /* qemu_ld/st */
-REGS('s', ALL_BYTEL_REGS & ~SOFTMMU_RESERVE_REGS)/* qemu_st8_i32 data */
+REGS('s', ALL_BYTEL_REGS & ~SOFTMMU_RESERVE_REGS)/* qemu_st MO_8 data */
  
  /*

   * Define constraint letters for constants:
diff --git a/tcg/i386/tcg-target-has.h b/tcg/i386/tcg-target-has.h
index 628e736de7..42647fabbd 100644
--- a/tcg/i386/tcg-target-has.h
+++ b/tcg/i386/tcg-target-has.h
@@ -29,9 +29,6 @@
  #if TCG_TARGET_REG_BITS == 64
  /* Keep 32-bit values zero-extended in a register.  */
  #define TCG_TARGET_HAS_extr_i64_i32 1
-#define TCG_TARGET_HAS_qemu_st8_i32 0
-#else
-#define TCG_TARGET_HAS_qemu_st8_i32 1
  #endif
  
  #define TCG_TARGET_HAS_qemu_ldst_i128 \

diff --git a/tcg/loongarch64/tcg-target-has.h b/tcg/loongarch64/tcg-target-has.h
index 9c118bd1f6..32abc6f457 100644
--- a/tcg/loongarch64/tcg-target-has.h
+++ b/tcg/loongarch64/tcg-target-has.h
@@ -9,9 +9,6 @@
  
  #include "host/cpuinfo.h"
  
-/* optional instructions */

-#define TCG_TARGET_HAS_qemu_st8_i32 0
-
  /* 64-bit operations */
  #define TCG_TARGET_HAS_extr_i64_i32 1
  
diff --git a/tcg/mips/tcg-target-has.h b/tcg/mips/tcg-target-has.h

index d8f9f7beef..b9eb338528 100644
--- a/tcg/mips/tcg-target-has.h
+++ b/tcg/mips/tcg-target-has.h
@@ -46,7 +46,6 @@ extern bool use_mips32r2_instructions;
  #endif
  
  /* optional instructions detected at runtime */

-#define TCG_TARGET_HAS_qemu_st8_i32 0
  #define TCG_TARGET_HAS_qemu_ldst_i128   0
  #define TCG_TARGET_HAS_tst  0
  
diff --git a/tcg/ppc/tcg-target-has.h b/tcg/ppc/tcg-target-has.h

index b978c91a62..81ec5aece7 100644
--- a/tcg/ppc/tcg-target-has.h
+++ b/tcg/ppc/tcg-target-has.h
@@ -17,8 +17,6 @@
  #define have_vsx   (cpuinfo & CPUINFO_VSX)
  
  /* optional instructions */

-#define TCG_TARGET_HAS_qemu_st8_i32 0
-
  #if TCG_TARGET_REG_BITS == 64
  #define TCG_TARGET_HAS_extr_i64_i32 0
  #endif
diff --git a/tcg/riscv/tcg-target-has.h b/tcg/riscv/tcg-target-has.h
index 8cd099546f..aef10c2d9d 100644
--- a/tcg/riscv/tcg-target-has.h
+++ b/tcg/riscv/tcg-target-has.h
@@ -10,7 +10,6 @@
  #include "host/cpuinfo.h"
  
  /* optional instructions */

-#define TCG_TARGET_HAS_qemu_st8_i32 0

Re: [PATCH v4 159/163] tcg: Remove INDEX_op_qemu_st8_*

2025-04-16 Thread Richard Henderson 

On 4/15/25 23:55, Philippe Mathieu-Daudé wrote:
@@ -2457,7 +2457,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg datalo, 
TCGReg datahi,

  switch (memop & MO_SIZE) {
  case MO_8:
-    /* This is handled with constraints on INDEX_op_qemu_st8_i32. */
+    /* This is handled with constraints on INDEX_op_qemu_st_*_i32. */


"... handled with constraints on INDEX_op_qemu_st_i32."

Either INDEX_op_qemu_st_i32 or INDEX_op_qemu_st_*.


As of the next patch, just INDEX_op_qemu_st.  :-/


+    return (TCG_TARGET_REG_BITS == 32 && flags == MO_8


)


+    ? C_O0_I2(s, L)
+    : C_O0_I2(L, L));


(misplaced parenthesis)


No, it's not.


r~

Re: [PATCH v4 159/163] tcg: Remove INDEX_op_qemu_st8_*

2025-04-15 Thread Philippe Mathieu-Daudé 

On 15/4/25 21:25, Richard Henderson wrote:

The i386 backend can now check TCGOP_FLAGS to select
the correct set of constraints.

Signed-off-by: Richard Henderson 
---
  include/tcg/tcg-opc.h| 4 
  tcg/aarch64/tcg-target-has.h | 1 -
  tcg/arm/tcg-target-has.h | 1 -
  tcg/i386/tcg-target-con-str.h| 2 +-
  tcg/i386/tcg-target-has.h| 3 ---
  tcg/loongarch64/tcg-target-has.h | 3 ---
  tcg/mips/tcg-target-has.h| 1 -
  tcg/ppc/tcg-target-has.h | 2 --
  tcg/riscv/tcg-target-has.h   | 1 -
  tcg/s390x/tcg-target-has.h   | 1 -
  tcg/sparc64/tcg-target-has.h | 1 -
  tcg/tci/tcg-target-has.h | 2 --
  tcg/optimize.c   | 1 -
  tcg/tcg-op-ldst.c| 9 ++---
  tcg/tcg.c| 4 
  docs/devel/tcg-ops.rst   | 6 --
  tcg/i386/tcg-target.c.inc| 9 -
  17 files changed, 7 insertions(+), 44 deletions(-)




diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index 52285bcd54..40e640ff89 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -2457,7 +2457,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg 
datalo, TCGReg datahi,
  
  switch (memop & MO_SIZE) {

  case MO_8:
-/* This is handled with constraints on INDEX_op_qemu_st8_i32. */
+/* This is handled with constraints on INDEX_op_qemu_st_*_i32. */


"... handled with constraints on INDEX_op_qemu_st_i32."

Either INDEX_op_qemu_st_i32 or INDEX_op_qemu_st_*.


  tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || datalo < 4);
  tcg_out_modrm_sib_offset(s, OPC_MOVB_EvGv + P_REXB_R + h.seg,
   datalo, h.base, h.index, 0, h.ofs);
@@ -3568,7 +3568,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, 
TCGType type,
  break;
  
  case INDEX_op_qemu_st_i32:

-case INDEX_op_qemu_st8_i32:
  tcg_out_qemu_st(s, a0, -1, a1, a2, TCG_TYPE_I32);
  break;
  case INDEX_op_qemu_st_i64:
@@ -4140,9 +4139,9 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned 
flags)
  return C_O1_I1(r, L);
  
  case INDEX_op_qemu_st_i32:

-return C_O0_I2(L, L);
-case INDEX_op_qemu_st8_i32:
-return C_O0_I2(s, L);
+return (TCG_TARGET_REG_BITS == 32 && flags == MO_8


)


+? C_O0_I2(s, L)
+: C_O0_I2(L, L));


(misplaced parenthesis)

Nice!

Reviewed-by: Philippe Mathieu-Daudé

[PATCH v4 159/163] tcg: Remove INDEX_op_qemu_st8_*

2025-04-15 Thread Richard Henderson 
The i386 backend can now check TCGOP_FLAGS to select
the correct set of constraints.

Signed-off-by: Richard Henderson 
---
 include/tcg/tcg-opc.h| 4 
 tcg/aarch64/tcg-target-has.h | 1 -
 tcg/arm/tcg-target-has.h | 1 -
 tcg/i386/tcg-target-con-str.h| 2 +-
 tcg/i386/tcg-target-has.h| 3 ---
 tcg/loongarch64/tcg-target-has.h | 3 ---
 tcg/mips/tcg-target-has.h| 1 -
 tcg/ppc/tcg-target-has.h | 2 --
 tcg/riscv/tcg-target-has.h   | 1 -
 tcg/s390x/tcg-target-has.h   | 1 -
 tcg/sparc64/tcg-target-has.h | 1 -
 tcg/tci/tcg-target-has.h | 2 --
 tcg/optimize.c   | 1 -
 tcg/tcg-op-ldst.c| 9 ++---
 tcg/tcg.c| 4 
 docs/devel/tcg-ops.rst   | 6 --
 tcg/i386/tcg-target.c.inc| 9 -
 17 files changed, 7 insertions(+), 44 deletions(-)

diff --git a/include/tcg/tcg-opc.h b/include/tcg/tcg-opc.h
index a22433d8b5..0ce8332aab 100644
--- a/include/tcg/tcg-opc.h
+++ b/include/tcg/tcg-opc.h
@@ -133,10 +133,6 @@ DEF(qemu_ld_i64, DATA64_ARGS, 1, 1,
 DEF(qemu_st_i64, 0, DATA64_ARGS + 1, 1,
 TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 
-/* Only used by i386 to cope with stupid register constraints. */
-DEF(qemu_st8_i32, 0, 1 + 1, 1,
-TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
-
 /* Only for 64-bit hosts at the moment. */
 DEF(qemu_ld_i128, 2, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 DEF(qemu_st_i128, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
diff --git a/tcg/aarch64/tcg-target-has.h b/tcg/aarch64/tcg-target-has.h
index b155e37639..69e83efb69 100644
--- a/tcg/aarch64/tcg-target-has.h
+++ b/tcg/aarch64/tcg-target-has.h
@@ -14,7 +14,6 @@
 
 /* optional instructions */
 #define TCG_TARGET_HAS_extr_i64_i32 0
-#define TCG_TARGET_HAS_qemu_st8_i32 0
 
 /*
  * Without FEAT_LSE2, we must use LDXP+STXP to implement atomic 128-bit load,
diff --git a/tcg/arm/tcg-target-has.h b/tcg/arm/tcg-target-has.h
index 187269e5bd..3bbbde5d59 100644
--- a/tcg/arm/tcg-target-has.h
+++ b/tcg/arm/tcg-target-has.h
@@ -24,7 +24,6 @@ extern bool use_neon_instructions;
 #endif
 
 /* optional instructions */
-#define TCG_TARGET_HAS_qemu_st8_i32 0
 #define TCG_TARGET_HAS_qemu_ldst_i128   0
 #define TCG_TARGET_HAS_tst  1
 
diff --git a/tcg/i386/tcg-target-con-str.h b/tcg/i386/tcg-target-con-str.h
index 52142ab121..dbedff1f54 100644
--- a/tcg/i386/tcg-target-con-str.h
+++ b/tcg/i386/tcg-target-con-str.h
@@ -20,7 +20,7 @@ REGS('r', ALL_GENERAL_REGS)
 REGS('x', ALL_VECTOR_REGS)
 REGS('q', ALL_BYTEL_REGS) /* regs that can be used as a byte operand */
 REGS('L', ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS)  /* qemu_ld/st */
-REGS('s', ALL_BYTEL_REGS & ~SOFTMMU_RESERVE_REGS)/* qemu_st8_i32 data */
+REGS('s', ALL_BYTEL_REGS & ~SOFTMMU_RESERVE_REGS)/* qemu_st MO_8 data */
 
 /*
  * Define constraint letters for constants:
diff --git a/tcg/i386/tcg-target-has.h b/tcg/i386/tcg-target-has.h
index 628e736de7..42647fabbd 100644
--- a/tcg/i386/tcg-target-has.h
+++ b/tcg/i386/tcg-target-has.h
@@ -29,9 +29,6 @@
 #if TCG_TARGET_REG_BITS == 64
 /* Keep 32-bit values zero-extended in a register.  */
 #define TCG_TARGET_HAS_extr_i64_i32 1
-#define TCG_TARGET_HAS_qemu_st8_i32 0
-#else
-#define TCG_TARGET_HAS_qemu_st8_i32 1
 #endif
 
 #define TCG_TARGET_HAS_qemu_ldst_i128 \
diff --git a/tcg/loongarch64/tcg-target-has.h b/tcg/loongarch64/tcg-target-has.h
index 9c118bd1f6..32abc6f457 100644
--- a/tcg/loongarch64/tcg-target-has.h
+++ b/tcg/loongarch64/tcg-target-has.h
@@ -9,9 +9,6 @@
 
 #include "host/cpuinfo.h"
 
-/* optional instructions */
-#define TCG_TARGET_HAS_qemu_st8_i32 0
-
 /* 64-bit operations */
 #define TCG_TARGET_HAS_extr_i64_i32 1
 
diff --git a/tcg/mips/tcg-target-has.h b/tcg/mips/tcg-target-has.h
index d8f9f7beef..b9eb338528 100644
--- a/tcg/mips/tcg-target-has.h
+++ b/tcg/mips/tcg-target-has.h
@@ -46,7 +46,6 @@ extern bool use_mips32r2_instructions;
 #endif
 
 /* optional instructions detected at runtime */
-#define TCG_TARGET_HAS_qemu_st8_i32 0
 #define TCG_TARGET_HAS_qemu_ldst_i128   0
 #define TCG_TARGET_HAS_tst  0
 
diff --git a/tcg/ppc/tcg-target-has.h b/tcg/ppc/tcg-target-has.h
index b978c91a62..81ec5aece7 100644
--- a/tcg/ppc/tcg-target-has.h
+++ b/tcg/ppc/tcg-target-has.h
@@ -17,8 +17,6 @@
 #define have_vsx   (cpuinfo & CPUINFO_VSX)
 
 /* optional instructions */
-#define TCG_TARGET_HAS_qemu_st8_i32 0
-
 #if TCG_TARGET_REG_BITS == 64
 #define TCG_TARGET_HAS_extr_i64_i32 0
 #endif
diff --git a/tcg/riscv/tcg-target-has.h b/tcg/riscv/tcg-target-has.h
index 8cd099546f..aef10c2d9d 100644
--- a/tcg/riscv/tcg-target-has.h
+++ b/tcg/riscv/tcg-target-has.h
@@ -10,7 +10,6 @@
 #include "host/cpuinfo.h"
 
 /* optional instructions */
-#define TCG_TARGET_HAS_qemu_st8_i32 0
 #define TCG_TARGET_HAS_extr_i64_i32 1
 #define TCG_TARGET_HAS_qemu_ldst_i128   0
 #define TCG_TARGET_HAS_tst  0