On Fri, Feb 23, 2018 at 05:29:56PM +, Michael Matz wrote:
> The normal gdb definition of the XER registers is only 32 bit,
> and that's what the current version of power64-core.xml also
> says (seems copied from gdb's). But qemu's idea of the XER register
> is target_ulong (in CPUPPCState, ppc
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: alpine.lsu.2.21.1802231729040.10...@wotan.suse.de
Subject: [Qemu-devel] [PATCH] ppc: Fix size of ppc64 xer register (fwd)
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BASE=base
n
The normal gdb definition of the XER registers is only 32 bit,
and that's what the current version of power64-core.xml also
says (seems copied from gdb's). But qemu's idea of the XER register
is target_ulong (in CPUPPCState, ppc_gdb_register_len and
ppc_cpu_gdb_read_register)
That mismatch leads
