Re: [Qemu-devel] [PATCH] tests: add test for TPM TIS device
On 02/15/2018 07:35 AM, Marc-André Lureau wrote: +#define DPRINTF_STS \ >+DPRINTF("%s: %d: sts = 0x%08x\n", __func__, __LINE__, sts) >+ >+typedef struct TestState { >+CompatGMutex data_mutex; >+CompatGCond data_cond; >+SocketAddress *addr; >+QIOChannel *tpm_ioc; >+GThread *emu_tpm_thread; >+struct tpm_hdr *tpm_msg; >+} TestState; We could avoid code duplication. What about adding a tests/tpm-emu.c/h ? ok, let me give that a try.
Re: [Qemu-devel] [PATCH] tests: add test for TPM TIS device
Hi On Thu, Feb 15, 2018 at 2:21 AM, Stefan Berger wrote: > Move the TPM TIS related register and flag #defines into > include/hw/acpi/tpm.h for access by the test case. > > Write a test case that covers the TIS functionality. > > Add the tests cases to the MAINTAINERS file. > > Signed-off-by: Stefan Berger > --- > MAINTAINERS| 1 + > hw/tpm/tpm_tis.c | 101 > include/hw/acpi/tpm.h | 105 > tests/Makefile.include | 2 + > tests/tpm-tis-test.c | 661 > + > 5 files changed, 769 insertions(+), 101 deletions(-) > create mode 100644 tests/tpm-tis-test.c > > diff --git a/MAINTAINERS b/MAINTAINERS > index 57358a0..60a9ae9 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -1633,6 +1633,7 @@ F: include/hw/acpi/tpm.h > F: include/sysemu/tpm* > F: qapi/tpm.json > F: backends/tpm.c > +F: tests/tpm-*-test > T: git git://github.com/stefanberger/qemu-tpm.git tpm-next > > Checkpatch > diff --git a/hw/tpm/tpm_tis.c b/hw/tpm/tpm_tis.c > index f81168a..834eef7 100644 > --- a/hw/tpm/tpm_tis.c > +++ b/hw/tpm/tpm_tis.c > @@ -92,107 +92,6 @@ typedef struct TPMState { > } \ > } while (0) > > -/* tis registers */ > -#define TPM_TIS_REG_ACCESS0x00 > -#define TPM_TIS_REG_INT_ENABLE0x08 > -#define TPM_TIS_REG_INT_VECTOR0x0c > -#define TPM_TIS_REG_INT_STATUS0x10 > -#define TPM_TIS_REG_INTF_CAPABILITY 0x14 > -#define TPM_TIS_REG_STS 0x18 > -#define TPM_TIS_REG_DATA_FIFO 0x24 > -#define TPM_TIS_REG_INTERFACE_ID 0x30 > -#define TPM_TIS_REG_DATA_XFIFO0x80 > -#define TPM_TIS_REG_DATA_XFIFO_END0xbc > -#define TPM_TIS_REG_DID_VID 0xf00 > -#define TPM_TIS_REG_RID 0xf04 > - > -/* vendor-specific registers */ > -#define TPM_TIS_REG_DEBUG 0xf90 > - > -#define TPM_TIS_STS_TPM_FAMILY_MASK (0x3 << 26)/* TPM 2.0 */ > -#define TPM_TIS_STS_TPM_FAMILY1_2 (0 << 26) /* TPM 2.0 */ > -#define TPM_TIS_STS_TPM_FAMILY2_0 (1 << 26) /* TPM 2.0 */ > -#define TPM_TIS_STS_RESET_ESTABLISHMENT_BIT (1 << 25) /* TPM 2.0 */ > -#define TPM_TIS_STS_COMMAND_CANCEL (1 << 24) /* TPM 2.0 */ > - > -#define TPM_TIS_STS_VALID (1 << 7) > -#define TPM_TIS_STS_COMMAND_READY (1 << 6) > -#define TPM_TIS_STS_TPM_GO(1 << 5) > -#define TPM_TIS_STS_DATA_AVAILABLE(1 << 4) > -#define TPM_TIS_STS_EXPECT(1 << 3) > -#define TPM_TIS_STS_SELFTEST_DONE (1 << 2) > -#define TPM_TIS_STS_RESPONSE_RETRY(1 << 1) > - > -#define TPM_TIS_BURST_COUNT_SHIFT 8 > -#define TPM_TIS_BURST_COUNT(X) \ > -((X) << TPM_TIS_BURST_COUNT_SHIFT) > - > -#define TPM_TIS_ACCESS_TPM_REG_VALID_STS (1 << 7) > -#define TPM_TIS_ACCESS_ACTIVE_LOCALITY(1 << 5) > -#define TPM_TIS_ACCESS_BEEN_SEIZED(1 << 4) > -#define TPM_TIS_ACCESS_SEIZE (1 << 3) > -#define TPM_TIS_ACCESS_PENDING_REQUEST(1 << 2) > -#define TPM_TIS_ACCESS_REQUEST_USE(1 << 1) > -#define TPM_TIS_ACCESS_TPM_ESTABLISHMENT (1 << 0) > - > -#define TPM_TIS_INT_ENABLED (1 << 31) > -#define TPM_TIS_INT_DATA_AVAILABLE(1 << 0) > -#define TPM_TIS_INT_STS_VALID (1 << 1) > -#define TPM_TIS_INT_LOCALITY_CHANGED (1 << 2) > -#define TPM_TIS_INT_COMMAND_READY (1 << 7) > - > -#define TPM_TIS_INT_POLARITY_MASK (3 << 3) > -#define TPM_TIS_INT_POLARITY_LOW_LEVEL(1 << 3) > - > -#define TPM_TIS_INTERRUPTS_SUPPORTED (TPM_TIS_INT_LOCALITY_CHANGED | \ > - TPM_TIS_INT_DATA_AVAILABLE | \ > - TPM_TIS_INT_STS_VALID | \ > - TPM_TIS_INT_COMMAND_READY) > - > -#define TPM_TIS_CAP_INTERFACE_VERSION1_3 (2 << 28) > -#define TPM_TIS_CAP_INTERFACE_VERSION1_3_FOR_TPM2_0 (3 << 28) > -#define TPM_TIS_CAP_DATA_TRANSFER_64B(3 << 9) > -#define TPM_TIS_CAP_DATA_TRANSFER_LEGACY (0 << 9) > -#define TPM_TIS_CAP_BURST_COUNT_DYNAMIC (0 << 8) > -#define TPM_TIS_CAP_INTERRUPT_LOW_LEVEL (1 << 4) /* support is mandatory */ > -#define TPM_TIS_CAPABILITIES_SUPPORTED1_3 \ > -(TPM_TIS_CAP_INTERRUPT_LOW_LEVEL | \ > - TPM_TIS_CAP_BURST_COUNT_DYNAMIC | \ > - TPM_TIS_CAP_DATA_TRANSFER_64B | \ > - TPM_TIS_CAP_INTERFACE_VERSION1_3 | \ > - TPM_TIS_INTERRUPTS_SUPPORTED) > - > -#define TPM_TIS_CAPABILITIES_SUPPORTED2_0 \ > -(TPM_TIS_CAP_INTERRUPT_LOW_LEVEL | \ > - TPM_TIS_CAP_BURST_COUNT_DYNAMIC | \ > - TPM_TIS_CAP_DATA_TRANSFER_64B | \ > - TPM_TIS_CAP_INTERFACE_VERSION1_3_FOR_TPM2_0 | \ > - TPM_TIS_INTERRUPTS_SUPPORTED) > - > -#define TPM_TIS_IFACE_ID_INTERFACE_TIS1_3 (0xf) /* TPM 2.0 */ > -#define TPM_TIS_IFACE_ID_INTERFACE_FIFO (0x0) /* TPM 2.0 */ > -#define TPM_TIS_IFACE_ID_INTERFACE_VER_FIFO (0 << 4) /* TPM 2.0 */ > -#define TPM_TIS_IFACE_ID_CAP_5_LOCALITIES
[Qemu-devel] [PATCH] tests: add test for TPM TIS device
Move the TPM TIS related register and flag #defines into include/hw/acpi/tpm.h for access by the test case. Write a test case that covers the TIS functionality. Add the tests cases to the MAINTAINERS file. Signed-off-by: Stefan Berger --- MAINTAINERS| 1 + hw/tpm/tpm_tis.c | 101 include/hw/acpi/tpm.h | 105 tests/Makefile.include | 2 + tests/tpm-tis-test.c | 661 + 5 files changed, 769 insertions(+), 101 deletions(-) create mode 100644 tests/tpm-tis-test.c diff --git a/MAINTAINERS b/MAINTAINERS index 57358a0..60a9ae9 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1633,6 +1633,7 @@ F: include/hw/acpi/tpm.h F: include/sysemu/tpm* F: qapi/tpm.json F: backends/tpm.c +F: tests/tpm-*-test T: git git://github.com/stefanberger/qemu-tpm.git tpm-next Checkpatch diff --git a/hw/tpm/tpm_tis.c b/hw/tpm/tpm_tis.c index f81168a..834eef7 100644 --- a/hw/tpm/tpm_tis.c +++ b/hw/tpm/tpm_tis.c @@ -92,107 +92,6 @@ typedef struct TPMState { } \ } while (0) -/* tis registers */ -#define TPM_TIS_REG_ACCESS0x00 -#define TPM_TIS_REG_INT_ENABLE0x08 -#define TPM_TIS_REG_INT_VECTOR0x0c -#define TPM_TIS_REG_INT_STATUS0x10 -#define TPM_TIS_REG_INTF_CAPABILITY 0x14 -#define TPM_TIS_REG_STS 0x18 -#define TPM_TIS_REG_DATA_FIFO 0x24 -#define TPM_TIS_REG_INTERFACE_ID 0x30 -#define TPM_TIS_REG_DATA_XFIFO0x80 -#define TPM_TIS_REG_DATA_XFIFO_END0xbc -#define TPM_TIS_REG_DID_VID 0xf00 -#define TPM_TIS_REG_RID 0xf04 - -/* vendor-specific registers */ -#define TPM_TIS_REG_DEBUG 0xf90 - -#define TPM_TIS_STS_TPM_FAMILY_MASK (0x3 << 26)/* TPM 2.0 */ -#define TPM_TIS_STS_TPM_FAMILY1_2 (0 << 26) /* TPM 2.0 */ -#define TPM_TIS_STS_TPM_FAMILY2_0 (1 << 26) /* TPM 2.0 */ -#define TPM_TIS_STS_RESET_ESTABLISHMENT_BIT (1 << 25) /* TPM 2.0 */ -#define TPM_TIS_STS_COMMAND_CANCEL (1 << 24) /* TPM 2.0 */ - -#define TPM_TIS_STS_VALID (1 << 7) -#define TPM_TIS_STS_COMMAND_READY (1 << 6) -#define TPM_TIS_STS_TPM_GO(1 << 5) -#define TPM_TIS_STS_DATA_AVAILABLE(1 << 4) -#define TPM_TIS_STS_EXPECT(1 << 3) -#define TPM_TIS_STS_SELFTEST_DONE (1 << 2) -#define TPM_TIS_STS_RESPONSE_RETRY(1 << 1) - -#define TPM_TIS_BURST_COUNT_SHIFT 8 -#define TPM_TIS_BURST_COUNT(X) \ -((X) << TPM_TIS_BURST_COUNT_SHIFT) - -#define TPM_TIS_ACCESS_TPM_REG_VALID_STS (1 << 7) -#define TPM_TIS_ACCESS_ACTIVE_LOCALITY(1 << 5) -#define TPM_TIS_ACCESS_BEEN_SEIZED(1 << 4) -#define TPM_TIS_ACCESS_SEIZE (1 << 3) -#define TPM_TIS_ACCESS_PENDING_REQUEST(1 << 2) -#define TPM_TIS_ACCESS_REQUEST_USE(1 << 1) -#define TPM_TIS_ACCESS_TPM_ESTABLISHMENT (1 << 0) - -#define TPM_TIS_INT_ENABLED (1 << 31) -#define TPM_TIS_INT_DATA_AVAILABLE(1 << 0) -#define TPM_TIS_INT_STS_VALID (1 << 1) -#define TPM_TIS_INT_LOCALITY_CHANGED (1 << 2) -#define TPM_TIS_INT_COMMAND_READY (1 << 7) - -#define TPM_TIS_INT_POLARITY_MASK (3 << 3) -#define TPM_TIS_INT_POLARITY_LOW_LEVEL(1 << 3) - -#define TPM_TIS_INTERRUPTS_SUPPORTED (TPM_TIS_INT_LOCALITY_CHANGED | \ - TPM_TIS_INT_DATA_AVAILABLE | \ - TPM_TIS_INT_STS_VALID | \ - TPM_TIS_INT_COMMAND_READY) - -#define TPM_TIS_CAP_INTERFACE_VERSION1_3 (2 << 28) -#define TPM_TIS_CAP_INTERFACE_VERSION1_3_FOR_TPM2_0 (3 << 28) -#define TPM_TIS_CAP_DATA_TRANSFER_64B(3 << 9) -#define TPM_TIS_CAP_DATA_TRANSFER_LEGACY (0 << 9) -#define TPM_TIS_CAP_BURST_COUNT_DYNAMIC (0 << 8) -#define TPM_TIS_CAP_INTERRUPT_LOW_LEVEL (1 << 4) /* support is mandatory */ -#define TPM_TIS_CAPABILITIES_SUPPORTED1_3 \ -(TPM_TIS_CAP_INTERRUPT_LOW_LEVEL | \ - TPM_TIS_CAP_BURST_COUNT_DYNAMIC | \ - TPM_TIS_CAP_DATA_TRANSFER_64B | \ - TPM_TIS_CAP_INTERFACE_VERSION1_3 | \ - TPM_TIS_INTERRUPTS_SUPPORTED) - -#define TPM_TIS_CAPABILITIES_SUPPORTED2_0 \ -(TPM_TIS_CAP_INTERRUPT_LOW_LEVEL | \ - TPM_TIS_CAP_BURST_COUNT_DYNAMIC | \ - TPM_TIS_CAP_DATA_TRANSFER_64B | \ - TPM_TIS_CAP_INTERFACE_VERSION1_3_FOR_TPM2_0 | \ - TPM_TIS_INTERRUPTS_SUPPORTED) - -#define TPM_TIS_IFACE_ID_INTERFACE_TIS1_3 (0xf) /* TPM 2.0 */ -#define TPM_TIS_IFACE_ID_INTERFACE_FIFO (0x0) /* TPM 2.0 */ -#define TPM_TIS_IFACE_ID_INTERFACE_VER_FIFO (0 << 4) /* TPM 2.0 */ -#define TPM_TIS_IFACE_ID_CAP_5_LOCALITIES (1 << 8) /* TPM 2.0 */ -#define TPM_TIS_IFACE_ID_CAP_TIS_SUPPORTED (1 << 13) /* TPM 2.0 */ -#define TPM_TIS_IFACE_ID_INT_SEL_LOCK (1 << 19) /* TPM 2.0 */ - -#define TPM_TIS_IFACE_ID_SUPPORTED_FLAGS1_3 \ -(TPM_TIS_IFACE_ID_INTERFACE_TIS1_3 | \ - (~0u << 4)/* all of it is don