Re: [Qemu-devel] [PATCH 08/11] openpic: move OpenPIC state and related definitions to openpic.h
On Mon, Feb 19, 2018 at 06:19:19PM +, Mark Cave-Ayland wrote: > This is to faciliate access to OpenPICState when wiring up the PIC to the > macio > controller. > > Signed-off-by: Mark Cave-Ayland Reviewed-by: David Gibson > --- > hw/intc/openpic.c| 157 -- > include/hw/ppc/openpic.h | 160 > ++- > 2 files changed, 159 insertions(+), 158 deletions(-) > > diff --git a/hw/intc/openpic.c b/hw/intc/openpic.c > index 9159a06f07..811cee9b26 100644 > --- a/hw/intc/openpic.c > +++ b/hw/intc/openpic.c > @@ -63,10 +63,6 @@ static int get_current_cpu(void); > } \ > } while (0) > > -#define MAX_CPU 32 > -#define MAX_MSI 8 > -#define VID 0x03 /* MPIC version ID */ > - > /* OpenPIC capability flags */ > #define OPENPIC_FLAG_IDR_CRIT (1 << 0) > #define OPENPIC_FLAG_ILR (2 << 0) > @@ -85,35 +81,6 @@ static int get_current_cpu(void); > #define OPENPIC_CPU_REG_START0x2 > #define OPENPIC_CPU_REG_SIZE 0x100 + ((MAX_CPU - 1) * 0x1000) > > -/* Raven */ > -#define RAVEN_MAX_CPU 2 > -#define RAVEN_MAX_EXT 48 > -#define RAVEN_MAX_IRQ 64 > -#define RAVEN_MAX_TMR OPENPIC_MAX_TMR > -#define RAVEN_MAX_IPI OPENPIC_MAX_IPI > - > -/* KeyLargo */ > -#define KEYLARGO_MAX_CPU 4 > -#define KEYLARGO_MAX_EXT 64 > -#define KEYLARGO_MAX_IPI 4 > -#define KEYLARGO_MAX_IRQ (64 + KEYLARGO_MAX_IPI) > -#define KEYLARGO_MAX_TMR 0 > -#define KEYLARGO_IPI_IRQ (KEYLARGO_MAX_EXT) /* First IPI IRQ */ > -/* Timers don't exist but this makes the code happy... */ > -#define KEYLARGO_TMR_IRQ (KEYLARGO_IPI_IRQ + KEYLARGO_MAX_IPI) > - > -/* Interrupt definitions */ > -#define RAVEN_FE_IRQ (RAVEN_MAX_EXT) /* Internal functional IRQ */ > -#define RAVEN_ERR_IRQ(RAVEN_MAX_EXT + 1) /* Error IRQ */ > -#define RAVEN_TMR_IRQ(RAVEN_MAX_EXT + 2) /* First timer IRQ */ > -#define RAVEN_IPI_IRQ(RAVEN_TMR_IRQ + RAVEN_MAX_TMR) /* First IPI IRQ */ > -/* First doorbell IRQ */ > -#define RAVEN_DBL_IRQ(RAVEN_IPI_IRQ + (RAVEN_MAX_CPU * RAVEN_MAX_IPI)) > - > -typedef struct FslMpicInfo { > -int max_ext; > -} FslMpicInfo; > - > static FslMpicInfo fsl_mpic_20 = { > .max_ext = 12, > }; > @@ -211,55 +178,6 @@ static void openpic_cpu_write_internal(void *opaque, > hwaddr addr, > uint32_t val, int idx); > static void openpic_reset(DeviceState *d); > > -typedef enum IRQType { > -IRQ_TYPE_NORMAL = 0, > -IRQ_TYPE_FSLINT,/* FSL internal interrupt -- level only */ > -IRQ_TYPE_FSLSPECIAL,/* FSL timer/IPI interrupt, edge, no polarity */ > -} IRQType; > - > -/* Round up to the nearest 64 IRQs so that the queue length > - * won't change when moving between 32 and 64 bit hosts. > - */ > -#define IRQQUEUE_SIZE_BITS ((OPENPIC_MAX_IRQ + 63) & ~63) > - > -typedef struct IRQQueue { > -unsigned long *queue; > -int32_t queue_size; /* Only used for VMSTATE_BITMAP */ > -int next; > -int priority; > -} IRQQueue; > - > -typedef struct IRQSource { > -uint32_t ivpr; /* IRQ vector/priority register */ > -uint32_t idr; /* IRQ destination register */ > -uint32_t destmask; /* bitmap of CPU destinations */ > -int last_cpu; > -int output; /* IRQ level, e.g. OPENPIC_OUTPUT_INT */ > -int pending;/* TRUE if IRQ is pending */ > -IRQType type; > -bool level:1; /* level-triggered */ > -bool nomask:1; /* critical interrupts ignore mask on some FSL MPICs */ > -} IRQSource; > - > -#define IVPR_MASK_SHIFT 31 > -#define IVPR_MASK_MASK(1U << IVPR_MASK_SHIFT) > -#define IVPR_ACTIVITY_SHIFT 30 > -#define IVPR_ACTIVITY_MASK(1U << IVPR_ACTIVITY_SHIFT) > -#define IVPR_MODE_SHIFT 29 > -#define IVPR_MODE_MASK(1U << IVPR_MODE_SHIFT) > -#define IVPR_POLARITY_SHIFT 23 > -#define IVPR_POLARITY_MASK(1U << IVPR_POLARITY_SHIFT) > -#define IVPR_SENSE_SHIFT 22 > -#define IVPR_SENSE_MASK (1U << IVPR_SENSE_SHIFT) > - > -#define IVPR_PRIORITY_MASK (0xFU << 16) > -#define IVPR_PRIORITY(_ivprr_) ((int)(((_ivprr_) & IVPR_PRIORITY_MASK) >> > 16)) > -#define IVPR_VECTOR(opp, _ivprr_) ((_ivprr_) & (opp)->vector_mask) > - > -/* IDR[EP/CI] are only for FSL MPIC prior to v4.0 */ > -#define IDR_EP 0x8000 /* external pin */ > -#define IDR_CI 0x4000 /* critical interrupt */ > - > /* Convert between openpic clock ticks and nanosecs. In the hardware the > clock > frequency is driven by board inputs to the PIC which the PIC would then > divide by 4 or 8. For now hard code to 25MZ. > @@ -275,81 +193,6 @@ static inline uint64_t ticks_to_ns(uint64_t ticks) > return ticks * OPENPIC_TIMER_NS_PER_TICK; > } > > -typedef struct OpenPICTimer { > -uint32_t tccr; /* Global timer current count register */ > -uint32_t tbcr; /* Global timer base count register */ > -int n_IRQ; >
[Qemu-devel] [PATCH 08/11] openpic: move OpenPIC state and related definitions to openpic.h
This is to faciliate access to OpenPICState when wiring up the PIC to the macio controller. Signed-off-by: Mark Cave-Ayland --- hw/intc/openpic.c| 157 -- include/hw/ppc/openpic.h | 160 ++- 2 files changed, 159 insertions(+), 158 deletions(-) diff --git a/hw/intc/openpic.c b/hw/intc/openpic.c index 9159a06f07..811cee9b26 100644 --- a/hw/intc/openpic.c +++ b/hw/intc/openpic.c @@ -63,10 +63,6 @@ static int get_current_cpu(void); } \ } while (0) -#define MAX_CPU 32 -#define MAX_MSI 8 -#define VID 0x03 /* MPIC version ID */ - /* OpenPIC capability flags */ #define OPENPIC_FLAG_IDR_CRIT (1 << 0) #define OPENPIC_FLAG_ILR (2 << 0) @@ -85,35 +81,6 @@ static int get_current_cpu(void); #define OPENPIC_CPU_REG_START0x2 #define OPENPIC_CPU_REG_SIZE 0x100 + ((MAX_CPU - 1) * 0x1000) -/* Raven */ -#define RAVEN_MAX_CPU 2 -#define RAVEN_MAX_EXT 48 -#define RAVEN_MAX_IRQ 64 -#define RAVEN_MAX_TMR OPENPIC_MAX_TMR -#define RAVEN_MAX_IPI OPENPIC_MAX_IPI - -/* KeyLargo */ -#define KEYLARGO_MAX_CPU 4 -#define KEYLARGO_MAX_EXT 64 -#define KEYLARGO_MAX_IPI 4 -#define KEYLARGO_MAX_IRQ (64 + KEYLARGO_MAX_IPI) -#define KEYLARGO_MAX_TMR 0 -#define KEYLARGO_IPI_IRQ (KEYLARGO_MAX_EXT) /* First IPI IRQ */ -/* Timers don't exist but this makes the code happy... */ -#define KEYLARGO_TMR_IRQ (KEYLARGO_IPI_IRQ + KEYLARGO_MAX_IPI) - -/* Interrupt definitions */ -#define RAVEN_FE_IRQ (RAVEN_MAX_EXT) /* Internal functional IRQ */ -#define RAVEN_ERR_IRQ(RAVEN_MAX_EXT + 1) /* Error IRQ */ -#define RAVEN_TMR_IRQ(RAVEN_MAX_EXT + 2) /* First timer IRQ */ -#define RAVEN_IPI_IRQ(RAVEN_TMR_IRQ + RAVEN_MAX_TMR) /* First IPI IRQ */ -/* First doorbell IRQ */ -#define RAVEN_DBL_IRQ(RAVEN_IPI_IRQ + (RAVEN_MAX_CPU * RAVEN_MAX_IPI)) - -typedef struct FslMpicInfo { -int max_ext; -} FslMpicInfo; - static FslMpicInfo fsl_mpic_20 = { .max_ext = 12, }; @@ -211,55 +178,6 @@ static void openpic_cpu_write_internal(void *opaque, hwaddr addr, uint32_t val, int idx); static void openpic_reset(DeviceState *d); -typedef enum IRQType { -IRQ_TYPE_NORMAL = 0, -IRQ_TYPE_FSLINT,/* FSL internal interrupt -- level only */ -IRQ_TYPE_FSLSPECIAL,/* FSL timer/IPI interrupt, edge, no polarity */ -} IRQType; - -/* Round up to the nearest 64 IRQs so that the queue length - * won't change when moving between 32 and 64 bit hosts. - */ -#define IRQQUEUE_SIZE_BITS ((OPENPIC_MAX_IRQ + 63) & ~63) - -typedef struct IRQQueue { -unsigned long *queue; -int32_t queue_size; /* Only used for VMSTATE_BITMAP */ -int next; -int priority; -} IRQQueue; - -typedef struct IRQSource { -uint32_t ivpr; /* IRQ vector/priority register */ -uint32_t idr; /* IRQ destination register */ -uint32_t destmask; /* bitmap of CPU destinations */ -int last_cpu; -int output; /* IRQ level, e.g. OPENPIC_OUTPUT_INT */ -int pending;/* TRUE if IRQ is pending */ -IRQType type; -bool level:1; /* level-triggered */ -bool nomask:1; /* critical interrupts ignore mask on some FSL MPICs */ -} IRQSource; - -#define IVPR_MASK_SHIFT 31 -#define IVPR_MASK_MASK(1U << IVPR_MASK_SHIFT) -#define IVPR_ACTIVITY_SHIFT 30 -#define IVPR_ACTIVITY_MASK(1U << IVPR_ACTIVITY_SHIFT) -#define IVPR_MODE_SHIFT 29 -#define IVPR_MODE_MASK(1U << IVPR_MODE_SHIFT) -#define IVPR_POLARITY_SHIFT 23 -#define IVPR_POLARITY_MASK(1U << IVPR_POLARITY_SHIFT) -#define IVPR_SENSE_SHIFT 22 -#define IVPR_SENSE_MASK (1U << IVPR_SENSE_SHIFT) - -#define IVPR_PRIORITY_MASK (0xFU << 16) -#define IVPR_PRIORITY(_ivprr_) ((int)(((_ivprr_) & IVPR_PRIORITY_MASK) >> 16)) -#define IVPR_VECTOR(opp, _ivprr_) ((_ivprr_) & (opp)->vector_mask) - -/* IDR[EP/CI] are only for FSL MPIC prior to v4.0 */ -#define IDR_EP 0x8000 /* external pin */ -#define IDR_CI 0x4000 /* critical interrupt */ - /* Convert between openpic clock ticks and nanosecs. In the hardware the clock frequency is driven by board inputs to the PIC which the PIC would then divide by 4 or 8. For now hard code to 25MZ. @@ -275,81 +193,6 @@ static inline uint64_t ticks_to_ns(uint64_t ticks) return ticks * OPENPIC_TIMER_NS_PER_TICK; } -typedef struct OpenPICTimer { -uint32_t tccr; /* Global timer current count register */ -uint32_t tbcr; /* Global timer base count register */ -int n_IRQ; -bool qemu_timer_active; /* Is the qemu_timer is running? */ -struct QEMUTimer *qemu_timer; -struct OpenPICState *opp; /* Device timer is part of. */ -/* The QEMU_CLOCK_VIRTUAL time (in ns) corresponding to the last - current_count written or read, only defined if qemu_timer_active. */ -uint64_t