Re: [Qemu-devel] [PATCH 1/7] tcg: Define "deposit" as an optional operation.
On Mon, Jan 10, 2011 at 07:23:42PM -0800, Richard Henderson wrote:
> Signed-off-by: Richard Henderson
> ---
> tcg/README| 14
> tcg/tcg-op.h | 64
> +
> tcg/tcg-opc.h |6 +
> 3 files changed, 84 insertions(+), 0 deletions(-)
>
> diff --git a/tcg/README b/tcg/README
> index a18a87f..a50ecc6 100644
> --- a/tcg/README
> +++ b/tcg/README
> @@ -285,6 +285,20 @@ the four high order bytes are set to zero.
> Indicate that the value of t0 won't be used later. It is useful to
> force dead code elimination.
>
> +* deposit_i32/i64 dest, t1, t2, pos, loc
^^^
Should maybe be len.
> +
> +Deposit T2 as a bitfield into T1, placing the result in DEST.
> +The bitfield is described by POS/LOC, which are immediate values:
^^^
LEN
The rest looks good, thanks.
Acked-by: Edgar E. Iglesias
> +
> + LEN - the length of the bitfield
> + POS - the position of the first bit, counting from the LSB
> +
> +For example, pos=8, len=4 indicates a 4-bit field at bit 8.
> +This operation would be equivalent to
> +
> + dest = (t1 & ~0x0f00) | ((t2 << 8) & 0x0f00)
> +
> +
> * Conditional moves
>
> * setcond_i32/i64 cond, dest, t1, t2
> diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
> index 3ee0a58..207a89f 100644
> --- a/tcg/tcg-op.h
> +++ b/tcg/tcg-op.h
> @@ -254,6 +254,30 @@ static inline void tcg_gen_op5i_i64(TCGOpcode opc,
> TCGv_i64 arg1, TCGv_i64 arg2,
> *gen_opparam_ptr++ = arg5;
> }
>
> +static inline void tcg_gen_op5ii_i32(TCGOpcode opc, TCGv_i32 arg1,
> + TCGv_i32 arg2, TCGv_i32 arg3,
> + TCGArg arg4, TCGArg arg5)
> +{
> +*gen_opc_ptr++ = opc;
> +*gen_opparam_ptr++ = GET_TCGV_I32(arg1);
> +*gen_opparam_ptr++ = GET_TCGV_I32(arg2);
> +*gen_opparam_ptr++ = GET_TCGV_I32(arg3);
> +*gen_opparam_ptr++ = arg4;
> +*gen_opparam_ptr++ = arg5;
> +}
> +
> +static inline void tcg_gen_op5ii_i64(TCGOpcode opc, TCGv_i64 arg1,
> + TCGv_i64 arg2, TCGv_i64 arg3,
> + TCGArg arg4, TCGArg arg5)
> +{
> +*gen_opc_ptr++ = opc;
> +*gen_opparam_ptr++ = GET_TCGV_I64(arg1);
> +*gen_opparam_ptr++ = GET_TCGV_I64(arg2);
> +*gen_opparam_ptr++ = GET_TCGV_I64(arg3);
> +*gen_opparam_ptr++ = arg4;
> +*gen_opparam_ptr++ = arg5;
> +}
> +
> static inline void tcg_gen_op6_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32
> arg2,
> TCGv_i32 arg3, TCGv_i32 arg4, TCGv_i32
> arg5,
> TCGv_i32 arg6)
> @@ -2071,6 +2095,44 @@ static inline void tcg_gen_rotri_i64(TCGv_i64 ret,
> TCGv_i64 arg1, int64_t arg2)
> }
> }
>
> +static inline void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1,
> +TCGv_i32 arg2, unsigned int ofs,
> +unsigned int len)
> +{
> +#ifdef TCG_TARGET_HAS_deposit_i32
> + tcg_gen_op5ii_i32(INDEX_op_deposit_i32, ret, arg1, arg2, ofs, len);
> +#else
> + uint32_t mask = (1u << len) - 1;
> + TCGv_i32 t1 = tcg_temp_new_i32 ();
> +
> + tcg_gen_andi_i32(t1, arg2, mask);
> + tcg_gen_shli_i32(t1, t1, ofs);
> + tcg_gen_andi_i32(ret, arg1, ~(mask << ofs));
> + tcg_gen_or_i32(ret, ret, t1);
> +
> + tcg_temp_free_i32(t1);
> +#endif
> +}
> +
> +static inline void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1,
> +TCGv_i64 arg2, unsigned int ofs,
> +unsigned int len)
> +{
> +#ifdef TCG_TARGET_HAS_deposit_i64
> + tcg_gen_op5ii_i64(INDEX_op_deposit_i64, ret, arg1, arg2, ofs, len);
> +#else
> + uint64_t mask = (1ull << len) - 1;
> + TCGv_i64 t1 = tcg_temp_new_i64 ();
> +
> + tcg_gen_andi_i64(t1, arg2, mask);
> + tcg_gen_shli_i64(t1, t1, ofs);
> + tcg_gen_andi_i64(ret, arg1, ~(mask << ofs));
> + tcg_gen_or_i64(ret, ret, t1);
> +
> + tcg_temp_free_i64(t1);
> +#endif
> +}
> +
> /***/
> /* QEMU specific operations. Their type depend on the QEMU CPU
> type. */
> @@ -2384,6 +2446,7 @@ static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv
> addr, int mem_index)
> #define tcg_gen_rotli_tl tcg_gen_rotli_i64
> #define tcg_gen_rotr_tl tcg_gen_rotr_i64
> #define tcg_gen_rotri_tl tcg_gen_rotri_i64
> +#define tcg_gen_deposit_tl tcg_gen_deposit_i64
> #define tcg_const_tl tcg_const_i64
> #define tcg_const_local_tl tcg_const_local_i64
> #else
> @@ -2454,6 +2517,7 @@ static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv
> addr, int mem_index)
> #define tcg_gen_rotli_tl tcg_gen_rotli_i32
> #define tcg_gen_rotr_tl tcg_gen_rotr_i32
> #define tcg_gen_rotri_tl tcg_gen_rotri_i32
> +#define tcg_gen_deposit_tl tcg_gen_deposit_i32
> #define tcg_const_tl tcg_const_i32
>
Re: [Qemu-devel] [PATCH 1/7] tcg: Define "deposit" as an optional operation.
On Mon, Jan 10, 2011 at 07:23:42PM -0800, Richard Henderson wrote:
> Signed-off-by: Richard Henderson
> ---
> tcg/README| 14
> tcg/tcg-op.h | 64
> +
> tcg/tcg-opc.h |6 +
> 3 files changed, 84 insertions(+), 0 deletions(-)
Acked-by: Aurelien Jarno
> diff --git a/tcg/README b/tcg/README
> index a18a87f..a50ecc6 100644
> --- a/tcg/README
> +++ b/tcg/README
> @@ -285,6 +285,20 @@ the four high order bytes are set to zero.
> Indicate that the value of t0 won't be used later. It is useful to
> force dead code elimination.
>
> +* deposit_i32/i64 dest, t1, t2, pos, loc
> +
> +Deposit T2 as a bitfield into T1, placing the result in DEST.
> +The bitfield is described by POS/LOC, which are immediate values:
> +
> + LEN - the length of the bitfield
> + POS - the position of the first bit, counting from the LSB
> +
> +For example, pos=8, len=4 indicates a 4-bit field at bit 8.
> +This operation would be equivalent to
> +
> + dest = (t1 & ~0x0f00) | ((t2 << 8) & 0x0f00)
> +
> +
> * Conditional moves
>
> * setcond_i32/i64 cond, dest, t1, t2
> diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
> index 3ee0a58..207a89f 100644
> --- a/tcg/tcg-op.h
> +++ b/tcg/tcg-op.h
> @@ -254,6 +254,30 @@ static inline void tcg_gen_op5i_i64(TCGOpcode opc,
> TCGv_i64 arg1, TCGv_i64 arg2,
> *gen_opparam_ptr++ = arg5;
> }
>
> +static inline void tcg_gen_op5ii_i32(TCGOpcode opc, TCGv_i32 arg1,
> + TCGv_i32 arg2, TCGv_i32 arg3,
> + TCGArg arg4, TCGArg arg5)
> +{
> +*gen_opc_ptr++ = opc;
> +*gen_opparam_ptr++ = GET_TCGV_I32(arg1);
> +*gen_opparam_ptr++ = GET_TCGV_I32(arg2);
> +*gen_opparam_ptr++ = GET_TCGV_I32(arg3);
> +*gen_opparam_ptr++ = arg4;
> +*gen_opparam_ptr++ = arg5;
> +}
> +
> +static inline void tcg_gen_op5ii_i64(TCGOpcode opc, TCGv_i64 arg1,
> + TCGv_i64 arg2, TCGv_i64 arg3,
> + TCGArg arg4, TCGArg arg5)
> +{
> +*gen_opc_ptr++ = opc;
> +*gen_opparam_ptr++ = GET_TCGV_I64(arg1);
> +*gen_opparam_ptr++ = GET_TCGV_I64(arg2);
> +*gen_opparam_ptr++ = GET_TCGV_I64(arg3);
> +*gen_opparam_ptr++ = arg4;
> +*gen_opparam_ptr++ = arg5;
> +}
> +
> static inline void tcg_gen_op6_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32
> arg2,
> TCGv_i32 arg3, TCGv_i32 arg4, TCGv_i32
> arg5,
> TCGv_i32 arg6)
> @@ -2071,6 +2095,44 @@ static inline void tcg_gen_rotri_i64(TCGv_i64 ret,
> TCGv_i64 arg1, int64_t arg2)
> }
> }
>
> +static inline void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1,
> +TCGv_i32 arg2, unsigned int ofs,
> +unsigned int len)
> +{
> +#ifdef TCG_TARGET_HAS_deposit_i32
> + tcg_gen_op5ii_i32(INDEX_op_deposit_i32, ret, arg1, arg2, ofs, len);
> +#else
> + uint32_t mask = (1u << len) - 1;
> + TCGv_i32 t1 = tcg_temp_new_i32 ();
> +
> + tcg_gen_andi_i32(t1, arg2, mask);
> + tcg_gen_shli_i32(t1, t1, ofs);
> + tcg_gen_andi_i32(ret, arg1, ~(mask << ofs));
> + tcg_gen_or_i32(ret, ret, t1);
> +
> + tcg_temp_free_i32(t1);
> +#endif
> +}
> +
> +static inline void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1,
> +TCGv_i64 arg2, unsigned int ofs,
> +unsigned int len)
> +{
> +#ifdef TCG_TARGET_HAS_deposit_i64
> + tcg_gen_op5ii_i64(INDEX_op_deposit_i64, ret, arg1, arg2, ofs, len);
> +#else
> + uint64_t mask = (1ull << len) - 1;
> + TCGv_i64 t1 = tcg_temp_new_i64 ();
> +
> + tcg_gen_andi_i64(t1, arg2, mask);
> + tcg_gen_shli_i64(t1, t1, ofs);
> + tcg_gen_andi_i64(ret, arg1, ~(mask << ofs));
> + tcg_gen_or_i64(ret, ret, t1);
> +
> + tcg_temp_free_i64(t1);
> +#endif
> +}
> +
> /***/
> /* QEMU specific operations. Their type depend on the QEMU CPU
> type. */
> @@ -2384,6 +2446,7 @@ static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv
> addr, int mem_index)
> #define tcg_gen_rotli_tl tcg_gen_rotli_i64
> #define tcg_gen_rotr_tl tcg_gen_rotr_i64
> #define tcg_gen_rotri_tl tcg_gen_rotri_i64
> +#define tcg_gen_deposit_tl tcg_gen_deposit_i64
> #define tcg_const_tl tcg_const_i64
> #define tcg_const_local_tl tcg_const_local_i64
> #else
> @@ -2454,6 +2517,7 @@ static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv
> addr, int mem_index)
> #define tcg_gen_rotli_tl tcg_gen_rotli_i32
> #define tcg_gen_rotr_tl tcg_gen_rotr_i32
> #define tcg_gen_rotri_tl tcg_gen_rotri_i32
> +#define tcg_gen_deposit_tl tcg_gen_deposit_i32
> #define tcg_const_tl tcg_const_i32
> #define tcg_const_local_tl tcg_const_local_i32
> #endif
> diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h
> index 2a98fed..2c7ca1a 100644
> --- a/tcg/tcg-opc.h
> +++ b/tcg/tcg-opc.h
> @@ -78,6 +78,9 @@ DEF(sar_i32, 1, 2, 0, 0)
[Qemu-devel] [PATCH 1/7] tcg: Define "deposit" as an optional operation.
Signed-off-by: Richard Henderson
---
tcg/README| 14
tcg/tcg-op.h | 64 +
tcg/tcg-opc.h |6 +
3 files changed, 84 insertions(+), 0 deletions(-)
diff --git a/tcg/README b/tcg/README
index a18a87f..a50ecc6 100644
--- a/tcg/README
+++ b/tcg/README
@@ -285,6 +285,20 @@ the four high order bytes are set to zero.
Indicate that the value of t0 won't be used later. It is useful to
force dead code elimination.
+* deposit_i32/i64 dest, t1, t2, pos, loc
+
+Deposit T2 as a bitfield into T1, placing the result in DEST.
+The bitfield is described by POS/LOC, which are immediate values:
+
+ LEN - the length of the bitfield
+ POS - the position of the first bit, counting from the LSB
+
+For example, pos=8, len=4 indicates a 4-bit field at bit 8.
+This operation would be equivalent to
+
+ dest = (t1 & ~0x0f00) | ((t2 << 8) & 0x0f00)
+
+
* Conditional moves
* setcond_i32/i64 cond, dest, t1, t2
diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
index 3ee0a58..207a89f 100644
--- a/tcg/tcg-op.h
+++ b/tcg/tcg-op.h
@@ -254,6 +254,30 @@ static inline void tcg_gen_op5i_i64(TCGOpcode opc,
TCGv_i64 arg1, TCGv_i64 arg2,
*gen_opparam_ptr++ = arg5;
}
+static inline void tcg_gen_op5ii_i32(TCGOpcode opc, TCGv_i32 arg1,
+ TCGv_i32 arg2, TCGv_i32 arg3,
+ TCGArg arg4, TCGArg arg5)
+{
+*gen_opc_ptr++ = opc;
+*gen_opparam_ptr++ = GET_TCGV_I32(arg1);
+*gen_opparam_ptr++ = GET_TCGV_I32(arg2);
+*gen_opparam_ptr++ = GET_TCGV_I32(arg3);
+*gen_opparam_ptr++ = arg4;
+*gen_opparam_ptr++ = arg5;
+}
+
+static inline void tcg_gen_op5ii_i64(TCGOpcode opc, TCGv_i64 arg1,
+ TCGv_i64 arg2, TCGv_i64 arg3,
+ TCGArg arg4, TCGArg arg5)
+{
+*gen_opc_ptr++ = opc;
+*gen_opparam_ptr++ = GET_TCGV_I64(arg1);
+*gen_opparam_ptr++ = GET_TCGV_I64(arg2);
+*gen_opparam_ptr++ = GET_TCGV_I64(arg3);
+*gen_opparam_ptr++ = arg4;
+*gen_opparam_ptr++ = arg5;
+}
+
static inline void tcg_gen_op6_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2,
TCGv_i32 arg3, TCGv_i32 arg4, TCGv_i32 arg5,
TCGv_i32 arg6)
@@ -2071,6 +2095,44 @@ static inline void tcg_gen_rotri_i64(TCGv_i64 ret,
TCGv_i64 arg1, int64_t arg2)
}
}
+static inline void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1,
+ TCGv_i32 arg2, unsigned int ofs,
+ unsigned int len)
+{
+#ifdef TCG_TARGET_HAS_deposit_i32
+ tcg_gen_op5ii_i32(INDEX_op_deposit_i32, ret, arg1, arg2, ofs, len);
+#else
+ uint32_t mask = (1u << len) - 1;
+ TCGv_i32 t1 = tcg_temp_new_i32 ();
+
+ tcg_gen_andi_i32(t1, arg2, mask);
+ tcg_gen_shli_i32(t1, t1, ofs);
+ tcg_gen_andi_i32(ret, arg1, ~(mask << ofs));
+ tcg_gen_or_i32(ret, ret, t1);
+
+ tcg_temp_free_i32(t1);
+#endif
+}
+
+static inline void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1,
+ TCGv_i64 arg2, unsigned int ofs,
+ unsigned int len)
+{
+#ifdef TCG_TARGET_HAS_deposit_i64
+ tcg_gen_op5ii_i64(INDEX_op_deposit_i64, ret, arg1, arg2, ofs, len);
+#else
+ uint64_t mask = (1ull << len) - 1;
+ TCGv_i64 t1 = tcg_temp_new_i64 ();
+
+ tcg_gen_andi_i64(t1, arg2, mask);
+ tcg_gen_shli_i64(t1, t1, ofs);
+ tcg_gen_andi_i64(ret, arg1, ~(mask << ofs));
+ tcg_gen_or_i64(ret, ret, t1);
+
+ tcg_temp_free_i64(t1);
+#endif
+}
+
/***/
/* QEMU specific operations. Their type depend on the QEMU CPU
type. */
@@ -2384,6 +2446,7 @@ static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv
addr, int mem_index)
#define tcg_gen_rotli_tl tcg_gen_rotli_i64
#define tcg_gen_rotr_tl tcg_gen_rotr_i64
#define tcg_gen_rotri_tl tcg_gen_rotri_i64
+#define tcg_gen_deposit_tl tcg_gen_deposit_i64
#define tcg_const_tl tcg_const_i64
#define tcg_const_local_tl tcg_const_local_i64
#else
@@ -2454,6 +2517,7 @@ static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv
addr, int mem_index)
#define tcg_gen_rotli_tl tcg_gen_rotli_i32
#define tcg_gen_rotr_tl tcg_gen_rotr_i32
#define tcg_gen_rotri_tl tcg_gen_rotri_i32
+#define tcg_gen_deposit_tl tcg_gen_deposit_i32
#define tcg_const_tl tcg_const_i32
#define tcg_const_local_tl tcg_const_local_i32
#endif
diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h
index 2a98fed..2c7ca1a 100644
--- a/tcg/tcg-opc.h
+++ b/tcg/tcg-opc.h
@@ -78,6 +78,9 @@ DEF(sar_i32, 1, 2, 0, 0)
DEF(rotl_i32, 1, 2, 0, 0)
DEF(rotr_i32, 1, 2, 0, 0)
#endif
+#ifdef TCG_TARGET_HAS_deposit_i32
+DEF(deposit_i32, 1, 2, 2, 0)
+#endif
DEF(brcond_i32, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
#if TCG_TARGET_REG_BITS == 32
@@ -168,6 +171,9 @@ DEF(sar_i64, 1, 2, 0, 0)
DEF(rotl_i64, 1, 2, 0, 0)
DEF(rotr_i64, 1, 2, 0, 0)
#endif
+#ifdef
Re: [Qemu-devel] [PATCH 1/7] tcg: Define "deposit" as an optional operation.
On 01/09/2011 01:38 PM, Aurelien Jarno wrote: > The encoding of the constant part actually doesn't match the one in the > C function where two arguments are separated and not encoded. What about > adding a tcg_gen_op5ii_i32/64 function and having the two arguments > separated? I certainly didn't want to expose the combined argument to the target translators. I had thought that saving some memory by combining the two constants would be a good idea, but perhaps you're right that it's overly complicated for the benefit. > Also what about a shorter name, like for example 'dep' as it is used on > some architectures. I suppose. I thought perhaps that would be too cryptic though. r~
Re: [Qemu-devel] [PATCH 1/7] tcg: Define "deposit" as an optional operation.
On Fri, Jan 07, 2011 at 02:42:57PM -0800, Richard Henderson wrote:
> Signed-off-by: Richard Henderson
> ---
> tcg/README| 14 ++
> tcg/tcg-op.h | 40
> tcg/tcg-opc.h |6 ++
> tcg/tcg.c | 13 +
> 4 files changed, 73 insertions(+), 0 deletions(-)
>
> diff --git a/tcg/README b/tcg/README
> index 68d27ff..ef59070 100644
> --- a/tcg/README
> +++ b/tcg/README
> @@ -285,6 +285,20 @@ the four high order bytes are set to zero.
> Indicate that the value of t0 won't be used later. It is useful to
> force dead code elimination.
>
> +* deposit_i32/i64 dest, t1, t2, loc
> +
> +Deposit T2 as a bitfield into T1, placing the result in DEST.
> +The bitfield is described by LOC, an immediate value:
> +
> + bits 0:7 - the length of the bitfield
> + bits 8:15 - the position of the first bit
> +
> +For example, 0x101 indicates a 1-bit field at bit 1.
> +This operation would be equivalent to
> +
> + dest = (t1 & ~2) | ((t2 << 1) & 2)
> +
> +
The encoding of the constant part actually doesn't match the one in the
C function where two arguments are separated and not encoded. What about
adding a tcg_gen_op5ii_i32/64 function and having the two arguments
separated?
Also what about a shorter name, like for example 'dep' as it is used on
some architectures.
> * Conditional moves
>
> * setcond_i32/i64 cond, dest, t1, t2
> diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
> index 3ee0a58..c5a019a 100644
> --- a/tcg/tcg-op.h
> +++ b/tcg/tcg-op.h
> @@ -2071,6 +2071,44 @@ static inline void tcg_gen_rotri_i64(TCGv_i64 ret,
> TCGv_i64 arg1, int64_t arg2)
> }
> }
>
> +static inline void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1,
> +TCGv_i32 arg2, unsigned int ofs,
> +unsigned int len)
> +{
> +#ifdef TCG_TARGET_HAS_deposit_i32
> + tcg_gen_op4i_i32(INDEX_op_deposit_i32, ret, arg1, arg2, (ofs << 8) | len);
> +#else
> + uint32_t mask = (1u << len) - 1;
> + TCGv_i32 t1 = tcg_temp_new_i32 ();
> +
> + tcg_gen_andi_i32(t1, arg2, mask);
> + tcg_gen_shli_i32(t1, t1, ofs);
> + tcg_gen_andi_i32(ret, arg1, ~(mask << ofs));
> + tcg_gen_or_i32(ret, ret, t1);
> +
> + tcg_temp_free_i32(t1);
> +#endif
> +}
> +
> +static inline void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1,
> +TCGv_i64 arg2, unsigned int ofs,
> +unsigned int len)
> +{
> +#ifdef TCG_TARGET_HAS_deposit_i64
> + tcg_gen_op4i_i64(INDEX_op_deposit_i64, ret, arg1, arg2, (ofs << 8) | len);
> +#else
> + uint64_t mask = (1ull << len) - 1;
> + TCGv_i64 t1 = tcg_temp_new_i64 ();
> +
> + tcg_gen_andi_i64(t1, arg2, mask);
> + tcg_gen_shli_i64(t1, t1, ofs);
> + tcg_gen_andi_i64(ret, arg1, ~(mask << ofs));
> + tcg_gen_or_i64(ret, ret, t1);
> +
> + tcg_temp_free_i64(t1);
> +#endif
> +}
> +
> /***/
> /* QEMU specific operations. Their type depend on the QEMU CPU
> type. */
> @@ -2384,6 +2422,7 @@ static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv
> addr, int mem_index)
> #define tcg_gen_rotli_tl tcg_gen_rotli_i64
> #define tcg_gen_rotr_tl tcg_gen_rotr_i64
> #define tcg_gen_rotri_tl tcg_gen_rotri_i64
> +#define tcg_gen_deposit_tl tcg_gen_deposit_i64
> #define tcg_const_tl tcg_const_i64
> #define tcg_const_local_tl tcg_const_local_i64
> #else
> @@ -2454,6 +2493,7 @@ static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv
> addr, int mem_index)
> #define tcg_gen_rotli_tl tcg_gen_rotli_i32
> #define tcg_gen_rotr_tl tcg_gen_rotr_i32
> #define tcg_gen_rotri_tl tcg_gen_rotri_i32
> +#define tcg_gen_deposit_tl tcg_gen_deposit_i32
> #define tcg_const_tl tcg_const_i32
> #define tcg_const_local_tl tcg_const_local_i32
> #endif
> diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h
> index 2a98fed..ded6311 100644
> --- a/tcg/tcg-opc.h
> +++ b/tcg/tcg-opc.h
> @@ -78,6 +78,9 @@ DEF(sar_i32, 1, 2, 0, 0)
> DEF(rotl_i32, 1, 2, 0, 0)
> DEF(rotr_i32, 1, 2, 0, 0)
> #endif
> +#ifdef TCG_TARGET_HAS_deposit_i32
> +DEF(deposit_i32, 1, 2, 1, 0)
> +#endif
>
> DEF(brcond_i32, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
> #if TCG_TARGET_REG_BITS == 32
> @@ -168,6 +171,9 @@ DEF(sar_i64, 1, 2, 0, 0)
> DEF(rotl_i64, 1, 2, 0, 0)
> DEF(rotr_i64, 1, 2, 0, 0)
> #endif
> +#ifdef TCG_TARGET_HAS_deposit_i64
> +DEF(deposit_i64, 1, 2, 1, 0)
> +#endif
>
> DEF(brcond_i64, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
> #ifdef TCG_TARGET_HAS_ext8s_i64
> diff --git a/tcg/tcg.c b/tcg/tcg.c
> index 5dd6a2c..e95a42f 100644
> --- a/tcg/tcg.c
> +++ b/tcg/tcg.c
> @@ -956,6 +956,19 @@ void tcg_dump_ops(TCGContext *s, FILE *outfile)
> fprintf(outfile, ",$0x%" TCG_PRIlx, args[k++]);
> i = 1;
> break;
> +#if defined(TCG_TARGET_HAS_deposit_i32) ||
> defined(TCG_TARGET_HAS_deposit_i64)
> +# ifdef TCG_TARGET_HAS_deposit_i32
> +case
Re: [Qemu-devel] [PATCH 1/7] tcg: Define "deposit" as an optional operation.
On Fri, Jan 07, 2011 at 02:42:57PM -0800, Richard Henderson wrote: > Signed-off-by: Richard Henderson > --- > tcg/README| 14 ++ > tcg/tcg-op.h | 40 > tcg/tcg-opc.h |6 ++ > tcg/tcg.c | 13 + > 4 files changed, 73 insertions(+), 0 deletions(-) > > diff --git a/tcg/README b/tcg/README > index 68d27ff..ef59070 100644 > --- a/tcg/README > +++ b/tcg/README > @@ -285,6 +285,20 @@ the four high order bytes are set to zero. > Indicate that the value of t0 won't be used later. It is useful to > force dead code elimination. > > +* deposit_i32/i64 dest, t1, t2, loc > + > +Deposit T2 as a bitfield into T1, placing the result in DEST. > +The bitfield is described by LOC, an immediate value: > + > + bits 0:7 - the length of the bitfield > + bits 8:15 - the position of the first bit > + > +For example, 0x101 indicates a 1-bit field at bit 1. > +This operation would be equivalent to > + > + dest = (t1 & ~2) | ((t2 << 1) & 2) I'm being rather picky, but would something like this be better? :- For example, 0x804 indicates a 4-bit field starting from bit 8. This operation would be equivalent to: dest = (t1 & ~(0xf << 8)) | ((t2 << 8) & (0xf << 8)) OTOH, the code in your version was simpler... so maybe 0x201 or 0x102 as a compromise? I suppose it's unlikely that anyone's really going to need the example though, so I'm probably fussing too much. :-) Cheers, -- Stuart Brady
[Qemu-devel] [PATCH 1/7] tcg: Define "deposit" as an optional operation.
Signed-off-by: Richard Henderson
---
tcg/README| 14 ++
tcg/tcg-op.h | 40
tcg/tcg-opc.h |6 ++
tcg/tcg.c | 13 +
4 files changed, 73 insertions(+), 0 deletions(-)
diff --git a/tcg/README b/tcg/README
index 68d27ff..ef59070 100644
--- a/tcg/README
+++ b/tcg/README
@@ -285,6 +285,20 @@ the four high order bytes are set to zero.
Indicate that the value of t0 won't be used later. It is useful to
force dead code elimination.
+* deposit_i32/i64 dest, t1, t2, loc
+
+Deposit T2 as a bitfield into T1, placing the result in DEST.
+The bitfield is described by LOC, an immediate value:
+
+ bits 0:7 - the length of the bitfield
+ bits 8:15 - the position of the first bit
+
+For example, 0x101 indicates a 1-bit field at bit 1.
+This operation would be equivalent to
+
+ dest = (t1 & ~2) | ((t2 << 1) & 2)
+
+
* Conditional moves
* setcond_i32/i64 cond, dest, t1, t2
diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
index 3ee0a58..c5a019a 100644
--- a/tcg/tcg-op.h
+++ b/tcg/tcg-op.h
@@ -2071,6 +2071,44 @@ static inline void tcg_gen_rotri_i64(TCGv_i64 ret,
TCGv_i64 arg1, int64_t arg2)
}
}
+static inline void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1,
+ TCGv_i32 arg2, unsigned int ofs,
+ unsigned int len)
+{
+#ifdef TCG_TARGET_HAS_deposit_i32
+ tcg_gen_op4i_i32(INDEX_op_deposit_i32, ret, arg1, arg2, (ofs << 8) | len);
+#else
+ uint32_t mask = (1u << len) - 1;
+ TCGv_i32 t1 = tcg_temp_new_i32 ();
+
+ tcg_gen_andi_i32(t1, arg2, mask);
+ tcg_gen_shli_i32(t1, t1, ofs);
+ tcg_gen_andi_i32(ret, arg1, ~(mask << ofs));
+ tcg_gen_or_i32(ret, ret, t1);
+
+ tcg_temp_free_i32(t1);
+#endif
+}
+
+static inline void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1,
+ TCGv_i64 arg2, unsigned int ofs,
+ unsigned int len)
+{
+#ifdef TCG_TARGET_HAS_deposit_i64
+ tcg_gen_op4i_i64(INDEX_op_deposit_i64, ret, arg1, arg2, (ofs << 8) | len);
+#else
+ uint64_t mask = (1ull << len) - 1;
+ TCGv_i64 t1 = tcg_temp_new_i64 ();
+
+ tcg_gen_andi_i64(t1, arg2, mask);
+ tcg_gen_shli_i64(t1, t1, ofs);
+ tcg_gen_andi_i64(ret, arg1, ~(mask << ofs));
+ tcg_gen_or_i64(ret, ret, t1);
+
+ tcg_temp_free_i64(t1);
+#endif
+}
+
/***/
/* QEMU specific operations. Their type depend on the QEMU CPU
type. */
@@ -2384,6 +2422,7 @@ static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv
addr, int mem_index)
#define tcg_gen_rotli_tl tcg_gen_rotli_i64
#define tcg_gen_rotr_tl tcg_gen_rotr_i64
#define tcg_gen_rotri_tl tcg_gen_rotri_i64
+#define tcg_gen_deposit_tl tcg_gen_deposit_i64
#define tcg_const_tl tcg_const_i64
#define tcg_const_local_tl tcg_const_local_i64
#else
@@ -2454,6 +2493,7 @@ static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv
addr, int mem_index)
#define tcg_gen_rotli_tl tcg_gen_rotli_i32
#define tcg_gen_rotr_tl tcg_gen_rotr_i32
#define tcg_gen_rotri_tl tcg_gen_rotri_i32
+#define tcg_gen_deposit_tl tcg_gen_deposit_i32
#define tcg_const_tl tcg_const_i32
#define tcg_const_local_tl tcg_const_local_i32
#endif
diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h
index 2a98fed..ded6311 100644
--- a/tcg/tcg-opc.h
+++ b/tcg/tcg-opc.h
@@ -78,6 +78,9 @@ DEF(sar_i32, 1, 2, 0, 0)
DEF(rotl_i32, 1, 2, 0, 0)
DEF(rotr_i32, 1, 2, 0, 0)
#endif
+#ifdef TCG_TARGET_HAS_deposit_i32
+DEF(deposit_i32, 1, 2, 1, 0)
+#endif
DEF(brcond_i32, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
#if TCG_TARGET_REG_BITS == 32
@@ -168,6 +171,9 @@ DEF(sar_i64, 1, 2, 0, 0)
DEF(rotl_i64, 1, 2, 0, 0)
DEF(rotr_i64, 1, 2, 0, 0)
#endif
+#ifdef TCG_TARGET_HAS_deposit_i64
+DEF(deposit_i64, 1, 2, 1, 0)
+#endif
DEF(brcond_i64, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
#ifdef TCG_TARGET_HAS_ext8s_i64
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 5dd6a2c..e95a42f 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -956,6 +956,19 @@ void tcg_dump_ops(TCGContext *s, FILE *outfile)
fprintf(outfile, ",$0x%" TCG_PRIlx, args[k++]);
i = 1;
break;
+#if defined(TCG_TARGET_HAS_deposit_i32) || defined(TCG_TARGET_HAS_deposit_i64)
+# ifdef TCG_TARGET_HAS_deposit_i32
+case INDEX_op_deposit_i32:
+# endif
+# ifdef TCG_TARGET_HAS_deposit_i64
+case INDEX_op_deposit_i64:
+# endif
+fprintf(outfile, ",%u,%u", (unsigned)args[k] >> 8,
+(unsigned)args[k] & 0xff);
+k++;
+i = 1;
+break;
+#endif
default:
i = 0;
break;
--
1.7.2.3
