[Qemu-devel] [PATCH 7/7] target-ppc: Use deposit operation.

[Richard Henderson]

Use this in implementing rl[wd]imi, at least for the cases
that don't require true rotation.

Signed-off-by: Richard Henderson 
---
 target-ppc/translate.c |   10 ++
 1 files changed, 10 insertions(+), 0 deletions(-)

diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 74e06d7..f45c0ec 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -1516,6 +1516,11 @@ static void gen_rlwimi(DisasContext *ctx)
 sh = SH(ctx->opcode);
 if (likely(sh == 0 && mb == 0 && me == 31)) {
 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
+} else if ((31 - me) == sh && mb <= me) {
+/* This is a well-behaved bitfield deposit.  */
+tcg_gen_deposit_tl (cpu_gpr[rA(ctx->opcode)],
+cpu_gpr[rA(ctx->opcode)],
+cpu_gpr[rS(ctx->opcode)], sh, me - mb + 1);
 } else {
 target_ulong mask;
 TCGv t1;
@@ -1761,6 +1766,11 @@ static inline void gen_rldimi(DisasContext *ctx, int 
mbn, int shn)
 me = 63 - sh;
 if (unlikely(sh == 0 && mb == 0)) {
 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
+} else if (mb <= me) {
+/* This is a well-behaved bitfield deposit.  */
+tcg_gen_deposit_tl (cpu_gpr[rA(ctx->opcode)],
+cpu_gpr[rA(ctx->opcode)],
+cpu_gpr[rS(ctx->opcode)], sh, me - mb + 1);
 } else {
 TCGv t0, t1;
 target_ulong mask;
-- 
1.7.2.3

[Qemu-devel] [PATCH 7/7] target-ppc: Use deposit operation.

[Richard Henderson]

Use this in implementing rl[wd]imi, at least for the cases
that don't require true rotation.

Signed-off-by: Richard Henderson 
---
 target-ppc/translate.c |   10 ++
 1 files changed, 10 insertions(+), 0 deletions(-)

diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 74e06d7..f45c0ec 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -1516,6 +1516,11 @@ static void gen_rlwimi(DisasContext *ctx)
 sh = SH(ctx->opcode);
 if (likely(sh == 0 && mb == 0 && me == 31)) {
 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
+} else if ((31 - me) == sh && mb <= me) {
+/* This is a well-behaved bitfield deposit.  */
+tcg_gen_deposit_tl (cpu_gpr[rA(ctx->opcode)],
+cpu_gpr[rA(ctx->opcode)],
+cpu_gpr[rS(ctx->opcode)], sh, me - mb + 1);
 } else {
 target_ulong mask;
 TCGv t1;
@@ -1761,6 +1766,11 @@ static inline void gen_rldimi(DisasContext *ctx, int 
mbn, int shn)
 me = 63 - sh;
 if (unlikely(sh == 0 && mb == 0)) {
 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
+} else if (mb <= me) {
+/* This is a well-behaved bitfield deposit.  */
+tcg_gen_deposit_tl (cpu_gpr[rA(ctx->opcode)],
+cpu_gpr[rA(ctx->opcode)],
+cpu_gpr[rS(ctx->opcode)], sh, me - mb + 1);
 } else {
 TCGv t0, t1;
 target_ulong mask;
-- 
1.7.2.3