Re: [Qemu-devel] [PATCH for-4.1 v2 00/13] tcg/ppc: Add vector opcodes

2019-03-17 Thread no-reply
Patchew URL: 
https://patchew.org/QEMU/20190317090834.5552-1-richard.hender...@linaro.org/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Subject: [Qemu-devel] [PATCH for-4.1 v2 00/13] tcg/ppc: Add vector opcodes
Type: series
Message-id: 20190317090834.5552-1-richard.hender...@linaro.org

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 * [new tag]   
patchew/20190317090834.5552-1-richard.hender...@linaro.org -> 
patchew/20190317090834.5552-1-richard.hender...@linaro.org
Switched to a new branch 'test'
9e9ef28e00 tcg/ppc: Update vector support to v3.00
e805447820 tcg/ppc: Update vector support to v2.07
29a048fa5c tcg/ppc: Update vector support to v2.06
702b53e3fe tcg/ppc: Support vector multiply
2ba329a816 tcg/ppc: Support vector shift by immediate
5e65162310 tcg/ppc: Implement INDEX_op_dupm_vec
3446564d5b tcg: Add INDEX_op_dup_mem_vec
f7bd30e149 tcg/ppc: Initial backend support for Altivec
593da57da7 target/arm: Fill in .opc for cmtst_op
18026c831d tcg: Allow add_vec, sub_vec, neg_vec, not_vec to be expanded
378fdc5169 tcg: Support cross-class moves without instruction support
b7b9445e8a tcg: Return bool success from tcg_out_mov
4a8963a14a tcg: Assert fixed_reg is read-only

=== OUTPUT BEGIN ===
1/13 Checking commit 4a8963a14ab4 (tcg: Assert fixed_reg is read-only)
WARNING: Block comments use a leading /* on a separate line
#102: FILE: tcg/tcg.c:3529:
+/* temp value is modified, so the value kept in memory is

WARNING: Block comments use * on subsequent lines
#103: FILE: tcg/tcg.c:3530:
+/* temp value is modified, so the value kept in memory is
+   potentially not the same */

WARNING: Block comments use a trailing */ on a separate line
#103: FILE: tcg/tcg.c:3530:
+   potentially not the same */

total: 0 errors, 3 warnings, 140 lines checked

Patch 1/13 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
2/13 Checking commit b7b9445e8a4f (tcg: Return bool success from tcg_out_mov)
3/13 Checking commit 378fdc51691e (tcg: Support cross-class moves without 
instruction support)
WARNING: Block comments use a leading /* on a separate line
#23: FILE: tcg/tcg.c:3372:
+/* Cross register class move not supported.

WARNING: Block comments use * on subsequent lines
#24: FILE: tcg/tcg.c:3373:
+/* Cross register class move not supported.
+   Store the source register into the destination slot

WARNING: Block comments use a trailing */ on a separate line
#25: FILE: tcg/tcg.c:3374:
+   and leave the destination temp as TEMP_VAL_MEM.  */

WARNING: Block comments use a leading /* on a separate line
#43: FILE: tcg/tcg.c:3485:
+/* Cross register class move not supported.  Sync the

WARNING: Block comments use * on subsequent lines
#44: FILE: tcg/tcg.c:3486:
+/* Cross register class move not supported.  Sync the
+   temp back to its slot and load from there.  */

WARNING: Block comments use a trailing */ on a separate line
#44: FILE: tcg/tcg.c:3486:
+   temp back to its slot and load from there.  */

WARNING: Block comments use a leading /* on a separate line
#56: FILE: tcg/tcg.c:3648:
+/* Cross register class move not supported.  Sync the

WARNING: Block comments use * on subsequent lines
#57: FILE: tcg/tcg.c:3649:
+/* Cross register class move not supported.  Sync the
+   temp back to its slot and load from there.  */

WARNING: Block comments use a trailing */ on a separate line
#57: FILE: tcg/tcg.c:3649:
+   temp back to its slot and load from there.  */

total: 0 errors, 9 warnings, 43 lines checked

Patch 3/13 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
4/13 Checking commit 18026c831d0e (tcg: Allow add_vec, sub_vec, neg_vec, 
not_vec to be expanded)
5/13 Checking commit 593da57da76b (target/arm: Fill in .opc for cmtst_op)
6/13 Checking commit f7bd30e149b0 (tcg/ppc: Initial backend support for Altivec)
ERROR: spaces required around that '|' (ctx:VxV)
#187: FILE: tcg/ppc/tcg-target.inc.c:327:
+#define VX4(opc)  (OPCD(4)|(opc))
   ^

ERROR: trailing whitespace
#541: FILE: tcg/ppc/tcg-target.inc.c:2871:
+umin_op[4] = { VMINUB, VMINUH, VMINUW, 0 }, $

ERROR: trailing whitespace
#542: FILE: tcg/ppc/tcg-target.inc.c:2872:
+smin_op[4] = {

[Qemu-devel] [PATCH for-4.1 v2 00/13] tcg/ppc: Add vector opcodes

2019-03-17 Thread Richard Henderson
Version 2 does not require VSX, and works with just Altivec.
But the last 3 patches incrementally add Power7/8/9 instructions.

I've tested this vs aa64 risu on power7 big-endian and power9
little-endian, so all of the easy bugs are out.  ;-)


r~


Richard Henderson (13):
  tcg: Assert fixed_reg is read-only
  tcg: Return bool success from tcg_out_mov
  tcg: Support cross-class moves without instruction support
  tcg: Allow add_vec, sub_vec, neg_vec, not_vec to be expanded
  target/arm: Fill in .opc for cmtst_op
  tcg/ppc: Initial backend support for Altivec
  tcg: Add INDEX_op_dup_mem_vec
  tcg/ppc: Implement INDEX_op_dupm_vec
  tcg/ppc: Support vector shift by immediate
  tcg/ppc: Support vector multiply
  tcg/ppc: Update vector support to v2.06
  tcg/ppc: Update vector support to v2.07
  tcg/ppc: Update vector support to v3.00

 tcg/aarch64/tcg-target.h |1 +
 tcg/i386/tcg-target.h|1 +
 tcg/ppc/tcg-target.h |   34 +-
 tcg/ppc/tcg-target.opc.h |   11 +
 tcg/tcg-op.h |1 +
 tcg/tcg-opc.h|1 +
 tcg/tcg.h|1 +
 target/arm/translate.c   |4 +
 tcg/aarch64/tcg-target.inc.c |5 +-
 tcg/arm/tcg-target.inc.c |7 +-
 tcg/i386/tcg-target.inc.c|5 +-
 tcg/mips/tcg-target.inc.c|3 +-
 tcg/ppc/tcg-target.inc.c | 1039 --
 tcg/riscv/tcg-target.inc.c   |5 +-
 tcg/s390/tcg-target.inc.c|3 +-
 tcg/sparc/tcg-target.inc.c   |3 +-
 tcg/tcg-op-gvec.c|   88 +--
 tcg/tcg-op-vec.c |   60 +-
 tcg/tcg.c|  120 ++--
 tcg/tci/tcg-target.inc.c |3 +-
 20 files changed, 1212 insertions(+), 183 deletions(-)
 create mode 100644 tcg/ppc/tcg-target.opc.h

-- 
2.17.2